^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Abilis Systems TB10x pin control driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) Abilis Systems 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Christian Ruppert <christian.ruppert@abilis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TB10X_PORT1 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TB10X_PORT2 (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TB10X_PORT3 (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TB10X_PORT4 (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TB10X_PORT5 (128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TB10X_PORT6 (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TB10X_PORT7 (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TB10X_PORT8 (96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TB10X_PORT9 (112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TB10X_GPIOS (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCFG_PORT_BITWIDTH (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCFG_PORT_MASK(PORT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct pinctrl_pin_desc tb10x_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Port 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Port 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Port 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Port 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Port 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Port 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Unmuxed GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MAX_PIN (TB10X_GPIOS + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(MAX_PIN, "GPION4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TB10X_PORT1 + 2, TB10X_PORT1 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TB10X_PORT1 + 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TB10X_PORT1 + 9, TB10X_PORT1 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TB10X_PORT1 + 2, TB10X_PORT1 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TB10X_PORT1 + 4, TB10X_PORT1 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TB10X_PORT1 + 6, TB10X_PORT1 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TB10X_PORT1 + 8, TB10X_PORT1 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) TB10X_PORT1 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) TB10X_PORT2 + 2, TB10X_PORT2 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TB10X_PORT2 + 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TB10X_PORT2 + 9, TB10X_PORT2 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) TB10X_PORT2 + 2, TB10X_PORT2 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TB10X_PORT2 + 4, TB10X_PORT2 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) TB10X_PORT2 + 6, TB10X_PORT2 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TB10X_PORT2 + 8, TB10X_PORT2 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TB10X_PORT2 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TB10X_PORT3 + 2, TB10X_PORT3 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TB10X_PORT3 + 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TB10X_PORT3 + 9, TB10X_PORT3 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TB10X_PORT3 + 2, TB10X_PORT3 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TB10X_PORT3 + 4, TB10X_PORT3 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TB10X_PORT3 + 6, TB10X_PORT3 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) TB10X_PORT3 + 8, TB10X_PORT3 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TB10X_PORT3 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Port 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TB10X_PORT4 + 2, TB10X_PORT4 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TB10X_PORT4 + 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) TB10X_PORT4 + 9, TB10X_PORT4 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) TB10X_PORT4 + 2, TB10X_PORT4 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TB10X_PORT4 + 4, TB10X_PORT4 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) TB10X_PORT4 + 6, TB10X_PORT4 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) TB10X_PORT4 + 8, TB10X_PORT4 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) TB10X_PORT4 + 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Port 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) TB10X_PORT6 + 2, TB10X_PORT6 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TB10X_PORT6 + 4, TB10X_PORT6 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) TB10X_PORT6 + 6, TB10X_PORT6 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) TB10X_PORT6 + 8, TB10X_PORT6 + 9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) TB10X_PORT6 + 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TB10X_PORT6 + 5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TB10X_PORT6 + 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned mos3_pins[] = { TB10X_PORT6 + 9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Port 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) TB10X_PORT7 + 2, TB10X_PORT7 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) TB10X_PORT7 + 6, TB10X_PORT7 + 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) TB10X_PORT7 + 2, TB10X_PORT7 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TB10X_PORT7 + 6, TB10X_PORT7 + 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Port 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) TB10X_PORT8 + 2, TB10X_PORT8 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) TB10X_PORT8 + 2, TB10X_PORT8 + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Port 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) TB10X_PORT9 + 2, TB10X_PORT9 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) TB10X_PORT9 + 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) TB10X_PORT9 + 2, TB10X_PORT9 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TB10X_PORT9 + 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Port 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) TB10X_PORT5 + 2, TB10X_PORT5 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) TB10X_PORT5 + 4, TB10X_PORT5 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) TB10X_PORT5 + 6, TB10X_PORT5 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) TB10X_PORT5 + 8, TB10X_PORT5 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) TB10X_PORT5 + 10, TB10X_PORT5 + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) TB10X_PORT5 + 12, TB10X_PORT5 + 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) TB10X_PORT5 + 14, TB10X_PORT5 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) TB10X_PORT5 + 16, TB10X_PORT5 + 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) TB10X_PORT5 + 18, TB10X_PORT5 + 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) TB10X_PORT5 + 20, TB10X_PORT5 + 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) TB10X_PORT5 + 22, TB10X_PORT5 + 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) TB10X_PORT5 + 24, TB10X_PORT5 + 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) TB10X_PORT5 + 26, TB10X_PORT5 + 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) TB10X_PORT5 + 28, TB10X_PORT5 + 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) TB10X_PORT5 + 30, TB10X_PORT5 + 31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TB10X_PORT5 + 34, TB10X_PORT5 + 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) TB10X_PORT5 + 36, TB10X_PORT5 + 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) TB10X_PORT5 + 38, TB10X_PORT5 + 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) TB10X_PORT5 + 40, TB10X_PORT5 + 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TB10X_PORT5 + 42, TB10X_PORT5 + 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TB10X_PORT5 + 44, TB10X_PORT5 + 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) TB10X_PORT5 + 46, TB10X_PORT5 + 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) TB10X_PORT5 + 48, TB10X_PORT5 + 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) TB10X_PORT5 + 50, TB10X_PORT5 + 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) TB10X_PORT5 + 52, TB10X_PORT5 + 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) TB10X_PORT5 + 2, TB10X_PORT5 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) TB10X_PORT5 + 4, TB10X_PORT5 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) TB10X_PORT5 + 6, TB10X_PORT5 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) TB10X_PORT5 + 8, TB10X_PORT5 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) TB10X_PORT5 + 10, TB10X_PORT5 + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) TB10X_PORT5 + 12, TB10X_PORT5 + 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) TB10X_PORT5 + 14, TB10X_PORT5 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) TB10X_PORT5 + 16, TB10X_PORT5 + 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) TB10X_PORT5 + 18, TB10X_PORT5 + 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) TB10X_PORT5 + 20, TB10X_PORT5 + 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) TB10X_PORT5 + 22, TB10X_PORT5 + 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) TB10X_PORT5 + 24, TB10X_PORT5 + 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) TB10X_PORT5 + 26, TB10X_PORT5 + 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) TB10X_PORT5 + 28, TB10X_PORT5 + 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) TB10X_PORT5 + 30, TB10X_PORT5 + 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) TB10X_PORT5 + 32, TB10X_PORT5 + 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) TB10X_PORT5 + 34, TB10X_PORT5 + 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) TB10X_PORT5 + 36, TB10X_PORT5 + 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) TB10X_PORT5 + 38, TB10X_PORT5 + 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) TB10X_PORT5 + 40, TB10X_PORT5 + 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TB10X_PORT5 + 42, TB10X_PORT5 + 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TB10X_PORT5 + 44, TB10X_PORT5 + 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TB10X_PORT5 + 46, TB10X_PORT5 + 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) TB10X_PORT5 + 48, TB10X_PORT5 + 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) TB10X_PORT5 + 50, TB10X_PORT5 + 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) TB10X_PORT5 + 52, TB10X_PORT5 + 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TB10X_PORT5 + 11, TB10X_PORT5 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TB10X_PORT5 + 22, TB10X_PORT5 + 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) TB10X_PORT5 + 33, TB10X_PORT5 + 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) TB10X_PORT5 + 36, TB10X_PORT5 + 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) TB10X_PORT5 + 38, TB10X_PORT5 + 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) TB10X_PORT5 + 40, TB10X_PORT5 + 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TB10X_PORT5 + 42, TB10X_PORT5 + 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) TB10X_PORT5 + 45, TB10X_PORT5 + 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) TB10X_PORT5 + 47, TB10X_PORT5 + 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) TB10X_PORT5 + 49, TB10X_PORT5 + 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TB10X_PORT5 + 51, TB10X_PORT5 + 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) TB10X_PORT5 + 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TB10X_PORT5 + 36, TB10X_PORT5 + 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) TB10X_PORT5 + 38, TB10X_PORT5 + 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) TB10X_PORT5 + 40};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) TB10X_PORT5 + 27, TB10X_PORT5 + 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) TB10X_PORT5 + 29, TB10X_PORT5 + 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) TB10X_PORT5 + 44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Unmuxed GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TB10X_GPIOS + 10, TB10X_GPIOS + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) TB10X_GPIOS + 12, TB10X_GPIOS + 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) TB10X_GPIOS + 14, TB10X_GPIOS + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TB10X_GPIOS + 16, TB10X_GPIOS + 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) TB10X_GPIOS + 18, TB10X_GPIOS + 19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct tb10x_pinfuncgrp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const unsigned int pincnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) const unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const int isgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = __stringify(NAME), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .port = (PORT), .mode = (MODE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .isgpio = (ISGPIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct tb10x_pinfuncgrp tb10x_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DEFPINFUNCGRP(mis0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DEFPINFUNCGRP(gpioa, 0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DEFPINFUNCGRP(mis1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEFPINFUNCGRP(mip1, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DEFPINFUNCGRP(mis2, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DEFPINFUNCGRP(gpioc, 1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DEFPINFUNCGRP(mis3, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DEFPINFUNCGRP(mip3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DEFPINFUNCGRP(mis4, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DEFPINFUNCGRP(gpioe, 2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DEFPINFUNCGRP(mis5, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DEFPINFUNCGRP(mip5, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DEFPINFUNCGRP(mis6, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DEFPINFUNCGRP(gpiog, 3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DEFPINFUNCGRP(mis7, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DEFPINFUNCGRP(mip7, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DEFPINFUNCGRP(gpioj, 4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DEFPINFUNCGRP(gpiok, 4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DEFPINFUNCGRP(ciplus, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DEFPINFUNCGRP(mcard, 4, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DEFPINFUNCGRP(stc0, 4, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DEFPINFUNCGRP(stc1, 4, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DEFPINFUNCGRP(mop, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DEFPINFUNCGRP(mos0, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DEFPINFUNCGRP(mos1, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DEFPINFUNCGRP(mos2, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DEFPINFUNCGRP(mos3, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DEFPINFUNCGRP(uart0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DEFPINFUNCGRP(uart1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DEFPINFUNCGRP(gpiol, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DEFPINFUNCGRP(gpiom, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DEFPINFUNCGRP(spi3, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DEFPINFUNCGRP(jtag, 7, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DEFPINFUNCGRP(spi1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEFPINFUNCGRP(gpion, 8, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DEFPINFUNCGRP(gpiob, -1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DEFPINFUNCGRP(gpiod, -1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEFPINFUNCGRP(gpiof, -1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DEFPINFUNCGRP(gpioh, -1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DEFPINFUNCGRP(gpioi, -1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #undef DEFPINFUNCGRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct tb10x_of_pinfunc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) const char *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define TB10X_PORTS (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * struct tb10x_port - state of an I/O port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * @mode: Node this port is currently in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * @count: Number of enabled functions which require this port to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * configured in @mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct tb10x_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * struct tb10x_pinctrl - TB10x pin controller internal state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @pctl: pointer to the pinctrl_dev structure of this pin controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @base: register set base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @pingroups: pointer to an array of the pin groups this driver manages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @pinfuncgrpcnt: number of pingroups in @pingroups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @pinfuncnt: number of pin functions in @pinfuncs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @mutex: mutex for exclusive access to a pin controller's state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @ports: current state of each port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @pinfuncs: flexible array of pin functions this driver manages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct tb10x_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const struct tb10x_pinfuncgrp *pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int pinfuncgrpcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int pinfuncnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct tb10x_port ports[TB10X_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DECLARE_BITMAP(gpios, MAX_PIN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tb10x_of_pinfunc pinfuncs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int port, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (state->ports[port].count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) state->ports[port].mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) iowrite32(pcfg, state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline unsigned int tb10x_pinctrl_get_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct tb10x_pinctrl *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return (ioread32(state->base) & PCFG_PORT_MASK(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) >> (PCFG_PORT_BITWIDTH * port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int tb10x_get_groups_count(struct pinctrl_dev *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return state->pinfuncgrpcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return state->pingroups[n].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned const **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned * const num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *pins = state->pingroups[n].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *num_pins = state->pingroups[n].pincnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const char *string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (of_property_read_string(np_config, "abilis,function", &string)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pr_err("%pOF: No abilis,function property in device tree.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) np_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) num_maps, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) num_maps, string, np_config->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct pinctrl_ops tb10x_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .get_groups_count = tb10x_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .get_group_name = tb10x_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .get_group_pins = tb10x_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .dt_node_to_map = tb10x_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int tb10x_get_functions_count(struct pinctrl_dev *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return state->pinfuncnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const char *tb10x_get_function_name(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return state->pinfuncs[n].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int tb10x_get_function_groups(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned n, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *groups = &state->pinfuncs[n].group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *num_groups = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int muxport = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int muxmode = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Figure out to which port the requested GPIO belongs and how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * configure that port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * This loop also checks for pin conflicts between GPIOs and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (i = 0; i < state->pinfuncgrpcnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned int mode = pfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int j, port = pfg->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Skip pin groups which are always mapped and don't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * to be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (port < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (j = 0; j < pfg->pincnt; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (pin == pfg->pins[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (pfg->isgpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Remember the GPIO-only setting of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * the port this pin belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) muxport = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) muxmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } else if (state->ports[port].count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) && (state->ports[port].mode == mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Error: The requested pin is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * used for something else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * If we haven't returned an error at this point, the GPIO pin is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * used by another function and the GPIO request can be granted:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Register pin as being used as GPIO so we don't allocate it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * another function later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) set_bit(pin, state->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Potential conflicts between GPIOs and pin functions were caught
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * earlier in this function and tb10x_pinctrl_set_config will do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Right Thing, either configure the port in GPIO only mode or leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * another mode compatible with this GPIO request untouched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (muxport >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) tb10x_pinctrl_set_config(state, muxport, muxmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) clear_bit(pin, state->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned func_selector, unsigned group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (grp->port < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Check if the requested function is compatible with previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * requested functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (state->ports[grp->port].count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) && (state->ports[grp->port].mode != grp->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * Check if the requested function is compatible with previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * requested GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) for (i = 0; i < grp->pincnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (test_bit(grp->pins[i], state->gpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tb10x_pinctrl_set_config(state, grp->port, grp->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) state->ports[grp->port].count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const struct pinmux_ops tb10x_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .get_functions_count = tb10x_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .get_function_name = tb10x_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .get_function_groups = tb10x_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .gpio_request_enable = tb10x_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .gpio_disable_free = tb10x_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .set_mux = tb10x_pctl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static struct pinctrl_desc tb10x_pindesc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "TB10x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .pins = tb10x_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .npins = ARRAY_SIZE(tb10x_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .pctlops = &tb10x_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pmxops = &tb10x_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int tb10x_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct device_node *of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct tb10x_pinctrl *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(dev, "No device tree node found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) state = devm_kzalloc(dev, struct_size(state, pinfuncs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) of_get_child_count(of_node)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) platform_set_drvdata(pdev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mutex_init(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) state->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (IS_ERR(state->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = PTR_ERR(state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) state->pingroups = tb10x_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < TB10X_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) state->ports[i].mode = tb10x_pinctrl_get_config(state, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) for_each_child_of_node(of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!of_property_read_string(child, "abilis,function",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) state->pinfuncs[state->pinfuncnt].name = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) state->pinfuncs[state->pinfuncnt].group = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) state->pinfuncnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) state->pctl = devm_pinctrl_register(dev, &tb10x_pindesc, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (IS_ERR(state->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(dev, "could not register TB10x pin driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = PTR_ERR(state->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mutex_destroy(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int tb10x_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_destroy(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct of_device_id tb10x_pinctrl_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .compatible = "abilis,tb10x-iomux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct platform_driver tb10x_pinctrl_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .probe = tb10x_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .remove = tb10x_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .name = "tb10x_pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) module_platform_driver(tb10x_pinctrl_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags