^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Driver for Semtech SX150X I2C GPIO Expanders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Gregory Bean <gbean@codeaurora.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The chip models of sx150x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SX150X_123 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SX150X_456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SX150X_789,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SX150X_MAX_REGISTER = 0xad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SX150X_789_RESET_KEY1 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SX150X_789_RESET_KEY2 = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct sx150x_123_pri {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 reg_pld_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 reg_pld_table0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 reg_pld_table1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 reg_pld_table2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 reg_pld_table3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 reg_pld_table4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 reg_advanced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sx150x_456_pri {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 reg_pld_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 reg_pld_table0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 reg_pld_table1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 reg_pld_table2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 reg_pld_table3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 reg_pld_table4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 reg_advanced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sx150x_789_pri {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 reg_drain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 reg_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 reg_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 reg_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 reg_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sx150x_device_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 reg_pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 reg_pulldn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 reg_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 reg_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 reg_irq_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 reg_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct sx150x_123_pri x123;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sx150x_456_pri x456;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sx150x_789_pri x789;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sx150x_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pinctrl_desc pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct sx150x_device_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct pinctrl_pin_desc sx150x_4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(4, "oscio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct pinctrl_pin_desc sx150x_8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(8, "oscio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct pinctrl_pin_desc sx150x_16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(16, "oscio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct sx150x_device_data sx1501q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .model = SX150X_123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg_pullup = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .reg_pulldn = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .reg_dir = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_irq_mask = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_irq_src = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .reg_sense = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pri.x123 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .reg_pld_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg_pld_table0 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .reg_pld_table2 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .reg_advanced = 0xad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .ngpios = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pins = sx150x_4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .npins = 4, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct sx150x_device_data sx1502q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .model = SX150X_123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg_pullup = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .reg_pulldn = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .reg_dir = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .reg_irq_mask = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reg_irq_src = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .reg_sense = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .pri.x123 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .reg_pld_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .reg_pld_table0 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .reg_pld_table1 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .reg_pld_table2 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_pld_table3 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .reg_pld_table4 = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg_advanced = 0xad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .ngpios = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pins = sx150x_8_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .npins = 8, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct sx150x_device_data sx1503q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .model = SX150X_123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .reg_pullup = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .reg_pulldn = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .reg_dir = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .reg_irq_mask = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .reg_irq_src = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .reg_sense = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .pri.x123 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .reg_pld_mode = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .reg_pld_table0 = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .reg_pld_table1 = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .reg_pld_table2 = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .reg_pld_table3 = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .reg_pld_table4 = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .reg_advanced = 0xad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ngpios = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pins = sx150x_16_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .npins = 16, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct sx150x_device_data sx1504q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .model = SX150X_456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .reg_pullup = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .reg_pulldn = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .reg_dir = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .reg_irq_mask = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .reg_irq_src = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .reg_sense = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .pri.x456 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .reg_pld_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg_pld_table0 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .reg_pld_table2 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ngpios = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pins = sx150x_4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .npins = 4, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct sx150x_device_data sx1505q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .model = SX150X_456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .reg_pullup = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .reg_pulldn = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .reg_dir = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg_irq_mask = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .reg_irq_src = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .reg_sense = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .pri.x456 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .reg_pld_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .reg_pld_table0 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .reg_pld_table1 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .reg_pld_table2 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .reg_pld_table3 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .reg_pld_table4 = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ngpios = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pins = sx150x_8_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .npins = 8, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct sx150x_device_data sx1506q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .model = SX150X_456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .reg_pullup = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .reg_pulldn = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .reg_dir = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .reg_data = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .reg_irq_mask = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .reg_irq_src = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg_sense = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pri.x456 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .reg_pld_mode = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .reg_pld_table0 = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .reg_pld_table1 = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .reg_pld_table2 = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .reg_pld_table3 = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .reg_pld_table4 = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .reg_advanced = 0xad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .ngpios = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .pins = sx150x_16_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .npins = 16, /* oscio not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct sx150x_device_data sx1507q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .model = SX150X_789,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .reg_pullup = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .reg_pulldn = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .reg_dir = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .reg_data = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .reg_irq_mask = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .reg_irq_src = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .reg_sense = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .pri.x789 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .reg_drain = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .reg_polarity = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .reg_clock = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .reg_misc = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .reg_reset = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .ngpios = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pins = sx150x_4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .npins = ARRAY_SIZE(sx150x_4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct sx150x_device_data sx1508q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .model = SX150X_789,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .reg_pullup = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .reg_pulldn = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .reg_dir = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .reg_data = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .reg_irq_mask = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .reg_irq_src = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .reg_sense = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .pri.x789 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .reg_drain = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .reg_polarity = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .reg_clock = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .reg_misc = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .reg_reset = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .ngpios = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .pins = sx150x_8_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .npins = ARRAY_SIZE(sx150x_8_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct sx150x_device_data sx1509q_device_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .model = SX150X_789,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .reg_pullup = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .reg_pulldn = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .reg_dir = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .reg_data = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .reg_irq_mask = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .reg_irq_src = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .reg_sense = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .pri.x789 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .reg_drain = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .reg_polarity = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .reg_clock = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .reg_misc = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .reg_reset = 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ngpios = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .pins = sx150x_16_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .npins = ARRAY_SIZE(sx150x_16_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct pinctrl_ops sx150x_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .get_groups_count = sx150x_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .get_group_name = sx150x_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .get_group_pins = sx150x_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (pin >= pctl->data->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* OSCIO pin is only present in 789 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (pctl->data->model != SX150X_789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return !strcmp(pctl->data->pins[pin].name, "oscio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int sx150x_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (sx150x_pin_is_oscio(pctl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (value & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (sx150x_pin_is_oscio(pctl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return !!(value & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) BIT(offset), value ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return regmap_write(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pctl->data->pri.x789.reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (value ? 0x1f : 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (sx150x_pin_is_oscio(pctl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sx150x_gpio_oscio_set(pctl, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __sx150x_gpio_set(pctl, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int sx150x_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (sx150x_pin_is_oscio(pctl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pctl->data->reg_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BIT(offset), BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int sx150x_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (sx150x_pin_is_oscio(pctl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return sx150x_gpio_oscio_set(pctl, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = __sx150x_gpio_set(pctl, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pctl->data->reg_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) BIT(offset), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void sx150x_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct sx150x_pinctrl *pctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int n = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pctl->irq.masked |= BIT(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void sx150x_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct sx150x_pinctrl *pctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int n = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pctl->irq.masked &= ~BIT(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int line, unsigned int sense)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Every interrupt line is represented by two bits shifted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * proportionally to the line number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) const unsigned int n = line * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SX150X_IRQ_TYPE_EDGE_FALLING) << n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pctl->irq.sense &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pctl->irq.sense |= sense << n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct sx150x_pinctrl *pctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned int n, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) n = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (flow_type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= SX150X_IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (flow_type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val |= SX150X_IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sx150x_irq_set_sense(pctl, n, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned long n, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) status = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) for_each_set_bit(n, &status, pctl->data->ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void sx150x_irq_bus_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct sx150x_pinctrl *pctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mutex_lock(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct sx150x_pinctrl *pctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mutex_unlock(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (sx150x_pin_is_oscio(pctl, pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pctl->data->pri.x789.reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) arg = (data & 0x1f) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if ((data & 0x1f) == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else if ((data & 0x1f) == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pctl->data->reg_pulldn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) data &= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pctl->data->reg_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) data &= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (pctl->data->model != SX150X_789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pctl->data->pri.x789.reg_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) data &= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (pctl->data->model != SX150X_789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) arg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pctl->data->pri.x789.reg_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data &= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret == GPIO_LINE_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = sx150x_gpio_get(&pctl->gpio, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) arg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (sx150x_pin_is_oscio(pctl, pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (param == PIN_CONFIG_OUTPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = sx150x_gpio_direction_output(&pctl->gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pctl->data->reg_pulldn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) BIT(pin), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pctl->data->reg_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) BIT(pin), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pctl->data->reg_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) BIT(pin), BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pctl->data->reg_pulldn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) BIT(pin), BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (pctl->data->model != SX150X_789 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) sx150x_pin_is_oscio(pctl, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pctl->data->pri.x789.reg_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) BIT(pin), BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (pctl->data->model != SX150X_789 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) sx150x_pin_is_oscio(pctl, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pctl->data->pri.x789.reg_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) BIT(pin), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = sx150x_gpio_direction_output(&pctl->gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const struct pinconf_ops sx150x_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .pin_config_get = sx150x_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .pin_config_set = sx150x_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct i2c_device_id sx150x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct of_device_id sx150x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int sx150x_reset(struct sx150x_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) err = i2c_smbus_write_byte_data(pctl->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pctl->data->pri.x789.reg_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SX150X_789_RESET_KEY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) err = i2c_smbus_write_byte_data(pctl->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pctl->data->pri.x789.reg_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SX150X_789_RESET_KEY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u8 reg, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) switch (pctl->data->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case SX150X_789:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) reg = pctl->data->pri.x789.reg_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case SX150X_456:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reg = pctl->data->pri.x456.reg_advanced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Only SX1506 has RegAdvanced, SX1504/5 are expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * to initialize this offset to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case SX150X_123:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) reg = pctl->data->pri.x123.reg_advanced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) WARN(1, "Unknown chip model %d\n", pctl->data->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return regmap_write(pctl->regmap, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) const u8 reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [SX150X_789] = pctl->data->pri.x789.reg_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (pctl->data->model == SX150X_789 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) err = sx150x_reset(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) err = sx150x_init_misc(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Set all pins to work in normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) const struct sx150x_device_data *data = pctl->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (reg == data->reg_sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * RegSense packs two bits of configuration per GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * so we'd need to read twice as many bits as there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * are GPIO in our chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 2 * data->ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else if ((data->model == SX150X_789 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) (reg == data->pri.x789.reg_misc ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) reg == data->pri.x789.reg_clock ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) reg == data->pri.x789.reg_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (data->model == SX150X_123 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) reg == data->pri.x123.reg_advanced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) (data->model == SX150X_456 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) data->pri.x456.reg_advanced &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) reg == data->pri.x456.reg_advanced)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return data->ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned int a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) const struct sx150x_device_data *data = pctl->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Whereas SX1509 presents RegSense in a simple layout as such:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * reg [ f f e e d d c c ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * reg + 1 [ b b a a 9 9 8 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * reg + 2 [ 7 7 6 6 5 5 4 4 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * reg + 3 [ 3 3 2 2 1 1 0 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * SX1503 and SX1506 deviate from that data layout, instead storing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * their contents as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * reg [ f f e e d d c c ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * reg + 1 [ 7 7 6 6 5 5 4 4 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * reg + 2 [ b b a a 9 9 8 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * reg + 3 [ 3 3 2 2 1 1 0 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * so, taking that into account, we swap two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * inner bytes of a 4-byte result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (reg == data->reg_sense &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) data->ngpios == 16 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) (data->model == SX150X_123 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) data->model == SX150X_456)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) a = val & 0x00ff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) b = val & 0x0000ff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) val &= 0xff0000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) val |= b << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) val |= a >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * In order to mask the differences between 16 and 8 bit expander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * devices we set up a sligthly ficticious regmap that pretends to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * pair/quartet) registers and transparently reconstructs those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * registers via multiple I2C/SMBus reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * This way the rest of the driver code, interfacing with the chip via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * regmap API, can work assuming that each GPIO pin is represented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * a group of bits at an offset proportional to GPIO number within a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * given register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int sx150x_regmap_reg_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct sx150x_pinctrl *pctl = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct i2c_client *i2c = pctl->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) const int width = sx150x_regmap_reg_width(pctl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned int idx, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * There are four potential cases covered by this function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * 1) 8-pin chip, single configuration bit register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * This is trivial the code below just needs to read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * reg [ 7 6 5 4 3 2 1 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * 2) 8-pin chip, double configuration bit register (RegSense)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * The read will be done as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * reg [ 7 7 6 6 5 5 4 4 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * reg + 1 [ 3 3 2 2 1 1 0 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * 3) 16-pin chip, single configuration bit register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * The read will be done as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * reg [ f e d c b a 9 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * reg + 1 [ 7 6 5 4 3 2 1 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * 4) 16-pin chip, double configuration bit register (RegSense)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * The read will be done as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * reg [ f f e e d d c c ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * reg + 1 [ b b a a 9 9 8 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * reg + 2 [ 7 7 6 6 5 5 4 4 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * reg + 3 [ 3 3 2 2 1 1 0 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) val <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = i2c_smbus_read_byte_data(i2c, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) val |= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) *result = sx150x_maybe_swizzle(pctl, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int sx150x_regmap_reg_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct sx150x_pinctrl *pctl = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct i2c_client *i2c = pctl->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) const int width = sx150x_regmap_reg_width(pctl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) val = sx150x_maybe_swizzle(pctl, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) n = (width - 1) & ~7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) const u8 byte = (val >> n) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = i2c_smbus_write_byte_data(i2c, reg, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) n -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) } while (n >= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const struct regmap_config sx150x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .reg_read = sx150x_regmap_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .reg_write = sx150x_regmap_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .max_register = SX150X_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .volatile_reg = sx150x_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static int sx150x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) I2C_FUNC_SMBUS_WRITE_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct sx150x_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!i2c_check_functionality(client->adapter, i2c_funcs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) i2c_set_clientdata(client, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pctl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pctl->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pctl->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) pctl->data = (struct sx150x_device_data *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!pctl->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pctl->regmap = devm_regmap_init(dev, NULL, pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &sx150x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (IS_ERR(pctl->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = PTR_ERR(pctl->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_err(dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mutex_init(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = sx150x_init_hw(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Pinctrl_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) pctl->pinctrl_desc.name = "sx150x-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) pctl->pinctrl_desc.pins = pctl->data->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pctl->pinctrl_desc.npins = pctl->data->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pctl->pinctrl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pctl, &pctl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(dev, "Failed to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Register GPIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pctl->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pctl->gpio.ngpio = pctl->data->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pctl->gpio.get_direction = sx150x_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pctl->gpio.direction_input = sx150x_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pctl->gpio.direction_output = sx150x_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pctl->gpio.get = sx150x_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pctl->gpio.set = sx150x_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pctl->gpio.set_config = gpiochip_generic_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) pctl->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) pctl->gpio.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pctl->gpio.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!pctl->gpio.label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Setting multiple pins is not safe when all pins are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * handled by the same regmap register. The oscio pin (present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * on the SX150X_789 chips) lives in its own register, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * would require locking that is not in place at this time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (pctl->data->model != SX150X_789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Add Interrupt support if an irq is specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pctl->irq_chip.irq_mask = sx150x_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pctl->irq_chip.name = devm_kstrdup(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!pctl->irq_chip.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) pctl->irq.masked = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pctl->irq.sense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Because sx150x_irq_threaded_fn invokes all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * nested interrupt handlers via handle_nested_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * any "handler" assigned to struct gpio_irq_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * below is going to be ignored, so the choice of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * function does not matter that much.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * We set it to handle_bad_irq to avoid confusion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * plus it will be instantly noticeable if it is ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * called (should not happen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) girq = &pctl->gpio.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) girq->chip = &pctl->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sx150x_irq_thread_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) IRQF_ONESHOT | IRQF_SHARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pctl->irq_chip.name, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Pin control functions need to be enabled AFTER registering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * GPIO chip because sx150x_pinconf_set() calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * sx150x_gpio_direction_output().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = pinctrl_enable(pctl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dev_err(dev, "Failed to enable pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) 0, 0, pctl->data->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static struct i2c_driver sx150x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .name = "sx150x-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .of_match_table = of_match_ptr(sx150x_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .probe = sx150x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .id_table = sx150x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int __init sx150x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return i2c_add_driver(&sx150x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) subsys_initcall(sx150x_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags