^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/stmfx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* GPIOs expander */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NR_GPIO_REGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NR_GPIOS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define get_mask(offset) (BIT(get_shift(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Pins availability is managed thanks to gpio-ranges property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct pinctrl_pin_desc stmfx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(16, "agpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(17, "agpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(18, "agpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(19, "agpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(20, "agpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(21, "agpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(22, "agpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(23, "agpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct stmfx_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct stmfx *stmfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mutex lock; /* IRQ bus lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long gpio_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Cache of IRQ_GPI_* registers for bus_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 irq_gpi_src[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 irq_gpi_type[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 irq_gpi_evt[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 irq_toggle_edge[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Backup of GPIO_* registers for suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 bkp_gpio_state[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 bkp_gpio_dir[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 bkp_gpio_type[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 bkp_gpio_pupd[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_read(pctl->stmfx->map, reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret ? ret : !!(value & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = regmap_read(pctl->stmfx->map, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * On stmfx, gpio pins direction is (0)input, (1)output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int stmfx_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) stmfx_gpio_set(gc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 pupd, mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_read(pctl->stmfx->map, reg, &pupd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return !!(pupd & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int offset, u32 pupd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 type, mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = regmap_read(pctl->stmfx->map, reg, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return !!(type & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int offset, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ret, dir, type, pupd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (dir < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Currently the gpiolib IN is 1 and OUT is 0 but let's not count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * on it just to be on the safe side also in the future :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) type = stmfx_pinconf_get_type(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pupd = stmfx_pinconf_get_pupd(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (pupd < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return pupd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if ((!dir && (!type || !pupd)) || (dir && !type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (dir && type && !pupd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (type && pupd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if ((!dir && type) || (dir && !type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if ((!dir && !type) || (dir && type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) arg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(pctldev->dev, "pin %d is not available\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = stmfx_pinconf_set_type(pctl, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = stmfx_pinconf_set_type(pctl, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = stmfx_pinconf_set_type(pctl, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = stmfx_pinconf_set_type(pctl, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct seq_file *s, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int dir, type, pupd, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (dir < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) type = stmfx_pinconf_get_type(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pupd = stmfx_pinconf_get_pupd(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (pupd < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = stmfx_gpio_get(&pctl->gpio_chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (dir == GPIO_LINE_DIRECTION_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) seq_printf(s, "output %s ", val ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) seq_printf(s, "open drain %s internal pull-up ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pupd ? "with" : "without");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) seq_puts(s, "push pull no pull ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) seq_printf(s, "input %s ", val ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) seq_printf(s, "with internal pull-%s ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pupd ? "up" : "down");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) seq_printf(s, "%s ", pupd ? "floating" : "analog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct pinconf_ops stmfx_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .pin_config_get = stmfx_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .pin_config_set = stmfx_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pin_config_dbg_show = stmfx_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct pinctrl_ops stmfx_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .get_groups_count = stmfx_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .get_group_name = stmfx_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .get_group_pins = stmfx_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void stmfx_pinctrl_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 reg = get_reg(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 mask = get_mask(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pctl->irq_gpi_src[reg] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 reg = get_reg(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 mask = get_mask(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pctl->irq_gpi_src[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 reg = get_reg(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 mask = get_mask(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (type == IRQ_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pctl->irq_gpi_evt[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pctl->irq_gpi_evt[reg] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pctl->irq_gpi_type[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pctl->irq_gpi_type[reg] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * GPIO value to set the right edge trigger. But in atomic context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * here we can't access registers over I2C. That's why (type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pctl->irq_toggle_edge[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pctl->irq_toggle_edge[reg] &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mutex_lock(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 reg = get_reg(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 mask = get_mask(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * (this couldn't be done in .irq_set_type because of atomic context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * to set the right irq trigger type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (pctl->irq_toggle_edge[reg] & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (stmfx_gpio_get(gpio_chip, data->hwirq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pctl->irq_gpi_type[reg] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pctl->irq_gpi_type[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pctl->irq_gpi_evt, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pctl->irq_gpi_type, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pctl->irq_gpi_src, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mutex_unlock(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int stmfx_gpio_irq_request_resources(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return gpiochip_reqres_irq(gpio_chip, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void stmfx_gpio_irq_release_resources(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return gpiochip_relres_irq(gpio_chip, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 reg = get_reg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 mask = get_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!(pctl->irq_toggle_edge[reg] & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val = stmfx_gpio_get(&pctl->gpio_chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pctl->irq_gpi_type[reg] &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) regmap_write_bits(pctl->stmfx->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) STMFX_REG_IRQ_GPI_TYPE + reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pctl->irq_gpi_type[reg] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) regmap_write_bits(pctl->stmfx->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) STMFX_REG_IRQ_GPI_TYPE + reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct gpio_chip *gc = &pctl->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 pending[NR_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 src[NR_GPIO_REGS] = {0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned long n, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) &pending, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) src, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) status |= (unsigned long)pending[i] << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for_each_set_bit(n, &status, gc->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) stmfx_pinctrl_irq_toggle_trigger(pctl, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pctl->irq_gpi_src, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct pinctrl_gpio_range *gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 func = STMFX_FUNC_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pctl->gpio_valid_mask = GENMASK(15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (gpio_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) func |= STMFX_FUNC_ALTGPIO_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pctl->gpio_valid_mask |= GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (gpio_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) func |= STMFX_FUNC_ALTGPIO_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pctl->gpio_valid_mask |= GENMASK(23, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return stmfx_function_enable(pctl->stmfx, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int stmfx_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct stmfx_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) platform_set_drvdata(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pctl->stmfx = stmfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!of_find_property(np, "gpio-ranges", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(pctl->dev, "missing required gpio-ranges property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mutex_init(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Register pin controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pctl->pctl_desc.name = "stmfx-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pctl->pctl_desc.confops = &stmfx_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pctl->pctl_desc.pins = stmfx_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pctl->pctl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) pctl->pctl_desc.link_consumers = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pctl, &pctl->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(pctl->dev, "pinctrl registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = pinctrl_enable(pctl->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_err(pctl->dev, "pinctrl enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Register gpio controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pctl->gpio_chip.label = "stmfx-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pctl->gpio_chip.parent = pctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pctl->gpio_chip.get = stmfx_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pctl->gpio_chip.set = stmfx_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pctl->gpio_chip.set_config = gpiochip_generic_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pctl->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pctl->gpio_chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) pctl->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pctl->irq_chip.name = dev_name(pctl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) girq = &pctl->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) girq->chip = &pctl->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(pctl->dev, "gpio_chip registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = stmfx_pinctrl_gpio_function_enable(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) stmfx_pinctrl_irq_thread_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) pctl->irq_chip.name, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(pctl->dev, "cannot request irq%d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_info(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int stmfx_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return stmfx_function_disable(stmfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) STMFX_FUNC_GPIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) STMFX_FUNC_ALTGPIO_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) STMFX_FUNC_ALTGPIO_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) &pctl->bkp_gpio_state, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) &pctl->bkp_gpio_dir, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) &pctl->bkp_gpio_type, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pctl->bkp_gpio_dir, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pctl->bkp_gpio_type, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pctl->bkp_gpio_pupd, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pctl->bkp_gpio_state, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pctl->irq_gpi_evt, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pctl->irq_gpi_type, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pctl->irq_gpi_src, NR_GPIO_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int stmfx_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = stmfx_pinctrl_backup_regs(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_err(pctl->dev, "registers backup failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int stmfx_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = stmfx_pinctrl_restore_regs(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(pctl->dev, "registers restoration failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct of_device_id stmfx_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) { .compatible = "st,stmfx-0300-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct platform_driver stmfx_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .name = "stmfx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .of_match_table = stmfx_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .pm = &stmfx_pinctrl_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .probe = stmfx_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .remove = stmfx_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) module_platform_driver(stmfx_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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