^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Srinivas Kandagatla <srinivas.kandagatla@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_gpio.h> /* of_get_named_gpio() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PIO Block registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PIO output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_PIO_POUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Set bits of POUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_PIO_SET_POUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Clear bits of POUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_PIO_CLR_POUT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PIO input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_PIO_PIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* PIO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Set bits of PC[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Clear bits of PC[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* PIO input comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_PIO_PCOMP 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Set bits of PCOMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_PIO_SET_PCOMP 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Clear bits of PCOMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_PIO_CLR_PCOMP 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PIO input comparison mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_PIO_PMASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Set bits of PMASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_PIO_SET_PMASK 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Clear bits of PMASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_PIO_CLR_PMASK 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ST_GPIO_DIRECTION_BIDIR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ST_GPIO_DIRECTION_OUT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ST_GPIO_DIRECTION_IN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Packed style retime configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * There are two registers cfg0 and cfg1 in this style for each bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Each field in this register is 8 bit corresponding to 8 pins in the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RT_P_CFGS_PER_BANK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Dedicated style retime Configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * each register is dedicated per pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RT_D_CFGS_PER_BANK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RT_D_CFG_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RT_D_CFG_CLK_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RT_D_CFG_CLKNOTDATA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RT_D_CFG_DELAY_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RT_D_CFG_DELAY_MASK (0xf << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RT_D_CFG_INVERTCLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RT_D_CFG_INVERTCLK_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RT_D_CFG_RETIME_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RT_D_CFG_RETIME_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Pinconf is represented in an opaque unsigned long variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Below is the bit allocation details for each possible configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * All the bit fields can be encapsulated into four variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * (direction, retime-type, retime-clk, retime-delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *[31:28]| reserved-3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * +----------------+-------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *[27] | oe | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * +----------------+ v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *[26] | pu | [Direction ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * +----------------+ ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *[25] | od | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * +----------------+-------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *[24] | reserved-2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * +----------------+-------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *[23] | retime | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * +----------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *[22] | retime-invclk | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * +----------------+ v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *[21] |retime-clknotdat| [Retime-type ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * +----------------+ ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *[20] | retime-de | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * +----------------+-------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *[19:18]| retime-clk |------>[Retime-Clk ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *[17:16]| reserved-1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *[15..0]| retime-delay |------>[Retime Delay]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ST_PINCONF_UNPACK(conf, param)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) & ST_PINCONF_ ##param ##_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ST_PINCONF_PACK(conf, val, param) (conf |=\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ((val & ST_PINCONF_ ##param ##_MASK) << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ST_PINCONF_ ##param ##_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ST_PINCONF_OE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ST_PINCONF_OE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ST_PINCONF_OE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Pull Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ST_PINCONF_PU_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ST_PINCONF_PU_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ST_PINCONF_PU BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Open Drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ST_PINCONF_OD_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ST_PINCONF_OD_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ST_PINCONF_OD BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ST_PINCONF_RT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ST_PINCONF_RT_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ST_PINCONF_RT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ST_PINCONF_RT_INVERTCLK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ST_PINCONF_RT_CLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ST_PINCONF_RT_CLK_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ST_PINCONF_RT_CLK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* RETIME_DELAY in Pico Secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ST_PINCONF_RT_DELAY_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ST_PINCONF_RT_DELAY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ST_PINCONF_PACK(conf, val, RT_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ST_GPIO_PINS_PER_BANK (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OF_GPIO_ARGS_MIN (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OF_RT_ARGS_MIN (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define gpio_range_to_bank(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) container_of(chip, struct st_gpio_bank, range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define pc_to_bank(pc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) container_of(pc, struct st_gpio_bank, pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enum st_retime_style {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) st_retime_style_none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) st_retime_style_packed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) st_retime_style_dedicated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct st_retime_dedicated {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct st_retime_packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct regmap_field *clk1notclk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct regmap_field *delay_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct regmap_field *delay_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct regmap_field *invertclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct regmap_field *retime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct regmap_field *clknotdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct regmap_field *double_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct st_pio_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 rt_pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct regmap_field *alt, *oe, *pu, *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* retiming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct st_retime_packed rt_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct st_retime_dedicated rt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct st_pctl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const enum st_retime_style rt_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const unsigned int *input_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) const int ninput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const unsigned int *output_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) const int noutput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* register offset information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const int alt, oe, pu, od, rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct st_pinconf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int altfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct st_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct st_pctl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct st_pinconf *pin_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Edge triggers are not supported at hardware level, it is supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * software by exploiting the level trigger support in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * of each gpio pin in a GPIO bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * bit allocation per pin is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * A pin can have one of following the values in its edge configuration field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * ------- ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * [0-3] - Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * ------- ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 0000 - No edge IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 0001 - Falling edge IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 0010 - Rising edge IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * 0011 - Rising and Falling edge IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * ------- ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ST_IRQ_EDGE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ST_IRQ_EDGE_FALLING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ST_IRQ_EDGE_RISING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ST_IRQ_RISING_EDGE_CONF(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ST_IRQ_FALLING_EDGE_CONF(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ST_IRQ_BOTH_EDGE_CONF(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ST_IRQ_EDGE_CONF(conf, pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct st_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct pinctrl_gpio_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct st_pio_control pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long irq_edge_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct st_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct st_gpio_bank *banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct st_pmx_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct st_pctl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const struct st_pctl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void __iomem *irqmux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* SOC specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct st_pctl_data stih407_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .rt_style = st_retime_style_dedicated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .input_delays = stih407_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .ninput_delays = ARRAY_SIZE(stih407_delays),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .output_delays = stih407_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .noutput_delays = ARRAY_SIZE(stih407_delays),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct st_pctl_data stih407_flashdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .rt_style = st_retime_style_none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .input_delays = stih407_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .ninput_delays = ARRAY_SIZE(stih407_delays),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .output_delays = stih407_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .noutput_delays = ARRAY_SIZE(stih407_delays),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .alt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .oe = -1, /* Not Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .pu = -1, /* Not Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .od = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .rt = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct st_pio_control *st_get_pio_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct pinctrl_dev *pctldev, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct pinctrl_gpio_range *range =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pinctrl_find_gpio_range_from_pin(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct st_gpio_bank *bank = gpio_range_to_bank(range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return &bank->pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Low level functions.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline int st_gpio_bank(int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return gpio/ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline int st_gpio_pin(int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return gpio%ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void st_pinconf_set_config(struct st_pio_control *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int pin, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct regmap_field *output_enable = pc->oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct regmap_field *pull_up = pc->pu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct regmap_field *open_drain = pc->od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int oe_value, pu_value, od_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long mask = BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (output_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) regmap_field_read(output_enable, &oe_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) oe_value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (config & ST_PINCONF_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) oe_value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regmap_field_write(output_enable, oe_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pull_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_field_read(pull_up, &pu_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pu_value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (config & ST_PINCONF_PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pu_value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regmap_field_write(pull_up, pu_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (open_drain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regmap_field_read(open_drain, &od_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) od_value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (config & ST_PINCONF_OD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) od_value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regmap_field_write(open_drain, od_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void st_pctl_set_function(struct st_pio_control *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int pin_id, int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct regmap_field *alt = pc->alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int pin = st_gpio_pin(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int offset = pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regmap_field_read(alt, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val &= ~(0xf << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val |= function << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regmap_field_write(alt, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct regmap_field *alt = pc->alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int offset = pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regmap_field_read(alt, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return (val >> offset) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const struct st_pctl_data *data, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const unsigned int *delay_times;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int num_delay_times, i, closest_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int closest_divergence = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ST_PINCONF_UNPACK_OE(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) delay_times = data->output_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) num_delay_times = data->noutput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) delay_times = data->input_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) num_delay_times = data->ninput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (i = 0; i < num_delay_times; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int divergence = abs(delay - delay_times[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (divergence == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (divergence < closest_divergence) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) closest_divergence = divergence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) closest_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pr_warn("Attempt to set delay %d, closest available %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) delay, delay_times[closest_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return closest_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static unsigned long st_pinconf_bit_to_delay(unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const struct st_pctl_data *data, unsigned long output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const unsigned int *delay_times;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int num_delay_times;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) delay_times = data->output_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) num_delay_times = data->noutput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) delay_times = data->input_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) num_delay_times = data->ninput_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (index < num_delay_times) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return delay_times[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pr_warn("Delay not found in/out delay list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int enable, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_field_read(field, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regmap_field_write(field, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct st_pio_control *pc, unsigned long config, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct st_retime_packed *rt_p = &pc->rt.rt_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ST_PINCONF_UNPACK_RT_CLK(config), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) st_regmap_field_bit_set_clear_pin(rt_p->retime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ST_PINCONF_UNPACK_RT(config), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) data, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* 2 bit delay, lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* 2 bit delay, msb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct st_pio_control *pc, unsigned long config, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int clk = ST_PINCONF_UNPACK_RT_CLK(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int retime = ST_PINCONF_UNPACK_RT(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long delay = st_pinconf_delay_to_bit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ST_PINCONF_UNPACK_RT_DELAY(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) info->data, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned long retime_config =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ((clk) << RT_D_CFG_CLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ((delay) << RT_D_CFG_DELAY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ((retime) << RT_D_CFG_RETIME_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) regmap_field_write(rt_d->rt[pin], retime_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void st_pinconf_get_direction(struct st_pio_control *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int oe_value, pu_value, od_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (pc->oe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) regmap_field_read(pc->oe, &oe_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (oe_value & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ST_PINCONF_PACK_OE(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (pc->pu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regmap_field_read(pc->pu, &pu_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (pu_value & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ST_PINCONF_PACK_PU(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (pc->od) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regmap_field_read(pc->od, &od_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (od_value & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ST_PINCONF_PACK_OD(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct st_pio_control *pc, int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct st_retime_packed *rt_p = &pc->rt.rt_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int delay_bits, delay, delay0, delay1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int output = ST_PINCONF_UNPACK_OE(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ST_PINCONF_PACK_RT(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ST_PINCONF_PACK_RT_CLK(*config, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ST_PINCONF_PACK_RT_INVERTCLK(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regmap_field_read(rt_p->delay_0, &delay0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) regmap_field_read(rt_p->delay_1, &delay1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) (((delay0 & BIT(pin)) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) delay = st_pinconf_bit_to_delay(delay_bits, data, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ST_PINCONF_PACK_RT_DELAY(*config, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct st_pio_control *pc, int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long delay_bits, delay, rt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int output = ST_PINCONF_UNPACK_OE(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) regmap_field_read(rt_d->rt[pin], &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ST_PINCONF_PACK_RT_DELAY(*config, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (value & RT_D_CFG_CLKNOTDATA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (value & RT_D_CFG_INVERTCLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ST_PINCONF_PACK_RT_INVERTCLK(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (value & RT_D_CFG_RETIME_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ST_PINCONF_PACK_RT(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* GPIO related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static inline void __st_gpio_set(struct st_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void st_gpio_direction(struct st_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int gpio, unsigned int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int offset = st_gpio_pin(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * There are three configuration registers (PIOn_PC0, PIOn_PC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * and PIOn_PC2) for each port. These are used to configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * PIO port pins. Each pin can be configured as an input, output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * bidirectional, or alternative function pin. Three bits, one bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * from each of the three registers, configure the corresponding bit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * the port. Valid bit settings is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * PC2 PC1 PC0 Direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * 0 0 0 [Input Weak pull-up]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * 0 0 or 1 1 [Bidirection]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * 0 1 0 [Output]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * 1 0 0 [Input]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * individually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) for (i = 0; i <= 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (direction & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct st_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct st_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __st_gpio_set(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int st_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct st_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __st_gpio_set(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct st_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct st_pio_control pc = bank->pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned int direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) unsigned int function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Alternate function direction is handled by Pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) function = st_pctl_get_pin_function(&pc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) st_pinconf_get_direction(&pc, offset, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ST_PINCONF_UNPACK_OE(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * GPIO direction is handled differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * - See st_gpio_direction() above for an explanation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (i = 0; i <= 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) value = readl(bank->base + REG_PIO_PC(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) direction |= ((value >> offset) & 0x1) << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (direction == ST_GPIO_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Pinctrl Groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return info->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned selector, const unsigned **pins, unsigned *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *pins = info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *npins = info->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static inline const struct st_pctl_group *st_pctl_find_group_by_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) const struct st_pinctrl *info, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) for (i = 0; i < info->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!strcmp(info->groups[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return &info->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) const struct st_pctl_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct pinctrl_map *new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int map_num, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) grp = st_pctl_find_group_by_name(info, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(info->dev, "unable to find group for node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) map_num = grp->npins + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) new_map = devm_kcalloc(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) map_num, sizeof(*new_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!new_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) parent = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) devm_kfree(pctldev->dev, new_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *map = new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *num_maps = map_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) new_map[0].data.mux.function = parent->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) new_map[0].data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* create config map per pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) new_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) new_map[i].data.configs.group_or_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pin_get_name(pctldev, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) new_map[i].data.configs.configs = &grp->pin_conf[i].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) new_map[i].data.configs.num_configs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) (*map)->data.mux.function, grp->name, map_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct pinctrl_ops st_pctlops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .get_groups_count = st_pctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .get_group_pins = st_pctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .get_group_name = st_pctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .dt_node_to_map = st_pctl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .dt_free_map = st_pctl_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return info->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return info->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned selector, const char * const **grps, unsigned * const ngrps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) *grps = info->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *ngrps = info->functions[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct st_pinconf *conf = info->groups[group].pin_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct st_pio_control *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) for (i = 0; i < info->groups[group].npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pc = st_get_pio_control(pctldev, conf[i].pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct pinctrl_gpio_range *range, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct st_gpio_bank *bank = gpio_range_to_bank(range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * When a PIO bank is used in its primary function mode (altfunc = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * for the primary PIO functions are driven by the related PIO block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) st_pctl_set_function(&bank->pc, gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) st_gpio_direction(bank, gpio, input ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct pinmux_ops st_pmxops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .get_functions_count = st_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .get_function_name = st_pmx_get_fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .get_function_groups = st_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .set_mux = st_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .gpio_set_direction = st_pmx_set_gpio_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Pinconf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static void st_pinconf_get_retime(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct st_pio_control *pc, int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (info->data->rt_style == st_retime_style_packed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) st_pinconf_get_retime_packed(info, pc, pin, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) else if (info->data->rt_style == st_retime_style_dedicated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if ((BIT(pin) & pc->rt_pin_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) st_pinconf_get_retime_dedicated(info, pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pin, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void st_pinconf_set_retime(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct st_pio_control *pc, int pin, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (info->data->rt_style == st_retime_style_packed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) st_pinconf_set_retime_packed(info, pc, config, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) else if (info->data->rt_style == st_retime_style_dedicated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if ((BIT(pin) & pc->rt_pin_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) st_pinconf_set_retime_dedicated(info, pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) config, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int pin = st_gpio_pin(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) st_pinconf_set_config(pc, pin, configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) st_pinconf_set_retime(info, pc, pin, configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int st_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned pin_id, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int pin = st_gpio_pin(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) st_pinconf_get_direction(pc, pin, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) st_pinconf_get_retime(info, pc, pin, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct seq_file *s, unsigned pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct st_pio_control *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned int function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int offset = st_gpio_pin(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) char f[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_unlock(&pctldev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pc = st_get_pio_control(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) st_pinconf_get(pctldev, pin_id, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mutex_lock(&pctldev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) function = st_pctl_get_pin_function(pc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) snprintf(f, 10, "Alt Fn %u", function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) snprintf(f, 5, "GPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "de:%ld,rt-clk:%ld,rt-delay:%ld]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (oe == GPIO_LINE_DIRECTION_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ST_PINCONF_UNPACK_PU(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ST_PINCONF_UNPACK_OD(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ST_PINCONF_UNPACK_RT(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ST_PINCONF_UNPACK_RT_INVERTCLK(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ST_PINCONF_UNPACK_RT_CLK(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ST_PINCONF_UNPACK_RT_DELAY(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const struct pinconf_ops st_confops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .pin_config_get = st_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .pin_config_set = st_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .pin_config_dbg_show = st_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void st_pctl_dt_child_count(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (of_property_read_bool(child, "gpio-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) info->nbanks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) info->nfunctions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) info->ngroups += of_get_child_count(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int bank, struct st_pio_control *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct regmap *rm = info->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* 2 registers per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct st_retime_packed *rt_p = &pc->rt.rt_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* cfg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* cfg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) IS_ERR(rt_p->double_edge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int bank, struct st_pio_control *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct regmap *rm = info->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* 8 registers per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) u32 pin_mask = pc->rt_pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (BIT(j) & pin_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (IS_ERR(rt_d->rt[j]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) reg_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int bank, struct st_pio_control *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (data->rt_style == st_retime_style_packed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return st_pctl_dt_setup_retime_packed(info, bank, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) else if (data->rt_style == st_retime_style_dedicated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static struct regmap_field *st_pc_get_value(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct regmap *regmap, int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int data, int lsb, int msb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return devm_regmap_field_alloc(dev, regmap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) const struct st_pctl_data *data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * For a given shared register like OE/PU/OD, there are 8 bits per bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * So each register is shared across 4 banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct st_pio_control *pc = &info->banks[bank].pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct regmap *regmap = info->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* retime avaiable for all pins by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pc->rt_pin_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) st_pctl_dt_setup_retime(info, bank, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * Each pin is represented in of the below forms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * <bank offset mux direction rt_type rt_delay rt_clk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int st_pctl_dt_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* bank pad direction val altfunction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct property *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct st_pinconf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct device_node *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int i = 0, npins = 0, nr_props, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pins = of_get_child_by_name(np, "st,pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) for_each_property_of_node(pins, pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Skip those we do not want to proceed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!strcmp(pp->name, "name"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) npins++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pr_warn("Invalid st,pins in %pOFn node\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) grp->npins = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) grp->pin_conf = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) npins, sizeof(*conf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!grp->pins || !grp->pin_conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* <bank offset mux direction rt_type rt_delay rt_clk> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) for_each_property_of_node(pins, pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!strcmp(pp->name, "name"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) nr_props = pp->length/sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) list = pp->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) conf = &grp->pin_conf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* bank & offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) conf->pin = of_get_named_gpio(pins, pp->name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) conf->name = pp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) grp->pins[i] = conf->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) conf->altfunc = be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) conf->config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) conf->config |= be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* rt_type rt_delay rt_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* rt_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) conf->config |= be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* rt_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) conf->config |= be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* rt_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) conf->config |= be32_to_cpup(list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) out_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) of_node_put(pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int st_pctl_parse_functions(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct st_pinctrl *info, u32 index, int *grp_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct st_pmx_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct st_pctl_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) func = &info->functions[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) func->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) func->ngroups = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (func->ngroups == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_err(info->dev, "No groups defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) func->groups = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) func->ngroups, sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) func->groups[i] = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) grp = &info->groups[*grp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *grp_index += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = st_pctl_dt_parse_groups(child, grp, info, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) index, func->name, func->ngroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static void st_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct st_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static void st_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct st_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int st_gpio_irq_request_resources(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) st_gpio_direction_input(gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return gpiochip_lock_as_irq(gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void st_gpio_irq_release_resources(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) gpiochip_unlock_as_irq(gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct st_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int comp, pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u32 pin_edge_conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) comp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) comp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) comp = st_gpio_get(&bank->gpio_chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) bank->irq_edge_conf |= pin_edge_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) val = readl(bank->base + REG_PIO_PCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) val &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) val |= (comp << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) writel(val, bank->base + REG_PIO_PCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * As edge triggers are not supported at hardware level, it is supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * software by exploiting the level trigger support in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * Steps for detection raising edge interrupt in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * Step 1: CONFIGURE pin to detect level LOW interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * IGNORE calling the actual interrupt handler for the pin at this stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * DISPATCH the interrupt to the interrupt handler of the pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * step-1 ________ __________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * | | step - 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * step -2 |_____|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * falling edge is also detected int the same way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static void __gpio_irq_handler(struct st_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) unsigned long port_in, port_mask, port_comp, active_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) unsigned long bank_edge_mask, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int n, val, ecfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) bank_edge_mask = bank->irq_edge_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) port_in = readl(bank->base + REG_PIO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) port_comp = readl(bank->base + REG_PIO_PCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) port_mask = readl(bank->base + REG_PIO_PMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) active_irqs = (port_in ^ port_comp) & port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (active_irqs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* check if we are detecting fake edges ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (ecfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* edge detection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) val = st_gpio_get(&bank->gpio_chip, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) writel(BIT(n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) val ? bank->base + REG_PIO_SET_PCOMP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) bank->base + REG_PIO_CLR_PCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ecfg != ST_IRQ_EDGE_BOTH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static void st_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* interrupt dedicated per bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct st_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) __gpio_irq_handler(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static void st_gpio_irqmux_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct st_pinctrl *info = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) status = readl(info->irqmux_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) for_each_set_bit(n, &status, info->nbanks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) __gpio_irq_handler(&info->banks[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static const struct gpio_chip st_gpio_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .get = st_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .set = st_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .direction_input = st_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .direction_output = st_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .get_direction = st_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .ngpio = ST_GPIO_PINS_PER_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static struct irq_chip st_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .name = "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .irq_request_resources = st_gpio_irq_request_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .irq_release_resources = st_gpio_irq_release_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .irq_disable = st_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .irq_mask = st_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .irq_unmask = st_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .irq_set_type = st_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static int st_gpiolib_register_bank(struct st_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int bank_nr, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct st_gpio_bank *bank = &info->banks[bank_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct pinctrl_gpio_range *range = &bank->range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int bank_num = of_alias_get_id(np, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct resource res, irq_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (of_address_to_resource(np, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) bank->base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (IS_ERR(bank->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return PTR_ERR(bank->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) bank->gpio_chip = st_gpio_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) bank->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) bank->gpio_chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) spin_lock_init(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) of_property_read_string(np, "st,bank-name", &range->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) bank->gpio_chip.label = range->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) range->id = bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) range->npins = bank->gpio_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) range->gc = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * GPIO bank can have one of the two possible types of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * interrupt-wirings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * First type is via irqmux, single interrupt is used by multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * gpio banks. This reduces number of overall interrupts numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * required. All these banks belong to a single pincontroller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * _________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * | |----> [gpio-bank (n) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * | |----> [gpio-bank (n + 1)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * | |----> [gpio-bank (... )]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * |_________|----> [gpio-bank (n + 7)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * Second type has a dedicated interrupt per each gpio bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * [irqN]----> [gpio-bank (n)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (of_irq_to_resource(np, 0, &irq_res) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) int gpio_irq = irq_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* This is not a valid IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (gpio_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dev_err(dev, "invalid IRQ for %pOF bank\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) goto skip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* We need to have a mux as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (!info->irqmux_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dev_err(dev, "no irqmux for %pOF bank\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) goto skip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) girq = &bank->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) girq->chip = &st_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) girq->parent_handler = st_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) girq->parents[0] = gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) skip_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) err = gpiochip_add_data(&bank->gpio_chip, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_info(dev, "%s bank added.\n", range->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static const struct of_device_id st_pctl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int st_pctl_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int i = 0, j = 0, k = 0, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct pinctrl_pin_desc *pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) int grp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) st_pctl_dt_child_count(info, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (!info->nbanks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_err(&pdev->dev, "you need atleast one gpio bank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) info->functions = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) info->groups = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) info->ngroups, sizeof(*info->groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) info->banks = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) info->nbanks, sizeof(*info->banks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (!info->functions || !info->groups || !info->banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (IS_ERR(info->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dev_err(info->dev, "No syscfg phandle specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return PTR_ERR(info->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) info->data = of_match_node(st_pctl_of_match, np)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) IORESOURCE_MEM, "irqmux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (IS_ERR(info->irqmux_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return PTR_ERR(info->irqmux_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pdesc = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (!pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) pctl_desc->pins = pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) bank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (of_property_read_bool(child, "gpio-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) const char *bank_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ret = st_gpiolib_register_bank(info, bank, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) k = info->banks[bank].range.pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) bank_name = info->banks[bank].range.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pdesc->number = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) bank_name, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pdesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) st_parse_syscfgs(info, bank, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) bank++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ret = st_pctl_parse_functions(child, info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) i++, &grp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dev_err(&pdev->dev, "No functions found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static int st_pctl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct st_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct pinctrl_desc *pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) dev_err(&pdev->dev, "device node not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (!pctl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = st_pctl_probe_dt(pdev, pctl_desc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pctl_desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) pctl_desc->pctlops = &st_pctlops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) pctl_desc->pmxops = &st_pmxops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) pctl_desc->confops = &st_confops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) pctl_desc->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (IS_ERR(info->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_err(&pdev->dev, "Failed pinctrl registration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return PTR_ERR(info->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) for (i = 0; i < info->nbanks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static struct platform_driver st_pctl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .name = "st-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .of_match_table = st_pctl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .probe = st_pctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static int __init st_pctl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return platform_driver_register(&st_pctl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) arch_initcall(st_pctl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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