^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Generic device tree based pinctrl driver for one register per pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * type pinmux controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/pinctrl-single.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "devicetree.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_NAME "pinctrl-single"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCS_OFF_DISABLED ~0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct pcs_func_vals - mux function register offset and value pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @reg: register virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @val: register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @mask: mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pcs_func_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * struct pcs_conf_vals - pinconf parameter, pinconf register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * and value, enable, disable, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @param: config parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @val: user input bits in the pinconf register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @enable: enable bits in the pinconf register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @disable: disable bits in the pinconf register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @mask: mask bits in the register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pcs_conf_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * struct pcs_conf_type - pinconf property name, pinconf param pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @name: property name in DTS file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @param: config parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pcs_conf_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * struct pcs_function - pinctrl function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @name: pinctrl function name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @vals: register and vals array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @nvals: number of entries in vals array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @pgnames: array of pingroup names the function uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @npgnames: number of pingroup names the function uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @conf: array of pin configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @nconfs: number of pin configurations available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @node: list node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pcs_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct pcs_func_vals *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned nvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const char **pgnames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int npgnames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pcs_conf_vals *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int nconfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @offset: offset base of pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @npins: number pins with the same mux value of gpio function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @gpiofunc: mux value of gpio function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @node: list node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pcs_gpiofunc_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned gpiofunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct pcs_data - wrapper for data needed by pinctrl framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @pa: pindesc array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @cur: index to current element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * REVISIT: We should be able to drop this eventually by adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * support for registering pins individually in the pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * framework for those drivers that don't need a static array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pcs_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct pinctrl_pin_desc *pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * struct pcs_soc_data - SoC specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @flags: initial SoC specific PCS_FEAT_xxx values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @irq: optional interrupt for the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @irq_enable_mask: optional SoC specific interrupt enable mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @irq_status_mask: optional SoC specific interrupt status mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @rearm: optional SoC specific wake-up rearm function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pcs_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned irq_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned irq_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void (*rearm)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * struct pcs_device - pinctrl device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @res: resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @base: virtual address of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @saved_vals: saved values for the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @size: size of the ioremapped area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @dev: device entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @np: device tree node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @pctl: pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @flags: mask of PCS_FEAT_xxx values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @missing_nr_pinctrl_cells: for legacy binding, may go away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @socdata: soc specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @lock: spinlock for register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @mutex: mutex protecting the lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @width: bits per mux register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @fmask: function register mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @fshift: function register shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @foff: value to turn mux off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @fmax: max number of functions in fmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @bits_per_mux: number of bits per mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @bits_per_pin: number of bits per pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @pins: physical pins on the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @gpiofuncs: list of gpio functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @irqs: list of interrupt registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @chip: chip container for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @domain: IRQ domain for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @desc: pin controller descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @read: register read function to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @write: register write function to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pcs_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void *saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCS_CONTEXT_LOSS_OFF (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCS_QUIRK_SHARED_IRQ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCS_FEAT_IRQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCS_FEAT_PINCONF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct property *missing_nr_pinctrl_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pcs_soc_data socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned fmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned fshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned foff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned fmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool bits_per_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct pcs_data pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct list_head gpiofuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct list_head irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pinctrl_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned (*read)(void __iomem *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void (*write)(unsigned val, void __iomem *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long *configs, unsigned num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static enum pin_config_param pcs_bias[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PIN_CONFIG_BIAS_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PIN_CONFIG_BIAS_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * This lock class tells lockdep that irqchip core that this single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * pinctrl can be in a different category than its parents, so it won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * report false recursion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct lock_class_key pcs_lock_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Class for the IRQ request mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct lock_class_key pcs_request_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * REVISIT: Reads and writes could eventually use regmap or something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * generic. But at least on omaps, some mux registers are performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * critical as they may need to be remuxed every time before and after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * idle. Adding tests for register access width for every read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * write like regmap is doing is not desired, and caching the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * does not help in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static unsigned __maybe_unused pcs_readb(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return readb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static unsigned __maybe_unused pcs_readw(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return readw(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static unsigned __maybe_unused pcs_readl(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writeb(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writew(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (pcs->bits_per_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int pin_offset_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return (pin_offset_bytes / mux_bytes) * mux_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return pin * mux_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) size_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) offset = pcs_pin_reg_offset_get(pcs, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val = pcs->read(pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (pcs->bits_per_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pa = pcs->res->start + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) devm_kfree(pcs->dev, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct pinctrl_map **map, unsigned *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct pinctrl_ops pcs_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .pin_dbg_show = pcs_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .dt_node_to_map = pcs_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .dt_free_map = pcs_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pcs_function **func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) const struct pinctrl_setting_mux *setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct function_desc *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned fselector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* If pin is not described in DTS & enabled, mux_setting is NULL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) setting = pdesc->mux_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fselector = setting->func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) function = pinmux_generic_get_function(pctldev, fselector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *func = function->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!(*func)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(pcs->dev, "%s could not find function%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __func__, fselector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct function_desc *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct pcs_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* If function mask is null, needn't enable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!pcs->fmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) function = pinmux_generic_get_function(pctldev, fselector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) func = function->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(pcs->dev, "enabling %s function%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) func->name, fselector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = 0; i < func->nvals; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct pcs_func_vals *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) vals = &func->vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) raw_spin_lock_irqsave(&pcs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val = pcs->read(vals->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (pcs->bits_per_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mask = vals->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mask = pcs->fmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val |= (vals->val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pcs->write(val, vals->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) raw_spin_unlock_irqrestore(&pcs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int pcs_request_gpio(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pinctrl_gpio_range *range, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct pcs_gpiofunc_range *frange = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct list_head *pos, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* If function mask is null, return directly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!pcs->fmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) frange = list_entry(pos, struct pcs_gpiofunc_range, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (pin >= frange->offset + frange->npins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) || pin < frange->offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) offset = pcs_pin_reg_offset_get(pcs, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (pcs->bits_per_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) data = pcs->read(pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) data &= ~(pcs->fmask << pin_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) data |= frange->gpiofunc << pin_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pcs->write(data, pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) data = pcs->read(pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) data &= ~pcs->fmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) data |= frange->gpiofunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pcs->write(data, pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct pinmux_ops pcs_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .set_mux = pcs_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .gpio_request_enable = pcs_request_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Clear BIAS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) config = pinconf_to_config_packed(pcs_bias[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pcs_pinconf_set(pctldev, pin, &config, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) config = pinconf_to_config_packed(pcs_bias[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!pcs_pinconf_get(pctldev, pin, &config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct pcs_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned offset = 0, data = 0, i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = pcs_get_function(pctldev, pin, &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < func->nconfs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (param == PIN_CONFIG_BIAS_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (pcs_pinconf_bias_disable(pctldev, pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else if (param != func->conf[i].param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) offset = pin * (pcs->width / BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) data = pcs->read(pcs->base + offset) & func->conf[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (func->conf[i].param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* 4 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if ((data != func->conf[i].enable) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (data == func->conf[i].disable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* 2 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case PIN_CONFIG_INPUT_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) for (j = 0; j < func->nconfs; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) switch (func->conf[j].param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (data != func->conf[j].enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *config = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *config = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct pcs_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned offset = 0, shift = 0, i, data, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = pcs_get_function(pctldev, pin, &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) for (j = 0; j < num_configs; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < func->nconfs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (pinconf_to_config_param(configs[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) != func->conf[i].param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) offset = pin * (pcs->width / BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) data = pcs->read(pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) arg = pinconf_to_config_argument(configs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) switch (func->conf[i].param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* 2 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case PIN_CONFIG_INPUT_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) shift = ffs(func->conf[i].mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) data &= ~func->conf[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) data |= (arg << shift) & func->conf[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* 4 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pcs_pinconf_clear_bias(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pcs_pinconf_clear_bias(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) data &= ~func->conf[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) data |= func->conf[i].enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) data |= func->conf[i].disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pcs->write(data, pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (i >= func->nconfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned group, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned npins, old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (pcs_pinconf_get(pctldev, pins[i], config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* configs do not match between two pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (i && (old != *config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) old = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct seq_file *s, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct seq_file *s, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pinconf_generic_dump_config(pctldev, s, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static const struct pinconf_ops pcs_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .pin_config_get = pcs_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .pin_config_set = pcs_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .pin_config_group_get = pcs_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .pin_config_group_set = pcs_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .pin_config_dbg_show = pcs_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * pcs_add_pin() - add a pin to the static per controller pin array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * @offset: register offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct pcs_soc_data *pcs_soc = &pcs->socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct pinctrl_pin_desc *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) i = pcs->pins.cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (i >= pcs->desc.npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_err(pcs->dev, "too many pins, max %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pcs->desc.npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (pcs_soc->irq_enable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) val = pcs->read(pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (val & pcs_soc->irq_enable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (unsigned long)pcs->res->start + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val &= ~pcs_soc->irq_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pcs->write(val, pcs->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pin = &pcs->pins.pa[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pin->number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pcs->pins.cur++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * In case of errors, resources are freed in pcs_free_resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * If your hardware needs holes in the address space, then just set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * up multiple driver instances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int pcs_allocate_pin_table(struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int mux_bytes, nr_pins, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int num_pins_in_register = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mux_bytes = pcs->width / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (pcs->bits_per_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pcs->bits_per_pin = fls(pcs->fmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) num_pins_in_register = pcs->width / pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) nr_pins = pcs->size / mux_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pcs->pins.pa = devm_kcalloc(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) nr_pins, sizeof(*pcs->pins.pa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!pcs->pins.pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pcs->desc.pins = pcs->pins.pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pcs->desc.npins = nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) for (i = 0; i < pcs->desc.npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) offset = pcs_pin_reg_offset_get(pcs, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) res = pcs_add_pin(pcs, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(pcs->dev, "error adding pins: %i\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * pcs_add_function() - adds a new function to the function list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * @fcn: new function allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * @name: name of the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * @vals: array of mux register value pairs used by the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * @nvals: number of mux register value pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * @pgnames: array of pingroup names for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * @npgnames: number of pingroup names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int pcs_add_function(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct pcs_function **fcn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct pcs_func_vals *vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned int nvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) const char **pgnames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned int npgnames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct pcs_function *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) function->vals = vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) function->nvals = nvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) selector = pinmux_generic_add_function(pcs->pctl, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pgnames, npgnames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (selector < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) devm_kfree(pcs->dev, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *fcn = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *fcn = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * pcs_get_pin_by_offset() - get a pin index based on the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * @offset: register offset from the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Note that this is OK as long as the pins are in a static array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (offset >= pcs->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) offset, pcs->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (pcs->bits_per_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) index = offset / (pcs->width / BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * check whether data matches enable bits or disable bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * Return value: 1 for matching enable bits, 0 for matching disable bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * and negative value for matching failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (data == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else if (data == disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned value, unsigned enable, unsigned disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) (*conf)->param = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (*conf)->val = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) (*conf)->enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (*conf)->disable = disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) (*conf)->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) (*conf)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void add_setting(unsigned long **setting, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) **setting = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) (*setting)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* add pinconf setting with 2 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) const char *name, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct pcs_conf_vals **conf, unsigned long **settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned value[2], shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = of_property_read_u32_array(np, name, value, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* set value & mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) value[0] &= value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) shift = ffs(value[1]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* skip enable & disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) add_config(conf, param, value[0], 0, 0, value[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) add_setting(settings, param, value[0] >> shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* add pinconf setting with 4 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) const char *name, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct pcs_conf_vals **conf, unsigned long **settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned value[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* value to set, enable, disable, mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = of_property_read_u32_array(np, name, value, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!value[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(pcs->dev, "mask field of the property can't be 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) value[0] &= value[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) value[1] &= value[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) value[2] &= value[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = pcs_config_match(value[0], value[1], value[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) add_config(conf, param, value[0], value[1], value[2], value[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) add_setting(settings, param, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct pcs_function *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct pinctrl_map **map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct pinctrl_map *m = *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int i = 0, nconfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned long *settings = NULL, *s = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct pcs_conf_vals *conf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct pcs_conf_type prop2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct pcs_conf_type prop4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) { "pinctrl-single,input-schmitt-enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* If pinconf isn't supported, don't parse properties in below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!PCS_HAS_PINCONF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* cacluate how much properties are supported in current node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) for (i = 0; i < ARRAY_SIZE(prop2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (of_find_property(np, prop2[i].name, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) nconfs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) for (i = 0; i < ARRAY_SIZE(prop4); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (of_find_property(np, prop4[i].name, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) nconfs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!nconfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) func->conf = devm_kcalloc(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) nconfs, sizeof(struct pcs_conf_vals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!func->conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) func->nconfs = nconfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) conf = &(func->conf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) m++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) s = &settings[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) for (i = 0; i < ARRAY_SIZE(prop2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &conf, &s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) for (i = 0; i < ARRAY_SIZE(prop4); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) &conf, &s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) m->data.configs.group_or_pin = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) m->data.configs.configs = settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) m->data.configs.num_configs = nconfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * @pcs: pinctrl driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @np: device node of the mux entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * @map: map entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * @num_maps: number of map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * @pgnames: pingroup names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Note that this binding currently supports only sets of one register + value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Also note that this driver tries to avoid understanding pin and function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * names because of the extra bloat they would cause especially in the case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * a large number of pins. This driver just sets what is specified for the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * in the .dts file. Further user space debugging tools can be developed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * decipher the pin and function names using debugfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * If you are concerned about the boot time, set up the static pins in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * the bootloader, and only set up selected pins as device tree entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned *num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) const char **pgnames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const char *name = "pinctrl-single,pins";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct pcs_func_vals *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct pcs_function *function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) rows = pinctrl_count_index_with_args(np, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (rows <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!vals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) goto free_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) for (i = 0; i < rows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct of_phandle_args pinctrl_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_err(pcs->dev, "invalid args_count for spec: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pinctrl_spec.args_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) offset = pinctrl_spec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) vals[found].reg = pcs->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) switch (pinctrl_spec.args_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) vals[found].val = pinctrl_spec.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pinctrl_spec.np, offset, vals[found].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pin = pcs_get_pin_by_offset(pcs, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (pin < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_err(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "could not add functions for %pOFn %ux\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) np, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pins[found++] = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pgnames[0] = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) mutex_lock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) fsel = pcs_add_function(pcs, &function, np->name, vals, found,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pgnames, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (fsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) res = fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) goto free_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (gsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) res = gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto free_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) (*map)->data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) (*map)->data.mux.function = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (PCS_HAS_PINCONF && function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) res = pcs_parse_pinconf(pcs, np, function, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (res == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) *num_maps = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else if (res == -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) goto free_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) free_pingroups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pinctrl_generic_remove_group(pcs->pctl, gsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) free_function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pinmux_generic_remove_function(pcs->pctl, fsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) free_pins:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) devm_kfree(pcs->dev, pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) free_vals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) devm_kfree(pcs->dev, vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) unsigned *num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) const char **pgnames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) const char *name = "pinctrl-single,bits";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct pcs_func_vals *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int npins_in_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct pcs_function *function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) rows = pinctrl_count_index_with_args(np, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (rows <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) npins_in_row = pcs->width / pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) vals = devm_kzalloc(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) array3_size(rows, npins_in_row, sizeof(*vals)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!vals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pins = devm_kzalloc(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) array3_size(rows, npins_in_row, sizeof(*pins)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto free_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) for (i = 0; i < rows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct of_phandle_args pinctrl_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned offset, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned mask, bit_pos, val_pos, mask_pos, submask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned pin_num_from_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (pinctrl_spec.args_count < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(pcs->dev, "invalid args_count for spec: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pinctrl_spec.args_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Index plus two value cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) offset = pinctrl_spec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) val = pinctrl_spec.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) mask = pinctrl_spec.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pinctrl_spec.np, offset, val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Parse pins in each row from LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) bit_pos = __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mask_pos = ((pcs->fmask) << bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) val_pos = val & mask_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) submask = mask & mask_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if ((mask & mask_pos) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "Invalid mask for %pOFn at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) np, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mask &= ~mask_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (submask != mask_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dev_warn(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) "Invalid submask 0x%x for %pOFn at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) submask, np, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) vals[found].mask = submask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) vals[found].reg = pcs->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) vals[found].val = val_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pin = pcs_get_pin_by_offset(pcs, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (pin < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(pcs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "could not add functions for %pOFn %ux\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) np, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pins[found++] = pin + pin_num_from_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pgnames[0] = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mutex_lock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) fsel = pcs_add_function(pcs, &function, np->name, vals, found,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pgnames, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (fsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) res = fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) goto free_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (gsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) res = gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto free_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) (*map)->data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) (*map)->data.mux.function = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (PCS_HAS_PINCONF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) dev_err(pcs->dev, "pinconf not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) res = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) goto free_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) free_pingroups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pinctrl_generic_remove_group(pcs->pctl, gsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) free_function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pinmux_generic_remove_function(pcs->pctl, fsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) free_pins:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) devm_kfree(pcs->dev, pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) free_vals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) devm_kfree(pcs->dev, vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * pcs_dt_node_to_map() - allocates and parses pinctrl maps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * @pctldev: pinctrl instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * @np_config: device tree pinmux entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * @map: array of map entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * @num_maps: number of maps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) const char **pgnames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) pcs = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* create 2 maps. One is for pinmux, and the other is for pinconf. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (!*map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!pgnames) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto free_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (pcs->bits_per_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) num_maps, pgnames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_err(pcs->dev, "no pins entries for %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) np_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) goto free_pgnames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) num_maps, pgnames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(pcs->dev, "no pins entries for %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) np_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) goto free_pgnames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) free_pgnames:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) devm_kfree(pcs->dev, pgnames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) free_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) devm_kfree(pcs->dev, *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * pcs_irq_free() - free interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static void pcs_irq_free(struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct pcs_soc_data *pcs_soc = &pcs->socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (pcs_soc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (pcs->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) irq_domain_remove(pcs->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (PCS_QUIRK_HAS_SHARED_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) free_irq(pcs_soc->irq, pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) irq_set_chained_handler(pcs_soc->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * pcs_free_resources() - free memory used by this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static void pcs_free_resources(struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pcs_irq_free(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pinctrl_unregister(pcs->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (pcs->missing_nr_pinctrl_cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) const char *propname = "pinctrl-single,gpio-range";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) const char *cellname = "#pinctrl-single,gpio-range-cells";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct of_phandle_args gpiospec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct pcs_gpiofunc_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) for (i = 0; ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ret = of_parse_phandle_with_args(node, propname, cellname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) i, &gpiospec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Do not treat it as error. Only treat it as end condition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) range->offset = gpiospec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) range->npins = gpiospec.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) range->gpiofunc = gpiospec.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mutex_lock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) list_add_tail(&range->node, &pcs->gpiofuncs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * struct pcs_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * @reg: virtual address of interrupt register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * @hwirq: hardware irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * @irq: virtual irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * @node: list node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct pcs_interrupt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * pcs_irq_set() - enables or disables an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * @pcs_soc: SoC specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * @irq: interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * @enable: enable or disable the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Note that this currently assumes one interrupt per pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * register that is typically used for wake-up events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) int irq, const bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pcs = container_of(pcs_soc, struct pcs_device, socdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) list_for_each(pos, &pcs->irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct pcs_interrupt *pcswi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) unsigned soc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pcswi = list_entry(pos, struct pcs_interrupt, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (irq != pcswi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) soc_mask = pcs_soc->irq_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) raw_spin_lock(&pcs->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) mask = pcs->read(pcswi->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) mask |= soc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mask &= ~soc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) pcs->write(mask, pcswi->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mask = pcs->read(pcswi->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) raw_spin_unlock(&pcs->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (pcs_soc->rearm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pcs_soc->rearm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * pcs_irq_mask() - mask pinctrl interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * @d: interrupt data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static void pcs_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) pcs_irq_set(pcs_soc, d->irq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * pcs_irq_unmask() - unmask pinctrl interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * @d: interrupt data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static void pcs_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pcs_irq_set(pcs_soc, d->irq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * pcs_irq_set_wake() - toggle the suspend and resume wake up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * @d: interrupt data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * @state: wake-up state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * Note that this should be called only for suspend and resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * For runtime PM, the wake-up events should be enabled by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pcs_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) pcs_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * pcs_irq_handle() - common interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * @pcs_soc: SoC specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * Note that this currently assumes we have one interrupt bit per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * mux register. This interrupt is typically used for wake-up events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * For more complex interrupts different handlers can be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pcs = container_of(pcs_soc, struct pcs_device, socdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) list_for_each(pos, &pcs->irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct pcs_interrupt *pcswi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) pcswi = list_entry(pos, struct pcs_interrupt, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) raw_spin_lock(&pcs->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) mask = pcs->read(pcswi->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) raw_spin_unlock(&pcs->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (mask & pcs_soc->irq_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) generic_handle_irq(irq_find_mapping(pcs->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) pcswi->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * pcs_irq_handler() - handler for the shared interrupt case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * @irq: interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * @d: data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * Use this for cases where multiple instances of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * pinctrl-single share a single interrupt like on omaps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static irqreturn_t pcs_irq_handler(int irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct pcs_soc_data *pcs_soc = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * pcs_irq_handle() - handler for the dedicated chained interrupt case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * @desc: interrupt descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * Use this if you have a separate interrupt for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * pinctrl-single instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static void pcs_irq_chain_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pcs_irq_handle(pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* REVISIT: export and add handle_bad_irq(irq, desc)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct pcs_soc_data *pcs_soc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct pcs_interrupt *pcswi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pcs = container_of(pcs_soc, struct pcs_device, socdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (!pcswi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pcswi->reg = pcs->base + hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) pcswi->hwirq = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pcswi->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) mutex_lock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) list_add_tail(&pcswi->node, &pcs->irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mutex_unlock(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) irq_set_chip_data(irq, pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) irq_set_chip_and_handler(irq, &pcs->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct irq_domain_ops pcs_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .map = pcs_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * pcs_irq_init_chained_handler() - set up a chained interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * @pcs: pcs driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * @np: device node pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct pcs_soc_data *pcs_soc = &pcs->socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) const char *name = "pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) int num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!pcs_soc->irq_enable_mask ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) !pcs_soc->irq_status_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) pcs_soc->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) INIT_LIST_HEAD(&pcs->irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pcs->chip.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pcs->chip.irq_ack = pcs_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pcs->chip.irq_mask = pcs_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) pcs->chip.irq_unmask = pcs_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) pcs->chip.irq_set_wake = pcs_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (PCS_QUIRK_HAS_SHARED_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) res = request_irq(pcs_soc->irq, pcs_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) IRQF_SHARED | IRQF_NO_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) name, pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) pcs_soc->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) irq_set_chained_handler_and_data(pcs_soc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) pcs_irq_chain_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * We can use the register offset as the hardirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * number as irq_domain_add_simple maps them lazily.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * This way we can easily support more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * interrupt per function if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) num_irqs = pcs->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) &pcs_irqdomain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pcs_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (!pcs->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) irq_set_chained_handler(pcs_soc->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static int pcs_save_context(struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) int i, mux_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) u64 *regsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 *regsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) u16 *regshw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) mux_bytes = pcs->width / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!pcs->saved_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!pcs->saved_vals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) switch (pcs->width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) regsl = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) *regsl++ = pcs->read(pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) regsw = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) *regsw++ = pcs->read(pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) regshw = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) *regshw++ = pcs->read(pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static void pcs_restore_context(struct pcs_device *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) int i, mux_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u64 *regsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u32 *regsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u16 *regshw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) mux_bytes = pcs->width / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) switch (pcs->width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) regsl = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pcs->write(*regsl++, pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) regsw = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) pcs->write(*regsw++, pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) regshw = pcs->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) for (i = 0; i < pcs->size; i += mux_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) pcs->write(*regshw++, pcs->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int pinctrl_single_suspend(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pcs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = pcs_save_context(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return pinctrl_force_sleep(pcs->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static int pinctrl_single_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) pcs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (!pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) pcs_restore_context(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return pinctrl_force_default(pcs->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * pcs_quirk_missing_pinctrl_cells - handle legacy binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * @pcs: pinctrl driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * @np: device tree node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * @cells: number of cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * Handle legacy binding with no #pinctrl-cells. This should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * always two pinctrl-single,bit-per-mux and one for others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * At some point we may want to consider removing this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) int cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct property *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) const char *name = "#pinctrl-cells";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) error = of_property_read_u32(np, name, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) name, cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) p->length = sizeof(__be32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (!p->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) *(__be32 *)p->value = cpu_to_be32(cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (!p->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) pcs->missing_nr_pinctrl_cells = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static int pcs_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) struct pcs_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct pcs_device *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) const struct pcs_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (WARN_ON(!soc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (!pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) pcs->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) pcs->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) raw_spin_lock_init(&pcs->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) mutex_init(&pcs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) INIT_LIST_HEAD(&pcs->gpiofuncs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) pcs->flags = soc->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) memcpy(&pcs->socdata, soc, sizeof(*soc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ret = of_property_read_u32(np, "pinctrl-single,register-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) &pcs->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dev_err(pcs->dev, "register width not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = of_property_read_u32(np, "pinctrl-single,function-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) &pcs->fmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) pcs->fshift = __ffs(pcs->fmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) pcs->fmax = pcs->fmask >> pcs->fshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* If mask property doesn't exist, function mux is invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pcs->fmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pcs->fshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) pcs->fmax = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ret = of_property_read_u32(np, "pinctrl-single,function-off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) &pcs->foff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) pcs->foff = PCS_OFF_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pcs->bits_per_mux = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) "pinctrl-single,bit-per-mux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) pcs->bits_per_mux ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_err(pcs->dev, "could not get resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) pcs->res = devm_request_mem_region(pcs->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) resource_size(res), DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (!pcs->res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dev_err(pcs->dev, "could not get mem_region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pcs->size = resource_size(pcs->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (!pcs->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) dev_err(pcs->dev, "could not ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) platform_set_drvdata(pdev, pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) switch (pcs->width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pcs->read = pcs_readb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) pcs->write = pcs_writeb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) pcs->read = pcs_readw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) pcs->write = pcs_writew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) pcs->read = pcs_readl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) pcs->write = pcs_writel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pcs->desc.name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) pcs->desc.pctlops = &pcs_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pcs->desc.pmxops = &pcs_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (PCS_HAS_PINCONF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) pcs->desc.confops = &pcs_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) pcs->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ret = pcs_allocate_pin_table(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dev_err(pcs->dev, "could not register single pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ret = pcs_add_gpio_func(np, pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) pcs->socdata.irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (pcs->socdata.irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) pcs->flags |= PCS_FEAT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* We still need auxdata for some omaps for PRM interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (pdata->rearm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pcs->socdata.rearm = pdata->rearm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (pdata->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) pcs->socdata.irq = pdata->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) pcs->flags |= PCS_FEAT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (PCS_HAS_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) ret = pcs_irq_init_chained_handler(pcs, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) dev_warn(pcs->dev, "initialized with no interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return pinctrl_enable(pcs->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pcs_free_resources(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static int pcs_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct pcs_device *pcs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (!pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) pcs_free_resources(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static const struct pcs_soc_data pinctrl_single_omap_wkup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .flags = PCS_QUIRK_SHARED_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static const struct pcs_soc_data pinctrl_single_dra7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static const struct pcs_soc_data pinctrl_single_am437x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static const struct pcs_soc_data pinctrl_single = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const struct pcs_soc_data pinconf_single = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .flags = PCS_FEAT_PINCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const struct of_device_id pcs_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) { .compatible = "pinctrl-single", .data = &pinctrl_single },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) { .compatible = "pinconf-single", .data = &pinconf_single },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) MODULE_DEVICE_TABLE(of, pcs_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static struct platform_driver pcs_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .probe = pcs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .remove = pcs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .of_match_table = pcs_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .suspend = pinctrl_single_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .resume = pinctrl_single_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) module_platform_driver(pcs_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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