^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With some ideas taken from pinctrl-samsung:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * https://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * and pinctrl-at91:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef _PINCTRL_ROCKCHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define _PINCTRL_ROCKCHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK_GPIO0_A0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RK_GPIO0_A1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RK_GPIO0_A2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RK_GPIO0_A3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RK_GPIO0_A4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RK_GPIO0_A5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RK_GPIO0_A6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RK_GPIO0_A7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RK_GPIO0_B0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK_GPIO0_B1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK_GPIO0_B2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RK_GPIO0_B3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RK_GPIO0_B4 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RK_GPIO0_B5 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RK_GPIO0_B6 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RK_GPIO0_B7 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RK_GPIO0_C0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RK_GPIO0_C1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RK_GPIO0_C2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RK_GPIO0_C3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RK_GPIO0_C4 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RK_GPIO0_C5 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RK_GPIO0_C6 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RK_GPIO0_C7 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RK_GPIO0_D0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RK_GPIO0_D1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RK_GPIO0_D2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RK_GPIO0_D3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RK_GPIO0_D4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RK_GPIO0_D5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RK_GPIO0_D6 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK_GPIO0_D7 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RK_GPIO1_A0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RK_GPIO1_A1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK_GPIO1_A2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK_GPIO1_A3 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK_GPIO1_A4 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK_GPIO1_A5 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK_GPIO1_A6 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK_GPIO1_A7 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RK_GPIO1_B0 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK_GPIO1_B1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RK_GPIO1_B2 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RK_GPIO1_B3 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RK_GPIO1_B4 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RK_GPIO1_B5 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RK_GPIO1_B6 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RK_GPIO1_B7 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RK_GPIO1_C0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RK_GPIO1_C1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RK_GPIO1_C2 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RK_GPIO1_C3 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK_GPIO1_C4 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK_GPIO1_C5 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK_GPIO1_C6 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK_GPIO1_C7 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK_GPIO1_D0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK_GPIO1_D1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RK_GPIO1_D2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK_GPIO1_D3 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RK_GPIO1_D4 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RK_GPIO1_D5 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RK_GPIO1_D6 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RK_GPIO1_D7 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RK_GPIO2_A0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RK_GPIO2_A1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RK_GPIO2_A2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK_GPIO2_A3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RK_GPIO2_A4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RK_GPIO2_A5 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RK_GPIO2_A6 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RK_GPIO2_A7 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RK_GPIO2_B0 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RK_GPIO2_B1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RK_GPIO2_B2 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RK_GPIO2_B3 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RK_GPIO2_B4 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RK_GPIO2_B5 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RK_GPIO2_B6 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RK_GPIO2_B7 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RK_GPIO2_C0 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RK_GPIO2_C1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RK_GPIO2_C2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RK_GPIO2_C3 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RK_GPIO2_C4 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RK_GPIO2_C5 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RK_GPIO2_C6 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RK_GPIO2_C7 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RK_GPIO2_D0 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RK_GPIO2_D1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RK_GPIO2_D2 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RK_GPIO2_D3 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RK_GPIO2_D4 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RK_GPIO2_D5 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RK_GPIO2_D6 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RK_GPIO2_D7 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RK_GPIO3_A0 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RK_GPIO3_A1 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RK_GPIO3_A2 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RK_GPIO3_A3 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RK_GPIO3_A4 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RK_GPIO3_A5 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RK_GPIO3_A6 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RK_GPIO3_A7 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RK_GPIO3_B0 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RK_GPIO3_B1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RK_GPIO3_B2 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RK_GPIO3_B3 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RK_GPIO3_B4 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RK_GPIO3_B5 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RK_GPIO3_B6 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RK_GPIO3_B7 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RK_GPIO3_C0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RK_GPIO3_C1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RK_GPIO3_C2 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RK_GPIO3_C3 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RK_GPIO3_C4 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RK_GPIO3_C5 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RK_GPIO3_C6 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RK_GPIO3_C7 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RK_GPIO3_D0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RK_GPIO3_D1 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RK_GPIO3_D2 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RK_GPIO3_D3 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RK_GPIO3_D4 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RK_GPIO3_D5 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RK_GPIO3_D6 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RK_GPIO3_D7 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RK_GPIO4_A0 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RK_GPIO4_A1 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RK_GPIO4_A2 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RK_GPIO4_A3 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RK_GPIO4_A4 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RK_GPIO4_A5 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RK_GPIO4_A6 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RK_GPIO4_A7 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RK_GPIO4_B0 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RK_GPIO4_B1 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RK_GPIO4_B2 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RK_GPIO4_B3 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RK_GPIO4_B4 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RK_GPIO4_B5 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RK_GPIO4_B6 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RK_GPIO4_B7 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RK_GPIO4_C0 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RK_GPIO4_C1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RK_GPIO4_C2 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RK_GPIO4_C3 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RK_GPIO4_C4 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RK_GPIO4_C5 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RK_GPIO4_C6 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RK_GPIO4_C7 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RK_GPIO4_D0 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RK_GPIO4_D1 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RK_GPIO4_D2 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RK_GPIO4_D3 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RK_GPIO4_D4 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RK_GPIO4_D5 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RK_GPIO4_D6 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RK_GPIO4_D7 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum rockchip_pinctrl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PX30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RV1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) RV1108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RV1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) RK1808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RK2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) RK3066B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RK3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RK3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) RK3308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) RK3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RK3588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * struct rockchip_gpio_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @port_dr: data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @port_ddr: data direction register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @int_en: interrupt enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @int_mask: interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @int_type: interrupt trigger type, such as high, low, edge trriger type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @int_polarity: interrupt polarity enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @int_bothedge: interrupt bothedge enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @int_status: interrupt status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @int_rawstatus: int_status = int_rawstatus & int_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @debounce: enable debounce for interrupt signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @dbclk_div_en: enable divider for debounce clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @dbclk_div_con: setting for divider of debounce clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @port_eoi: end of interrupt of the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @ext_port: port data from external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @version_id: controller version register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct rockchip_gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 port_dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 port_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 int_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 int_bothedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 int_rawstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 dbclk_div_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 dbclk_div_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 port_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 ext_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 version_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * struct rockchip_iomux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @type: iomux variant using IOMUX_* constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @offset: if initialized to -1 it will be autocalculated, by specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * an initial offset value the relevant source offset can be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * to a new value for autocalculating the following iomux registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct rockchip_iomux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * enum type index corresponding to rockchip_perpin_drv_list arrays index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enum rockchip_pin_drv_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DRV_TYPE_IO_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DRV_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DRV_TYPE_IO_1V8_3V0_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DRV_TYPE_IO_3V3_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DRV_TYPE_IO_SMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DRV_TYPE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * enum type index corresponding to rockchip_pull_list arrays index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum rockchip_pin_pull_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PULL_TYPE_IO_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PULL_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PULL_TYPE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * struct rockchip_drv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @drv_type: drive strength variant using rockchip_perpin_drv_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @offset: if initialized to -1 it will be autocalculated, by specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * an initial offset value the relevant source offset can be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * to a new value for autocalculating the following drive strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * registers. if used chips own cal_drv func instead to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * registers offset, the variant could be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct rockchip_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum rockchip_pin_drv_type drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * struct rockchip_pin_bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @dev: the pinctrl device bind to the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @reg_base: register base of the gpio bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @regmap_pull: optional separate register for additional pull settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @clk: clock of the gpio bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @db_clk: clock of the gpio debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @irq: interrupt of the gpio bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @saved_masks: Saved content of GPIO_INTEN at suspend time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @pin_base: first pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @nr_pins: number of pins in this bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @name: name of the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @bank_num: number of the bank, to account for holes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @iomux: array describing the 4 iomux sources of the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @drv: array describing the 4 drive strength sources of the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @pull_type: array describing the 4 pull type sources of the bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @valid: is all necessary information present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @of_node: dt node of this bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @drvdata: common pinctrl basedata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @domain: irqdomain of the gpio bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @gpio_chip: gpiolib chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @grange: gpio range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @slock: spinlock for the gpio bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @recalced_mask: bit mask to indicate a need to recalulate the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @route_mask: bits describing the routing pins of per bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @deferred_output: gpio output settings to be done after gpio bank probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct rockchip_pin_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct regmap *regmap_pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct clk *db_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 saved_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct rockchip_iomux iomux[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct rockchip_drv drv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) enum rockchip_pin_pull_type pull_type[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct rockchip_pinctrl *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pinctrl_gpio_range grange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) raw_spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const struct rockchip_gpio_regs *gpio_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 gpio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 toggle_edge_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 recalced_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 route_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct list_head deferred_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mutex deferred_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * struct rockchip_mux_recalced_data: represent a pin iomux data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @num: bank number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @pin: pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @bit: index at register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @reg: register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @mask: mask bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct rockchip_mux_recalced_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) enum rockchip_mux_route_location {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ROCKCHIP_ROUTE_SAME = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ROCKCHIP_ROUTE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ROCKCHIP_ROUTE_GRF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * struct rockchip_mux_recalced_data: represent a pin iomux data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @bank_num: bank number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @pin: index at register or used to calc index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @func: the min pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * @route_location: the mux route location (same, pmu, grf).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @route_offset: the max pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * @route_val: the register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct rockchip_mux_route_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum rockchip_mux_route_location route_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 route_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 route_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct rockchip_pin_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct rockchip_pin_bank *pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) enum rockchip_pinctrl_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int grf_mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int pmu_mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int grf_drv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int pmu_drv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct rockchip_mux_recalced_data *iomux_recalced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 niomux_recalced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct rockchip_mux_route_data *iomux_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 niomux_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int *reg, u8 *bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int (*drv_calc_reg)(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int *reg, u8 *bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int *reg, u8 *bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int *reg, u8 *bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct rockchip_pin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int nconfigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum pin_config_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct rockchip_pin_deferred {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * struct rockchip_pin_group: represent group of pins of a pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @name: name of the pin group, used to lookup the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @pins: the pins included in this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @npins: number of pins included in this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @data: local pin configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct rockchip_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct rockchip_pin_config *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * struct rockchip_pmx_func: represent a pin function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @name: name of the pin function, used to lookup the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * @groups: one or more names of pin groups that provide this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @ngroups: number of groups included in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct rockchip_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct rockchip_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct regmap *regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct regmap *regmap_pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct regmap *regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct rockchip_pin_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct pinctrl_desc pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct rockchip_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct rockchip_pmx_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #if IS_ENABLED(CONFIG_PINCTRL_ROCKCHIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int rk_iomux_set(int bank, int pin, int mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int rk_iomux_get(int bank, int pin, int *mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline int rk_iomux_set(int bank, int pin, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline int rk_iomux_get(int bank, int pin, int *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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