^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl driver for Rockchip SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With some ideas taken from pinctrl-samsung:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * https://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * and pinctrl-at91:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <dt-bindings/pinctrl/rockchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "pinctrl-rockchip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Generate a bitmask for setting a value (v) with a write mask bit in hiword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * register 31:16 area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WRITE_MASK_VAL(h, l, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Encode variants of iomux registers into a type variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IOMUX_GPIO_ONLY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IOMUX_WIDTH_4BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IOMUX_SOURCE_PMU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IOMUX_UNROUTED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IOMUX_WIDTH_3BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IOMUX_WIDTH_2BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IOMUX_WRITABLE_32BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IOMUX_L_SOURCE_PMU BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PIN_BANK(id, pins, label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .type = iom0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .type = iom1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .type = iom2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .type = iom3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iom3, offset0, offset1, offset2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) offset3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .type = iom0, .offset = offset0 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .type = iom1, .offset = offset1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .type = iom2, .offset = offset2 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .type = iom3, .offset = offset3 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .drv = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .drv_type = type0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .drv_type = type1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .drv_type = type2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .drv_type = type3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iom2, iom3, pull0, pull1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pull2, pull3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .type = iom0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .type = iom1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .type = iom2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .type = iom3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .pull_type[0] = pull0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .pull_type[1] = pull1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .pull_type[2] = pull2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .pull_type[3] = pull3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) drv2, drv3, pull0, pull1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pull2, pull3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .drv = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .drv_type = drv0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .drv_type = drv1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .drv_type = drv2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .drv_type = drv3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .pull_type[0] = pull0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pull_type[1] = pull1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .pull_type[2] = pull2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pull_type[3] = pull3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) iom2, iom3, drv0, drv1, drv2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) drv3, offset0, offset1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) offset2, offset3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .type = iom0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .type = iom1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .type = iom2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .type = iom3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .drv = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .drv_type = drv0, .offset = offset0 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .drv_type = drv1, .offset = offset1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .drv_type = drv2, .offset = offset2 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .drv_type = drv3, .offset = offset3 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) label, iom0, iom1, iom2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) iom3, drv0, drv1, drv2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) drv3, offset0, offset1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) offset2, offset3, pull0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pull1, pull2, pull3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .bank_num = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .iomux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .type = iom0, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .type = iom1, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .type = iom2, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .type = iom3, .offset = -1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .drv = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .drv_type = drv0, .offset = offset0 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .drv_type = drv1, .offset = offset1 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .drv_type = drv2, .offset = offset2 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .drv_type = drv3, .offset = offset3 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .pull_type[0] = pull0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pull_type[1] = pull1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .pull_type[2] = pull2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .pull_type[3] = pull3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .bank_num = ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .pin = PIN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .func = FUNC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .route_offset = REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .route_val = VAL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .route_location = FLAG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MTYPE, MTYPE, MTYPE, MTYPE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DTYPE, DTYPE, DTYPE, DTYPE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) -1, -1, -1, -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct pinctrl_dev *g_pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static DEFINE_MUTEX(iomux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct regmap_config rockchip_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static inline const struct rockchip_pin_group *pinctrl_name_to_group(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < info->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!strcmp(info->groups[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return &info->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * given a pin number that is local to a pin controller, find out the pin bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * and the register base of the pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct rockchip_pin_bank *b = info->ctrl->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (pin >= (b->pin_base + b->nr_pins))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) b++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct rockchip_pin_bank *bank_num_to_bank(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct rockchip_pin_bank *b = info->ctrl->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (b->bank_num == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Pinctrl_ops handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return info->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned selector, const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *pins = info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *npins = info->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const struct rockchip_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct pinctrl_map *new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int map_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * first find the group of this node and check if we need to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * config maps for pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) grp = pinctrl_name_to_group(info, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dev, "unable to find group for node %pOFn\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) map_num += grp->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!new_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *map = new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *num_maps = map_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* create mux map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) parent = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) kfree(new_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) new_map[0].data.mux.function = parent->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) new_map[0].data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* create config map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) new_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) new_map[i].data.configs.group_or_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pin_get_name(pctldev, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) new_map[i].data.configs.configs = grp->data[i].configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_dbg(dev, "maps: function %s group %s num %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (*map)->data.mux.function, (*map)->data.mux.group, map_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct pinctrl_ops rockchip_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .get_groups_count = rockchip_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .get_group_name = rockchip_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .get_group_pins = rockchip_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .dt_node_to_map = rockchip_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .dt_free_map = rockchip_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Hardware access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pin = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .pin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .pin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .pin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .pin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .pin = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .pin = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .pin = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .reg = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .pin = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .reg = 0x41c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .pin = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .reg = 0x41c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .pin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .pin = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .pin = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .pin = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .pin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .reg = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .pin = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .reg = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .pin = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .reg = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .pin = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .reg = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .pin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .reg = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* gpio1b6_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .pin = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .reg = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* gpio1b7_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .pin = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .reg = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* gpio1c2_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .pin = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .reg = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* gpio1c3_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pin = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .reg = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* gpio1c4_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .pin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .reg = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* gpio1c5_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .pin = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .reg = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* gpio1c6_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .pin = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .reg = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* gpio1c7_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .pin = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .reg = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* gpio2a2_sel_plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .pin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .reg = 0x608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* gpio2a3_sel_plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .pin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .reg = 0x608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* gpio2c0_sel_plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .reg = 0x610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* gpio3b2_sel_plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .pin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .reg = 0x610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* gpio3b3_sel_plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pin = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .reg = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* gpio3b4_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .pin = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .reg = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* gpio3b5_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pin = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .reg = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .mask = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .pin = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .pin = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .pin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .pin = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pin = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .pin = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .pin = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .pin = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .reg = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .mask = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pin = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .reg = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .mask = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int *reg, u8 *bit, int *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct rockchip_mux_recalced_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) for (i = 0; i < ctrl->niomux_recalced; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) data = &ctrl->iomux_recalced[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (data->num == bank->bank_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) data->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (i >= ctrl->niomux_recalced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) *reg = data->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *mask = data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *bit = data->bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x190, BIT(16 + 3)), /* i2c2m0_sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x190, BIT(16 + 3) | BIT(3)), /* i2c2m1_sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) RK_MUXROUTE_SAME(1, RK_PA6, 2, 0x190, BIT(16 + 4)), /* spi2m0_miso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x190, BIT(16 + 4) | BIT(4)), /* spi2m1_miso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK_MUXROUTE_SAME(4, RK_PB7, 2, 0x190, BIT(16 + 5)), /* spi1m0_miso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x190, BIT(16 + 5) | BIT(5)), /* spi1m1_miso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RK_MUXROUTE_SAME(4, RK_PB0, 2, 0x190, BIT(16 + 13)), /* uart1_rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RK_MUXROUTE_SAME(1, RK_PB4, 3, 0x190, BIT(16 + 13) | BIT(13)), /* uart1_rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RK_MUXROUTE_SAME(4, RK_PA3, 2, 0x190, BIT(16 + 14) | BIT(16 + 15)), /* uart2_rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) RK_MUXROUTE_SAME(2, RK_PD1, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(14)), /* uart2_rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RK_MUXROUTE_SAME(3, RK_PA4, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(15)), /* uart2_rxm2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static struct rockchip_mux_route_data px30_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) RK_MUXROUTE_GRF(4, RK_PB7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int mux, u32 *loc, u32 *reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct rockchip_mux_route_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (i = 0; i < ctrl->niomux_routes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) data = &ctrl->iomux_routes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if ((data->bank_num == bank->bank_num) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) (data->pin == pin) && (data->func == mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (i >= ctrl->niomux_routes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) *loc = data->route_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) *reg = data->route_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) *value = data->route_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int iomux_num = (pin / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int reg, ret, mask, mux_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (iomux_num > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_err(info->dev, "pin %d is unrouted\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return RK_FUNC_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* get basic quadrupel of mux registers and the correct reg inside */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mux_type = bank->iomux[iomux_num].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) reg = bank->iomux[iomux_num].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (mux_type & IOMUX_WIDTH_4BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if ((pin % 8) >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) reg += 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) bit = (pin % 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) } else if (mux_type & IOMUX_WIDTH_3BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if ((pin % 8) >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) reg += 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) bit = (pin % 8 % 5) * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) mask = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) bit = (pin % 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (bank->recalced_mask & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (ctrl->type == RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u32 reg0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = regmap_read(regmap, reg0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!(val & BIT(8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ((val >> bit) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) reg = reg + 0x8000; /* BUS_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else if (bank->bank_num > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) reg += 0x8000; /* BUS_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = regmap_read(regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return ((val >> bit) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int pin, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int iomux_num = (pin / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (iomux_num > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev_err(dev, "pin %d is unrouted\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (mux != RK_FUNC_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_err(dev, "pin %d only supports a gpio mux\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Set a new mux function for a pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * The register is divided into the upper and lower 16 bit. When changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * a value, the previous register value is not read and changed. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * it seems the changed bits are marked in the upper 16 bit, while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * changed value gets set in the same offset in the lower 16 bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * All pin settings seem to be 2 bit wide in both the upper and lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * @bank: pin bank to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * @pin: pin to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * @mux: new mux function to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int iomux_num = (pin / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int reg, ret, mask, mux_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u32 data, rmask, route_location, route_reg, route_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = rockchip_verify_mux(bank, pin, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* get basic quadrupel of mux registers and the correct reg inside */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mux_type = bank->iomux[iomux_num].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) reg = bank->iomux[iomux_num].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (mux_type & IOMUX_WIDTH_4BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if ((pin % 8) >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) reg += 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) bit = (pin % 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } else if (mux_type & IOMUX_WIDTH_3BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if ((pin % 8) >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) reg += 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) bit = (pin % 8 % 5) * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) mask = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) bit = (pin % 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (bank->recalced_mask & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ctrl->type == RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (mux < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 reg0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) data |= (mux & mask) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = regmap_update_bits(regmap, reg0, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) reg0 = reg + 0x8000; /* BUS_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret |= regmap_update_bits(regmap, reg0, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u32 reg0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) data |= 8 << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = regmap_update_bits(regmap, reg0, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) reg0 = reg + 0x8000; /* BUS_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) data |= (mux & mask) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret |= regmap_update_bits(regmap, reg0, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) data |= (mux & mask) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) } else if (bank->bank_num > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) reg += 0x8000; /* BUS_IOC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (mux > mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (bank->route_mask & BIT(pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (rockchip_get_mux_route(bank, pin, mux, &route_location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &route_reg, &route_val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct regmap *route_regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* handle special locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) switch (route_location) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) case ROCKCHIP_ROUTE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) route_regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case ROCKCHIP_ROUTE_GRF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) route_regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = regmap_write(route_regmap, route_reg, route_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (mux_type & IOMUX_WRITABLE_32BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) data &= ~(mask << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) data |= (mux & mask) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = regmap_write(regmap, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) data = (mask << (bit + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) data |= (mux & mask) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define PX30_PULL_PMU_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define PX30_PULL_GRF_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define PX30_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define PX30_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define PX30_PULL_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* The first 32 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) *reg = PX30_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) *reg = PX30_PULL_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) *bit = (pin_num % PX30_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) *bit *= PX30_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define PX30_DRV_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define PX30_DRV_GRF_OFFSET 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define PX30_DRV_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define PX30_DRV_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define PX30_DRV_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* The first 32 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *reg = PX30_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) *reg = PX30_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) *bit = (pin_num % PX30_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) *bit *= PX30_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define PX30_SCHMITT_PMU_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define PX30_SCHMITT_GRF_OFFSET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define PX30_SCHMITT_PINS_PER_PMU_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define PX30_SCHMITT_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define PX30_SCHMITT_PINS_PER_GRF_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) int pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) *reg = PX30_SCHMITT_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) *reg = PX30_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *reg += ((pin_num / pins_per_reg) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) *bit = pin_num % pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define RV1106_DRV_BITS_PER_PIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define RV1106_DRV_PINS_PER_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define RV1106_DRV_GPIO0_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define RV1106_DRV_GPIO1_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define RV1106_DRV_GPIO2_OFFSET 0x100C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define RV1106_DRV_GPIO3_OFFSET 0x20100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define RV1106_DRV_GPIO4_OFFSET 0x30020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* GPIO0_IOC is located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) switch (bank->bank_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) *reg = RV1106_DRV_GPIO0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) *reg = RV1106_DRV_GPIO1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *reg = RV1106_DRV_GPIO2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) *reg = RV1106_DRV_GPIO3_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) *reg = RV1106_DRV_GPIO4_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) *bit = pin_num % RV1106_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) *bit *= RV1106_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define RV1106_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define RV1106_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define RV1106_PULL_GPIO0_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define RV1106_PULL_GPIO1_OFFSET 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define RV1106_PULL_GPIO2_OFFSET 0x101D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define RV1106_PULL_GPIO3_OFFSET 0x201E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define RV1106_PULL_GPIO4_OFFSET 0x30070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* GPIO0_IOC is located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) switch (bank->bank_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) *reg = RV1106_PULL_GPIO0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) *reg = RV1106_PULL_GPIO1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) *reg = RV1106_PULL_GPIO2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) *reg = RV1106_PULL_GPIO3_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) *reg = RV1106_PULL_GPIO4_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) *bit = pin_num % RV1106_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) *bit *= RV1106_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define RV1106_SMT_BITS_PER_PIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define RV1106_SMT_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define RV1106_SMT_GPIO0_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define RV1106_SMT_GPIO1_OFFSET 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define RV1106_SMT_GPIO2_OFFSET 0x10290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define RV1106_SMT_GPIO3_OFFSET 0x202A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define RV1106_SMT_GPIO4_OFFSET 0x300A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* GPIO0_IOC is located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) switch (bank->bank_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) *reg = RV1106_SMT_GPIO0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) *reg = RV1106_SMT_GPIO1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) *reg = RV1106_SMT_GPIO2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) *reg = RV1106_SMT_GPIO3_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) *reg = RV1106_SMT_GPIO4_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) *bit = pin_num % RV1106_SMT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) *bit *= RV1106_SMT_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define RV1108_PULL_PMU_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define RV1108_PULL_OFFSET 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define RV1108_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define RV1108_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define RV1108_PULL_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) *reg = RV1108_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) *reg = RV1108_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) *bit *= RV1108_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define RV1108_DRV_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define RV1108_DRV_GRF_OFFSET 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define RV1108_DRV_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define RV1108_DRV_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define RV1108_DRV_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) *reg = RV1108_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *reg = RV1108_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) *bit = pin_num % RV1108_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) *bit *= RV1108_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define RV1108_SCHMITT_PMU_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define RV1108_SCHMITT_GRF_OFFSET 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define RV1108_SCHMITT_BANK_STRIDE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) int pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) *reg = RV1108_SCHMITT_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) *reg = RV1108_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) *reg += ((pin_num / pins_per_reg) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) *bit = pin_num % pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define RV1126_PULL_PMU_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define RV1126_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define RV1126_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define RV1126_PULL_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (RV1126_GPIO_C4_D7(pin_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) *bit = pin_num % RV1126_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) *bit *= RV1126_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) *reg = RV1126_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) *bit *= RV1126_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define RV1126_DRV_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define RV1126_DRV_BITS_PER_PIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define RV1126_DRV_PINS_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define RV1126_DRV_BANK_STRIDE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (RV1126_GPIO_C4_D7(pin_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) *reg -= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) *bit = pin_num % RV1126_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) *bit *= RV1126_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) *reg = RV1126_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) *bit = pin_num % RV1126_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) *bit *= RV1126_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define RV1126_SCHMITT_PMU_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define RV1126_SCHMITT_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) int pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (RV1126_GPIO_C4_D7(pin_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) *reg = RV1126_SCHMITT_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *reg += ((pin_num / pins_per_reg) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) *bit = pin_num % pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define RK3308_SCHMITT_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define RK3308_SCHMITT_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) *reg = RK3308_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define RK1808_PULL_PMU_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define RK1808_PULL_GRF_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define RK1808_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define RK1808_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define RK1808_PULL_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) *reg = RK1808_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) *reg = RK1808_PULL_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) *reg += (bank->bank_num - 1) * RK1808_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) *bit = (pin_num % RK1808_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) *bit *= RK1808_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define RK1808_DRV_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define RK1808_DRV_GRF_OFFSET 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define RK1808_DRV_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define RK1808_DRV_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define RK1808_DRV_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) *reg = RK1808_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) *reg = RK1808_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) *reg += (bank->bank_num - 1) * RK1808_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) *bit = pin_num % RK1808_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) *bit *= RK1808_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define RK1808_SR_PMU_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define RK1808_SR_GRF_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define RK1808_SR_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define RK1808_SR_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static int rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) *reg = RK1808_SR_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) *reg = RK1808_SR_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) *reg += (bank->bank_num - 1) * RK1808_SR_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) *reg += ((pin_num / RK1808_SR_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) *bit = pin_num % RK1808_SR_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define RK1808_SCHMITT_PMU_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define RK1808_SCHMITT_GRF_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define RK1808_SCHMITT_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define RK1808_SCHMITT_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) *reg = RK1808_SCHMITT_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) *reg = RK1808_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define RK2928_PULL_OFFSET 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define RK2928_PULL_PINS_PER_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define RK2928_PULL_BANK_STRIDE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) *reg = RK2928_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) *bit = pin_num % RK2928_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define RK3128_PULL_OFFSET 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) *reg = RK3128_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) *bit = pin_num % RK2928_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define RK3188_PULL_OFFSET 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define RK3188_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define RK3188_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define RK3188_PULL_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define RK3188_PULL_PMU_OFFSET 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* The first 12 pins of the first bank are located elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (bank->bank_num == 0 && pin_num < 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) *regmap = info->regmap_pmu ? info->regmap_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) : bank->regmap_pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) *bit = pin_num % RK3188_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) *regmap = info->regmap_pull ? info->regmap_pull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) : info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* correct the offset, as it is the 2nd pull register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) *reg -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * The bits in these registers have an inverse ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * with the lowest pin being in bits 15:14 and the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) * pin in bits 1:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define RK3288_PULL_OFFSET 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) *reg = RK3188_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) *bit = pin_num % RK3188_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) *reg = RK3288_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define RK3288_DRV_PMU_OFFSET 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define RK3288_DRV_GRF_OFFSET 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define RK3288_DRV_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define RK3288_DRV_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define RK3288_DRV_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* The first 24 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) *reg = RK3288_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) *bit = pin_num % RK3288_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) *reg = RK3288_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define RK3228_PULL_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) *reg = RK3228_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define RK3228_DRV_GRF_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) *reg = RK3228_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define RK3308_PULL_OFFSET 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) *reg = RK3308_PULL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define RK3308_DRV_GRF_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) *reg = RK3308_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define RK3308_SLEW_RATE_GRF_OFFSET 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define RK3308_SLEW_RATE_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static int rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) int pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) *reg = RK3308_SLEW_RATE_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) *reg += (bank->bank_num) * RK3308_SLEW_RATE_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) *reg += ((pin_num / pins_per_reg) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) *bit = pin_num % pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define RK3368_PULL_GRF_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define RK3368_PULL_PMU_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* The first 32 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) *reg = RK3368_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) *bit = pin_num % RK3188_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) *reg = RK3368_PULL_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define RK3368_DRV_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define RK3368_DRV_GRF_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /* The first 32 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) *reg = RK3368_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) *bit = pin_num % RK3288_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) *reg = RK3368_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /* correct the offset, as we're starting with the 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) *reg -= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) *bit *= RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define RK3399_PULL_GRF_OFFSET 0xe040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #define RK3399_PULL_PMU_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #define RK3399_DRV_3BITS_PER_PIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /* The bank0:16 and bank1:32 pins are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) *reg = RK3399_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) *bit = pin_num % RK3188_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) *reg = RK3399_PULL_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* correct the offset, as we're starting with the 3rd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) *reg -= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) *bit *= RK3188_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) int drv_num = (pin_num / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* The bank0:16 and bank1:32 pins are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if ((bank->bank_num == 0) || (bank->bank_num == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) *reg = bank->drv[drv_num].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) *bit = (pin_num % 8) * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) *bit = (pin_num % 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define RK3568_SR_PMU_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define RK3568_SR_GRF_OFFSET 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define RK3568_SR_BANK_STRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define RK3568_SR_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define RK3568_SR_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static int rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) *reg = RK3568_SR_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) *reg = RK3568_SR_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) *reg += (bank->bank_num - 1) * RK3568_SR_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) *reg += ((pin_num / RK3568_SR_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) *bit = pin_num % RK3568_SR_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) *bit *= RK3568_SR_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define RK3568_PULL_PMU_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define RK3568_PULL_GRF_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #define RK3568_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define RK3568_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define RK3568_PULL_BANK_STRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) *reg = RK3568_PULL_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) *bit = pin_num % RK3568_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) *bit *= RK3568_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) *reg = RK3568_PULL_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) *bit *= RK3568_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) #define RK3568_DRV_PMU_OFFSET 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #define RK3568_DRV_GRF_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define RK3568_DRV_BITS_PER_PIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define RK3568_DRV_PINS_PER_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define RK3568_DRV_BANK_STRIDE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* The first 32 pins of the first bank are located in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) *reg = RK3568_DRV_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) *bit = pin_num % RK3568_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) *bit *= RK3568_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) *reg = RK3568_DRV_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) *bit *= RK3568_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (rockchip_get_cpu_version() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if ((bank->bank_num == 1 && (pin_num == 15 || pin_num == 23 || pin_num == 31)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ((bank->bank_num == 2 || bank->bank_num == 3 || bank->bank_num == 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) (pin_num == 7 || pin_num == 15 || pin_num == 23 || pin_num == 31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) *bit -= RK3568_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #define RK3588_PMU1_IOC_REG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #define RK3588_PMU2_IOC_REG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define RK3588_BUS_IOC_REG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define RK3588_VCCIO1_4_IOC_REG 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define RK3588_VCCIO3_5_IOC_REG 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #define RK3588_VCCIO2_IOC_REG 0xB000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #define RK3588_VCCIO6_IOC_REG 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define RK3588_EMMC_IOC_REG 0xD000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static const u32 rk3588_ds_regs[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) { RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) { RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) { RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) { RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) { RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) { RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) { RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) { RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) { RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) { RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) { RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) { RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) { RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) { RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) { RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) { RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) { RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) { RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const u32 rk3588_p_regs[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) { RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const u32 rk3588_smt_regs[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) { RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define RK3588_PULL_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define RK3588_PULL_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) u8 bank_num = bank->bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) u32 pin = bank_num * 32 + pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (pin >= rk3588_p_regs[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) *reg = rk3588_p_regs[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) BUG_ON(i == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) *reg += ((pin - rk3588_p_regs[i][0]) / RK3588_PULL_PINS_PER_REG) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) *bit = pin_num % RK3588_PULL_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) *bit *= RK3588_PULL_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define RK3588_DRV_BITS_PER_PIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define RK3588_DRV_PINS_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) int pin_num, struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) u8 bank_num = bank->bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) u32 pin = bank_num * 32 + pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) if (pin >= rk3588_ds_regs[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) *reg = rk3588_ds_regs[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) BUG_ON(i == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) *reg += ((pin - rk3588_ds_regs[i][0]) / RK3588_DRV_PINS_PER_REG) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) *bit = pin_num % RK3588_DRV_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) *bit *= RK3588_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) #define RK3588_SMT_BITS_PER_PIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define RK3588_SMT_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) u8 bank_num = bank->bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) u32 pin = bank_num * 32 + pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (pin >= rk3588_smt_regs[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) *reg = rk3588_smt_regs[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) BUG_ON(i == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) *reg += ((pin - rk3588_smt_regs[i][0]) / RK3588_SMT_PINS_PER_REG) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) *bit = pin_num % RK3588_SMT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) *bit *= RK3588_SMT_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) { 2, 4, 8, 12, -1, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) { 3, 6, 9, 12, -1, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { 5, 10, 15, 20, -1, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) { 4, 6, 8, 10, 12, 14, 16, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) { 4, 7, 10, 13, 16, 19, 22, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { 0, 2, 4, 6, 6, 8, 10, 12 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) int pin_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) u32 data, temp, rmask_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) int drv_type = bank->drv[pin_num / 8].drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) switch (drv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) case DRV_TYPE_IO_1V8_3V0_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) case DRV_TYPE_IO_3V3_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) rmask_bits = RK3399_DRV_3BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) switch (bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) case 0 ... 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) /* regular case, nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) * drive-strength offset is special, as it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * spread over 2 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) ret = regmap_read(regmap, reg + 0x4, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * the bit data[15] contains bit 0 of the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * while temp[1:0] contains bits 2 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) data >>= 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) temp &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) temp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) data |= temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return rockchip_perpin_drv_list[drv_type][data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) case 18 ... 21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /* setting fully enclosed in the second register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) reg += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) bit -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) bit, drv_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) case DRV_TYPE_IO_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case DRV_TYPE_IO_1V8_OR_3V0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) case DRV_TYPE_IO_1V8_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case DRV_TYPE_IO_SMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) rmask_bits = RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) data >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) data &= (1 << rmask_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) if (drv_type == DRV_TYPE_IO_SMIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) ret = regmap_read(regmap, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) tmp >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) tmp &= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) data |= tmp << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) return rockchip_perpin_drv_list[drv_type][data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) int pin_num, int strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) int reg, ret, i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) u32 data, rmask, rmask_bits, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) int drv_type = bank->drv[pin_num / 8].drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) bank->bank_num, pin_num, strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (ctrl->type == RV1126 || ctrl->type == RK3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) rmask_bits = RV1126_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) ret = strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) goto config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) } else if (ctrl->type == RV1106 || ctrl->type == RK3568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) rmask_bits = RK3568_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ret = (1 << (strength + 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) goto config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (rockchip_perpin_drv_list[drv_type][i] == strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ret = rockchip_perpin_drv_list[drv_type][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) dev_err(dev, "unsupported driver strength %d\n", strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) switch (drv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) case DRV_TYPE_IO_1V8_3V0_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) case DRV_TYPE_IO_3V3_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) rmask_bits = RK3399_DRV_3BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) switch (bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) case 0 ... 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* regular case, nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) * drive-strength offset is special, as it is spread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * over 2 registers, the bit data[15] contains bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) * of the value while temp[1:0] contains bits 2 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) data = (ret & 0x1) << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) temp = (ret >> 0x1) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) rmask = BIT(15) | BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) data |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) err = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) rmask = 0x3 | (0x3 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) temp |= (0x3 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) reg += 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) err = regmap_update_bits(regmap, reg, rmask, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) case 18 ... 21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* setting fully enclosed in the second register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) reg += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) bit -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) bit, drv_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) case DRV_TYPE_IO_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) case DRV_TYPE_IO_1V8_OR_3V0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) case DRV_TYPE_IO_1V8_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) case DRV_TYPE_IO_SMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) rmask_bits = RK3288_DRV_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) /* enable the write to the equivalent lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) data = ((1 << rmask_bits) - 1) << (bit + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) data |= (ret << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) err = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) if (ctrl->type == RK3568 && rockchip_get_cpu_version() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (bank->bank_num == 1 && pin_num == 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) reg = 0x0840;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) else if (bank->bank_num == 2 && pin_num == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) reg = 0x0844;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) else if (bank->bank_num == 2 && pin_num == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) reg = 0x0848;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) else if (bank->bank_num == 3 && pin_num == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) reg = 0x084c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) else if (bank->bank_num == 3 && pin_num == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) reg = 0x0850;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) else if (bank->bank_num == 4 && pin_num == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) reg = 0x0854;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) data = ((1 << rmask_bits) - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) data |= (1 << (strength + 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) err = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) if (drv_type == DRV_TYPE_IO_SMIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) data = BIT(bit + 16) | (((ret >> 2) & 0x1) << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) err = regmap_write(regmap, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) PIN_CONFIG_BIAS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) PIN_CONFIG_BIAS_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) PIN_CONFIG_BIAS_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) PIN_CONFIG_BIAS_BUS_HOLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) PIN_CONFIG_BIAS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) PIN_CONFIG_BIAS_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) PIN_CONFIG_BIAS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) PIN_CONFIG_BIAS_PULL_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) int reg, ret, pull_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) /* rk3066b does support any pulls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) if (ctrl->type == RK3066B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) switch (ctrl->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) case RK2928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) case RK3128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) return !(data & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) : PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) case PX30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) case RV1106:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) case RV1108:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) case RV1126:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) case RK1808:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) case RK3188:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) case RK3288:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) case RK3308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) case RK3368:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) case RK3399:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) case RK3568:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) case RK3588:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) pull_type = bank->pull_type[pin_num / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) data >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) return rockchip_pull_list[pull_type][data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) dev_err(dev, "unsupported pinctrl type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) static int rockchip_set_pull(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) int pin_num, int pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) int reg, ret, i, pull_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) u32 data, rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) /* rk3066b does support any pulls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) if (ctrl->type == RK3066B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) return pull ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) switch (ctrl->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) case RK2928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) case RK3128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) data = BIT(bit + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) if (pull == PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) data |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) ret = regmap_write(regmap, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) case PX30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) case RV1106:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) case RV1108:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) case RV1126:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) case RK1808:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) case RK3188:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) case RK3288:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) case RK3308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) case RK3368:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) case RK3399:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) case RK3568:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) case RK3588:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) pull_type = bank->pull_type[pin_num / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) if (rockchip_pull_list[pull_type][i] == pull) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) * where that pull up value becomes 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) ret = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) dev_err(dev, "unsupported pull setting %d\n", pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) /* enable the write to the equivalent lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) data |= (ret << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ret = regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) dev_err(dev, "unsupported pinctrl type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define RK3328_SCHMITT_BITS_PER_PIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) #define RK3328_SCHMITT_PINS_PER_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) #define RK3328_SCHMITT_BANK_STRIDE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define RK3328_SCHMITT_GRF_OFFSET 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) *reg = RK3328_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) #define RK3568_SCHMITT_BITS_PER_PIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define RK3568_SCHMITT_PINS_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) #define RK3568_SCHMITT_BANK_STRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) #define RK3568_SCHMITT_GRF_OFFSET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) *reg = RK3568_SCHMITT_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) *bit *= RK3568_SCHMITT_BITS_PER_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) data >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) switch (ctrl->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) case RK3568:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) return data & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) int pin_num, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) u32 data, rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) bank->bank_num, pin_num, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) /* enable the write to the equivalent lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) switch (ctrl->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) case RK3568:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) rmask = data | (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) data |= ((enable ? 0x2 : 0x1) << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) data = BIT(bit + 16) | (enable << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) rmask = BIT(bit + 16) | BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) return regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) #define PX30_SLEW_RATE_PMU_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) #define PX30_SLEW_RATE_GRF_OFFSET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) #define PX30_SLEW_RATE_BANK_STRIDE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) struct regmap **regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) int *reg, u8 *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) int pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (bank->bank_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) *regmap = info->regmap_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) *reg = PX30_SLEW_RATE_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) pins_per_reg = PX30_SLEW_RATE_PINS_PER_PMU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) *regmap = info->regmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) *reg = PX30_SLEW_RATE_GRF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) pins_per_reg = PX30_SLEW_RATE_PINS_PER_GRF_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) *reg += (bank->bank_num - 1) * PX30_SLEW_RATE_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) *reg += ((pin_num / pins_per_reg) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) *bit = pin_num % pins_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) int drv_type = bank->drv[pin_num / 8].drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) if (drv_type == DRV_TYPE_IO_SMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) ret = regmap_read(regmap, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) data >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) return data & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) int pin_num, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) struct rockchip_pinctrl *info = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) struct rockchip_pin_ctrl *ctrl = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) u32 data, rmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) int drv_type = bank->drv[pin_num / 8].drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (drv_type == DRV_TYPE_IO_SMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) bank->bank_num, pin_num, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* enable the write to the equivalent lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) data = BIT(bit + 16) | (speed << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) rmask = BIT(bit + 16) | BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) return regmap_update_bits(regmap, reg, rmask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * Pinmux_ops handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) return info->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) return info->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) unsigned selector, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) *groups = info->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) *num_groups = info->functions[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) const unsigned int *pins = info->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) const struct rockchip_pin_config *data = info->groups[group].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) struct rockchip_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) int cnt, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) dev_dbg(dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) info->functions[selector].name, info->groups[group].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) * for each pin in the pin group selected, program the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) * pin function number in the config register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) bank = pin_to_bank(info, pins[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) data[cnt].func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) if (ret && cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /* revert the already done pin settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) for (cnt--; cnt >= 0 && !data[cnt].func; cnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) static const struct pinmux_ops rockchip_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .get_functions_count = rockchip_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) .get_function_name = rockchip_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .get_function_groups = rockchip_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) .set_mux = rockchip_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) * Pinconf_ops handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) enum pin_config_param pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) switch (ctrl->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) case RK2928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) case RK3128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) pull == PIN_CONFIG_BIAS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) case RK3066B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) return pull ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) case PX30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) case RV1106:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) case RV1108:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) case RV1126:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) case RK1808:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) case RK3188:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) case RK3288:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) case RK3308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) case RK3368:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) case RK3399:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) case RK3568:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) case RK3588:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) unsigned int pin, u32 param, u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) struct rockchip_pin_deferred *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) cfg->pin = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) cfg->param = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) cfg->arg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) list_add_tail(&cfg->head, &bank->deferred_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* set the pin config settings for a specified pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) struct gpio_chip *gpio = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) * Check for gpio driver not being probed yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) * The lock makes sure that either gpio-probe has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) * or the gpio driver hasn't probed yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) mutex_lock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) if (!gpio || !gpio->direction_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) mutex_unlock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) mutex_unlock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) rc = rockchip_set_pull(bank, pin - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) if (!rockchip_pinconf_pull_valid(info->ctrl, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) rc = rockchip_set_pull(bank, pin - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) rc = rockchip_set_mux(bank, pin - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) RK_FUNC_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (rc != RK_FUNC_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) rc = gpio->direction_output(gpio, pin - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) rc = rockchip_set_mux(bank, pin - bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) RK_FUNC_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) if (rc != RK_FUNC_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) rc = gpio->direction_input(gpio, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /* rk3288 is the first with per-pin drive-strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (!info->ctrl->drv_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) rc = rockchip_set_drive_perpin(bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) pin - bank->pin_base, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) if (!info->ctrl->schmitt_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) rc = rockchip_set_schmitt(bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) pin - bank->pin_base, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) if (!info->ctrl->slew_rate_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) rc = rockchip_set_slew_rate(bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) pin - bank->pin_base, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) /* get the pin config settings for a specified pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) struct gpio_chip *gpio = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) u16 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) if (!rockchip_pinconf_pull_valid(info->ctrl, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) rc = rockchip_get_mux(bank, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) if (rc != RK_FUNC_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) if (!gpio || !gpio->get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) rc = gpio->get(gpio, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) arg = rc ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) /* rk3288 is the first with per-pin drive-strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (!info->ctrl->drv_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) arg = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (!info->ctrl->schmitt_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) arg = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) if (!info->ctrl->slew_rate_calc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) rc = rockchip_get_slew_rate(bank, pin - bank->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) arg = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) static const struct pinconf_ops rockchip_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) .pin_config_get = rockchip_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) .pin_config_set = rockchip_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static const struct of_device_id rockchip_bank_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) { .compatible = "rockchip,gpio-bank" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) { .compatible = "rockchip,rk3188-gpio-bank0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) if (of_match_node(rockchip_bank_match, child))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) info->nfunctions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) info->ngroups += of_get_child_count(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) static int rockchip_pinctrl_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) struct rockchip_pin_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) struct rockchip_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) dev_dbg(dev, "group(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) /* Initialise group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) * the binding format is rockchip,pins = <bank pin mux CONFIG>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) * do sanity check and calculate pins number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) list = of_get_property(np, "rockchip,pins", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /* we do not check return since it's safe node passed down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) size /= sizeof(*list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) if (!size || size % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) grp->npins = size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) if (!grp->pins || !grp->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) for (i = 0, j = 0; i < size; i += 4, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) const __be32 *phandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) struct device_node *np_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) num = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) bank = bank_num_to_bank(info, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) if (IS_ERR(bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) return PTR_ERR(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) grp->data[j].func = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) phandle = list++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (!phandle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) ret = pinconf_generic_parse_dt_config(np_config, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) &grp->data[j].configs, &grp->data[j].nconfigs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) static int rockchip_pinctrl_parse_functions(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) struct rockchip_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) struct device *dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) struct rockchip_pmx_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) struct rockchip_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) static u32 grp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) func = &info->functions[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /* Initialise function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) func->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) func->ngroups = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) if (func->ngroups <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) func->groups[i] = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) grp = &info->groups[grp_index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) struct rockchip_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) rockchip_pinctrl_child_count(info, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) dev_dbg(dev, "ngroups = %d\n", info->ngroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (!info->functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) if (!info->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) if (of_match_node(rockchip_bank_match, child))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) ret = rockchip_pinctrl_parse_functions(child, info, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) dev_err(dev, "failed to parse function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) static int rockchip_pinctrl_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) struct rockchip_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) struct pinctrl_desc *ctrldesc = &info->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) struct pinctrl_pin_desc *pindesc, *pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) struct rockchip_pin_bank *pin_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) int pin, bank, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) ctrldesc->name = "rockchip-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) ctrldesc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) ctrldesc->pctlops = &rockchip_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) ctrldesc->pmxops = &rockchip_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) ctrldesc->confops = &rockchip_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) if (!pindesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) ctrldesc->pins = pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) ctrldesc->npins = info->ctrl->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) pdesc = pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) pin_bank = &info->ctrl->pin_banks[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) pdesc->number = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) pin_bank->name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) pdesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) INIT_LIST_HEAD(&pin_bank->deferred_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) mutex_init(&pin_bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) ret = rockchip_pinctrl_parse_dt(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) if (IS_ERR(info->pctl_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) static const struct of_device_id rockchip_pinctrl_dt_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) static struct rockchip_pin_bank rk3308bs_pin_banks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) static struct rockchip_pin_bank px30s_pin_banks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) /* retrieve the soc specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) struct rockchip_pinctrl *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) struct rockchip_pin_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) struct rockchip_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) match = of_match_node(rockchip_pinctrl_dt_match, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) ctrl = (struct rockchip_pin_ctrl *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) ctrl->pin_banks = rk3308bs_pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) ctrl->pin_banks = px30s_pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) grf_offs = ctrl->grf_mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) pmu_offs = ctrl->pmu_mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) drv_pmu_offs = ctrl->pmu_drv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) drv_grf_offs = ctrl->grf_drv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) bank = ctrl->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) int bank_pins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) raw_spin_lock_init(&bank->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) bank->drvdata = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) bank->pin_base = ctrl->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) ctrl->nr_pins += bank->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* calculate iomux and drv offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) struct rockchip_iomux *iom = &bank->iomux[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) struct rockchip_drv *drv = &bank->drv[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) int inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) if (bank_pins >= bank->nr_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) /* preset iomux offset value, set new start value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (iom->offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) pmu_offs = iom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) grf_offs = iom->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) } else { /* set current iomux offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) (iom->type & IOMUX_L_SOURCE_PMU)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) pmu_offs : grf_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) /* preset drv offset value, set new start value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) if (drv->offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) if (iom->type & IOMUX_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) drv_pmu_offs = drv->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) drv_grf_offs = drv->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) } else { /* set current drv offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) drv_pmu_offs : drv_grf_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) i, j, iom->offset, drv->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) * Increase offset according to iomux width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) * 4bit iomux'es are spread over two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) inc = (iom->type & (IOMUX_WIDTH_4BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) IOMUX_WIDTH_3BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) IOMUX_WIDTH_2BIT)) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) pmu_offs += inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) grf_offs += inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) * Increase offset according to drv width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) * 3bit drive-strenth'es are spread over two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) inc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) inc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) if (iom->type & IOMUX_SOURCE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) drv_pmu_offs += inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) drv_grf_offs += inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) bank_pins += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) /* calculate the per-bank recalced_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) for (j = 0; j < ctrl->niomux_recalced; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) int pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) if (ctrl->iomux_recalced[j].num == bank->bank_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) pin = ctrl->iomux_recalced[j].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) bank->recalced_mask |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /* calculate the per-bank route_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) for (j = 0; j < ctrl->niomux_routes; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) int pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) pin = ctrl->iomux_routes[j].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) bank->route_mask |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) return ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) #define RK3288_GRF_GPIO6C_IOMUX 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) static u32 rk3288_grf_gpio6c_iomux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) struct rockchip_pinctrl *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) int ret = pinctrl_force_sleep(info->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) * the setting here, and restore it at resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) if (info->ctrl->type == RK3288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) &rk3288_grf_gpio6c_iomux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) pinctrl_force_default(info->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) struct rockchip_pinctrl *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) if (info->ctrl->type == RK3288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) rk3288_grf_gpio6c_iomux |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) GPIO6C6_SEL_WRITE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) return pinctrl_force_default(info->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) rockchip_pinctrl_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) /* SoC data specially handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) /* rk3308 SoC data initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) #define RK3308_GRF_SOC_CON13 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) #define RK3308_GRF_SOC_CON15 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) /* RK3308_GRF_SOC_CON13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) /* RK3308_GRF_SOC_CON15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) * Enable the special ctrl of selected sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) RK3308_GRF_I2C3_IOFUNC_SRC_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) RK3308_GRF_GPIO2A3_SEL_SRC_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) RK3308_GRF_GPIO2C0_SEL_SRC_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) RK3308_GRF_GPIO3B3_SEL_SRC_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) static int rockchip_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) struct rockchip_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) struct device_node *np = dev->of_node, *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) struct rockchip_pin_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (!dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) return dev_err_probe(dev, -EINVAL, "driver data not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) info->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) node = of_parse_phandle(np, "rockchip,grf", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) info->regmap_base = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) if (IS_ERR(info->regmap_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) return PTR_ERR(info->regmap_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) rockchip_regmap_config.max_register = resource_size(res) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) rockchip_regmap_config.name = "rockchip,pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) info->regmap_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) /* to check for the old dt-bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) info->reg_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) /* Honor the old binding, with pull registers as 2nd resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) if (ctrl->type == RK3188 && info->reg_size < 0x200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) rockchip_regmap_config.max_register = resource_size(res) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) rockchip_regmap_config.name = "rockchip,pinctrl-pull";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) info->regmap_pull =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) /* try to find the optional reference to the pmu syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) node = of_parse_phandle(np, "rockchip,pmu", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) info->regmap_pmu = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) if (IS_ERR(info->regmap_pmu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) return PTR_ERR(info->regmap_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) ret = rk3308_soc_data_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) ret = rockchip_pinctrl_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) g_pctldev = info->pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) return dev_err_probe(dev, ret, "failed to register gpio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) dev_info(dev, "probed %s\n", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) static int rockchip_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) struct rockchip_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) struct rockchip_pin_deferred *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) g_pctldev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) for (i = 0; i < info->ctrl->nr_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) bank = &info->ctrl->pin_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) mutex_lock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) while (!list_empty(&bank->deferred_pins)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) cfg = list_first_entry(&bank->deferred_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) struct rockchip_pin_deferred, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) list_del(&cfg->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) mutex_unlock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) static struct rockchip_pin_bank px30_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) IOMUX_SOURCE_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) IOMUX_WIDTH_4BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) IOMUX_WIDTH_4BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) IOMUX_WIDTH_4BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) .pin_banks = px30_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) .nr_banks = ARRAY_SIZE(px30_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) .label = "PX30-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) .type = PX30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) .iomux_routes = px30_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) .pull_calc_reg = px30_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) .drv_calc_reg = px30_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) static struct rockchip_pin_bank rv1106_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) 0, 0x08, 0x10, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) 0x10020, 0x10028, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) 0x20040, 0x20048, 0x20050, 0x20058),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) 0x30000, 0x30008, 0x30010, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) .pin_banks = rv1106_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) .label = "RV1106-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) .type = RV1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) static struct rockchip_pin_bank rv1108_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) IOMUX_SOURCE_PMU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) static struct rockchip_pin_ctrl rv1108_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) .pin_banks = rv1108_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) .label = "RV1108-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) .type = RV1108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) .grf_mux_offset = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) .iomux_recalced = rv1108_mux_recalced_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) static struct rockchip_pin_bank rv1126_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) 0x10010, 0x10018, 0x10020, 0x10028),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) IOMUX_WIDTH_4BIT, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) static struct rockchip_pin_ctrl rv1126_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) .pin_banks = rv1126_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) .label = "RV1126-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) .type = RV1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) .iomux_routes = rv1126_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) .iomux_recalced = rv1126_mux_recalced_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) static struct rockchip_pin_bank rk1808_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) IOMUX_SOURCE_PMU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) static struct rockchip_pin_ctrl rk1808_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) .pin_banks = rk1808_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) .nr_banks = ARRAY_SIZE(rk1808_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) .label = "RK1808-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) .type = RK1808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) .iomux_routes = rk1808_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) .pull_calc_reg = rk1808_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) .drv_calc_reg = rk1808_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) .slew_rate_calc_reg = rk1808_calc_slew_rate_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) static struct rockchip_pin_bank rk2928_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) static struct rockchip_pin_ctrl rk2928_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) .pin_banks = rk2928_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) .label = "RK2928-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) .type = RK2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) .grf_mux_offset = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) static struct rockchip_pin_bank rk3036_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) static struct rockchip_pin_ctrl rk3036_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) .pin_banks = rk3036_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) .label = "RK3036-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) .type = RK2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) .grf_mux_offset = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) static struct rockchip_pin_bank rk3066a_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) PIN_BANK(4, 32, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) PIN_BANK(6, 16, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) static struct rockchip_pin_ctrl rk3066a_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) .pin_banks = rk3066a_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) .label = "RK3066a-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) .type = RK2928,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) .grf_mux_offset = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) static struct rockchip_pin_bank rk3066b_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) static struct rockchip_pin_ctrl rk3066b_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) .pin_banks = rk3066b_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) .label = "RK3066b-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) .type = RK3066B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) .grf_mux_offset = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) static struct rockchip_pin_bank rk3128_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) static struct rockchip_pin_ctrl rk3128_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) .pin_banks = rk3128_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) .label = "RK3128-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) .type = RK3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) .grf_mux_offset = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) .iomux_recalced = rk3128_mux_recalced_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) .iomux_routes = rk3128_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) static struct rockchip_pin_bank rk3188_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) static struct rockchip_pin_ctrl rk3188_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) .pin_banks = rk3188_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) .label = "RK3188-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) .type = RK3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) .grf_mux_offset = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) .iomux_routes = rk3188_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) static struct rockchip_pin_bank rk3228_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) PIN_BANK(0, 32, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) static struct rockchip_pin_ctrl rk3228_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) .pin_banks = rk3228_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) .label = "RK3228-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) .type = RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) .iomux_routes = rk3228_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) static struct rockchip_pin_bank rk3288_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) IOMUX_UNROUTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) IOMUX_UNROUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) IOMUX_UNROUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) IOMUX_UNROUTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) IOMUX_UNROUTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) PIN_BANK(8, 16, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static struct rockchip_pin_ctrl rk3288_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) .pin_banks = rk3288_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) .label = "RK3288-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) .type = RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) .pmu_mux_offset = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) .iomux_routes = rk3288_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) static struct rockchip_pin_bank rk3308bs_pin_banks[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) S_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) static struct rockchip_pin_bank rk3308_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) IOMUX_WIDTH_2BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) IOMUX_WIDTH_2BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) IOMUX_WIDTH_2BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) IOMUX_WIDTH_2BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) IOMUX_WIDTH_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) IOMUX_WIDTH_2BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) static struct rockchip_pin_ctrl rk3308_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) .pin_banks = rk3308_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) .label = "RK3308-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) .type = RK3308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) .iomux_recalced = rk3308_mux_recalced_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) .iomux_routes = rk3308_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) .slew_rate_calc_reg = rk3308_calc_slew_rate_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) static struct rockchip_pin_bank rk3328_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) IOMUX_WIDTH_3BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) IOMUX_WIDTH_3BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) IOMUX_WIDTH_3BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) IOMUX_WIDTH_3BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) static struct rockchip_pin_ctrl rk3328_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) .pin_banks = rk3328_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) .label = "RK3328-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) .type = RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) .iomux_recalced = rk3328_mux_recalced_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) .iomux_routes = rk3328_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) static struct rockchip_pin_bank rk3368_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) IOMUX_SOURCE_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) PIN_BANK(1, 32, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) PIN_BANK(2, 32, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) PIN_BANK(3, 32, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) static struct rockchip_pin_ctrl rk3368_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) .pin_banks = rk3368_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) .label = "RK3368-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) .type = RK3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) static struct rockchip_pin_bank rk3399_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) DRV_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) DRV_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) DRV_TYPE_IO_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) DRV_TYPE_IO_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) PULL_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) PULL_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) PULL_TYPE_IO_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) PULL_TYPE_IO_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) IOMUX_SOURCE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) DRV_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) DRV_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) PULL_TYPE_IO_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) PULL_TYPE_IO_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) PULL_TYPE_IO_1V8_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) PULL_TYPE_IO_1V8_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) DRV_TYPE_IO_3V3_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) DRV_TYPE_IO_3V3_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) DRV_TYPE_IO_1V8_OR_3V0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) DRV_TYPE_IO_1V8_3V0_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) DRV_TYPE_IO_1V8_OR_3V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) DRV_TYPE_IO_1V8_OR_3V0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) static struct rockchip_pin_ctrl rk3399_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) .pin_banks = rk3399_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) .label = "RK3399-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) .type = RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) .grf_mux_offset = 0xe000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) .grf_drv_offset = 0xe100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) .pmu_drv_offset = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) .iomux_routes = rk3399_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) static struct rockchip_pin_bank rk3568_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) IOMUX_WIDTH_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) IOMUX_WIDTH_4BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) static struct rockchip_pin_ctrl rk3568_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) .pin_banks = rk3568_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) .label = "RK3568-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) .type = RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) .grf_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) .pmu_mux_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) .grf_drv_offset = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) .pmu_drv_offset = 0x0070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) .iomux_routes = rk3568_mux_route_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) .slew_rate_calc_reg = rk3568_calc_slew_rate_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) static struct rockchip_pin_bank rk3588_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) static struct rockchip_pin_ctrl rk3588_pin_ctrl __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) .pin_banks = rk3588_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) .label = "RK3588-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) .type = RK3588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) static const struct of_device_id rockchip_pinctrl_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) { .compatible = "rockchip,px30-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) .data = &px30_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) #ifdef CONFIG_CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) { .compatible = "rockchip,rv1106-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) .data = &rv1106_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) #ifdef CONFIG_CPU_RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) { .compatible = "rockchip,rv1108-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) .data = &rv1108_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) { .compatible = "rockchip,rv1126-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) .data = &rv1126_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) #ifdef CONFIG_CPU_RK1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) { .compatible = "rockchip,rk1808-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) .data = &rk1808_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) #ifdef CONFIG_CPU_RK2928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) { .compatible = "rockchip,rk2928-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) .data = &rk2928_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) #ifdef CONFIG_CPU_RK3036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) { .compatible = "rockchip,rk3036-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) .data = &rk3036_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) #ifdef CONFIG_CPU_RK30XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) { .compatible = "rockchip,rk3066a-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) .data = &rk3066a_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) { .compatible = "rockchip,rk3066b-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) .data = &rk3066b_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) #ifdef CONFIG_CPU_RK312X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) { .compatible = "rockchip,rk3128-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) .data = (void *)&rk3128_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) #ifdef CONFIG_CPU_RK3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) { .compatible = "rockchip,rk3188-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) .data = &rk3188_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) #ifdef CONFIG_CPU_RK322X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) { .compatible = "rockchip,rk3228-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) .data = &rk3228_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) #ifdef CONFIG_CPU_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) { .compatible = "rockchip,rk3288-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) .data = &rk3288_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) { .compatible = "rockchip,rk3308-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) .data = &rk3308_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) #ifdef CONFIG_CPU_RK3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) { .compatible = "rockchip,rk3328-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) .data = &rk3328_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) #ifdef CONFIG_CPU_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) { .compatible = "rockchip,rk3368-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) .data = &rk3368_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) #ifdef CONFIG_CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) { .compatible = "rockchip,rk3399-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) .data = &rk3399_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) #ifdef CONFIG_CPU_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) { .compatible = "rockchip,rk3568-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) .data = &rk3568_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) #ifdef CONFIG_CPU_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) { .compatible = "rockchip,rk3588-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) .data = &rk3588_pin_ctrl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) static struct platform_driver rockchip_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) .probe = rockchip_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) .remove = rockchip_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) .name = "rockchip-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) .pm = &rockchip_pinctrl_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) .of_match_table = rockchip_pinctrl_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) static int __init rockchip_pinctrl_drv_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) return platform_driver_register(&rockchip_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) postcore_initcall(rockchip_pinctrl_drv_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) static void __exit rockchip_pinctrl_drv_unregister(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) platform_driver_unregister(&rockchip_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) module_exit(rockchip_pinctrl_drv_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) * rk_iomux_set - set the rockchip iomux by pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) * @bank: the gpio bank index, from 0 to the max bank num.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) * @pin: the gpio pin index, from 0 to 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) * @mux: the pointer to store mux value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) * Return 0 if set success, else return error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) int rk_iomux_set(int bank, int pin, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) struct pinctrl_dev *pctldev = g_pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) struct rockchip_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) struct rockchip_pin_bank *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) struct rockchip_pin_group *grp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) struct rockchip_pin_config *cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) if (!g_pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if (bank >= info->ctrl->nr_banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) if (pin > 31 || pin < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) gpio = &info->ctrl->pin_banks[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) mutex_lock(&iomux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) for (i = 0; i < info->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) grp = &info->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) for (j = 0; j < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) if (grp->pins[i] == (gpio->pin_base + pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) cfg = grp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) ret = rockchip_set_mux(gpio, pin, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) dev_err(info->dev, "mux GPIO%d-%d %d fail\n", bank, pin, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) if (cfg && (cfg->func != mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) cfg->func = mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) mutex_unlock(&iomux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) EXPORT_SYMBOL_GPL(rk_iomux_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) * rk_iomux_get - get the rockchip iomux by pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) * @bank: the gpio bank index, from 0 to the max bank num.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) * @pin: the gpio pin index, from 0 to 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) * @mux: the pointer to store mux value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) * Return 0 if get success, else return error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) int rk_iomux_get(int bank, int pin, int *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) struct pinctrl_dev *pctldev = g_pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) struct rockchip_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) struct rockchip_pin_bank *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) if (!g_pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) if (bank >= info->ctrl->nr_banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) if (pin > 31 || pin < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) gpio = &info->ctrl->pin_banks[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) mutex_lock(&iomux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) ret = rockchip_get_mux(gpio, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) mutex_unlock(&iomux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) *mux = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) return (ret >= 0) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) EXPORT_SYMBOL_GPL(rk_iomux_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) MODULE_ALIAS("platform:pinctrl-rockchip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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