^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl driver for Rockchip RK806 PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xu Shengfei <xsf@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/rk806.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct rk806_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const char *const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct rk806_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const unsigned int pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @reg: gpio setting register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @fun_mask: functions select mask value, when set is gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @dir_mask: input or output mask value, when set is output, otherwise input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @val_mask: gpio set value, when set is level high, otherwise low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Different PMIC has different pin features, belowing 3 mask members are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * all necessary for every PMIC. For example, RK805 has 2 pins that can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * as output only GPIOs, so func_mask and dir_mask are not needed. RK816 has 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct rk806_pin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 fun_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 fun_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 dir_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 val_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct rk806_pctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct rk806 *rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pinctrl_desc pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct rk806_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct rk806_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct rk806_pin_config *pin_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RK806_PWRCTRL1_DR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK806_PWRCTRL2_DR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK806_PWRCTRL3_DR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK806_PWRCTRL1_DATA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK806_PWRCTRL2_DATA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK806_PWRCTRL3_DATA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK806_PWRCTRL1_FUN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RK806_PWRCTRL2_FUN 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK806_PWRCTRL3_FUN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum rk806_pinmux_option {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK806_PINMUX_FUN0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK806_PINMUX_FUN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK806_PINMUX_FUN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK806_PINMUX_FUN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK806_PINMUX_FUN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK806_PINMUX_FUN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK806_GPIO_DVS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK806_GPIO_DVS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RK806_GPIO_DVS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char *const rk806_gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "gpio_pwrctrl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "gpio_pwrctrl2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "gpio_pwrctrl3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct pinctrl_pin_desc rk806_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), /* dvs1 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), /* dvs2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3") /* dvs3 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct rk806_pin_function rk806_pin_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "pin_fun0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .mux_option = RK806_PINMUX_FUN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "pin_fun1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mux_option = RK806_PINMUX_FUN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "pin_fun2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mux_option = RK806_PINMUX_FUN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "pin_fun3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .mux_option = RK806_PINMUX_FUN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "pin_fun4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .mux_option = RK806_PINMUX_FUN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "pin_fun5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .groups = rk806_gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .ngroups = ARRAY_SIZE(rk806_gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .mux_option = RK806_PINMUX_FUN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct rk806_pin_group rk806_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "gpio_pwrctrl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pins = { RK806_GPIO_DVS1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .npins = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "gpio_pwrctrl2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .pins = { RK806_GPIO_DVS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .npins = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "gpio_pwrctrl3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pins = { RK806_GPIO_DVS3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .npins = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct rk806_pin_config rk806_gpio_cfgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .fun_reg = RK806_SLEEP_CONFIG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .fun_msk = RK806_PWRCTRL1_FUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .reg = RK806_SLEEP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .val_msk = RK806_PWRCTRL1_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .dir_msk = RK806_PWRCTRL1_DR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .fun_reg = RK806_SLEEP_CONFIG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .fun_msk = RK806_PWRCTRL2_FUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg = RK806_SLEEP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .val_msk = RK806_PWRCTRL2_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .dir_msk = RK806_PWRCTRL2_DR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .fun_reg = RK806_SLEEP_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .fun_msk = RK806_PWRCTRL3_FUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg = RK806_SLEEP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .val_msk = RK806_PWRCTRL3_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .dir_msk = RK806_PWRCTRL3_DR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* generic gpio chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int rk806_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct rk806_pctrl_info *pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!pci->pin_cfg[offset].val_msk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(pci->dev, "getting gpio%d value is not support\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = regmap_read(pci->rk806->regmap, pci->pin_cfg[offset].reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(pci->dev, "get gpio%d value failed\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return !!(val & pci->pin_cfg[offset].val_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void rk806_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct rk806_pctrl_info *pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!pci->pin_cfg[offset].val_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regmap_update_bits(pci->rk806->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci->pin_cfg[offset].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pci->pin_cfg[offset].val_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) value ? pci->pin_cfg[offset].val_msk : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(pci->dev, "set gpio%d value %d failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int rk806_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int rk806_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rk806_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int rk806_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct rk806_pctrl_info *pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* default output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!pci->pin_cfg[offset].dir_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = regmap_read(pci->rk806->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pci->pin_cfg[offset].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(pci->dev, "get gpio%d direction failed\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return !(val & pci->pin_cfg[offset].dir_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct gpio_chip rk806_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .label = "rk806-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .get_direction = rk806_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .get = rk806_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .set = rk806_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .direction_input = rk806_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .direction_output = rk806_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* generic pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int rk806_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return pci->num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char *rk806_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return pci->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int rk806_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *pins = pci->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *num_pins = pci->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct pinctrl_ops rk806_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .get_groups_count = rk806_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .get_group_name = rk806_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .get_group_pins = rk806_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int rk806_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return pci->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const char *rk806_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return pci->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int rk806_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int *const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *groups = pci->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *num_groups = pci->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int _rk806_pinctrl_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!pci->pin_cfg[offset].fun_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = regmap_update_bits(pci->rk806->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pci->pin_cfg[offset].fun_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pci->pin_cfg[offset].fun_msk, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int rk806_pinctrl_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int mux = pci->functions[function].mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int offset = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return _rk806_pinctrl_set_mux(pctldev, offset, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int rk806_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* set direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!pci->pin_cfg[offset].dir_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = regmap_update_bits(pci->rk806->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pci->pin_cfg[offset].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pci->pin_cfg[offset].dir_msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) input ? 0 : pci->pin_cfg[offset].dir_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(pci->dev, "set gpio%d direction failed\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int rk806_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return _rk806_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct pinmux_ops rk806_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .gpio_request_enable = rk806_pinctrl_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .get_functions_count = rk806_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .get_function_name = rk806_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .get_function_groups = rk806_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .set_mux = rk806_pinctrl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .gpio_set_direction = rk806_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int rk806_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) arg = rk806_gpio_get(&pci->gpio_chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int rk806_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct rk806_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 i, arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rk806_pmx_gpio_set_direction(pctldev, NULL, pin, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rk806_gpio_set(&pci->gpio_chip, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rk806_pmx_gpio_set_direction(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct pinconf_ops rk806_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .pin_config_get = rk806_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .pin_config_set = rk806_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct pinctrl_desc rk806_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .name = "rk806-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .pctlops = &rk806_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .pmxops = &rk806_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .confops = &rk806_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int rk806_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct rk806_pctrl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) np = of_get_child_by_name(pdev->dev.parent->of_node, "pinctrl_rk806");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci->dev->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pci->dev->of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pci->rk806 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) platform_set_drvdata(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pci->pinctrl_desc = rk806_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pci->gpio_chip = rk806_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pci->pins = rk806_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci->functions = rk806_pin_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pci->groups = rk806_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pci->pinctrl_desc.pins = rk806_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pci->pin_cfg = rk806_gpio_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pci->gpio_chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pci->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pci->gpio_chip.of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Add gpiochip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = devm_gpiochip_add_data(&pdev->dev, &pci->gpio_chip, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(&pdev->dev, "Couldn't add gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Add pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (IS_ERR(pci->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(&pdev->dev, "Couldn't add pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return PTR_ERR(pci->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Add pin range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = gpiochip_add_pin_range(&pci->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pci->gpio_chip.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(&pdev->dev, "Couldn't add gpiochip pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct platform_driver rk806_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .probe = rk806_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "rk806-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int __init rk806_pinctrl_driver_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return platform_driver_register(&rk806_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) subsys_initcall(rk806_pinctrl_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fs_initcall_sync(rk806_pinctrl_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MODULE_DESCRIPTION("RK806 pin control and GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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