^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl driver for Rockchip RK628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Weixin Zhou <zwx@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on the pinctrl-rk805/pinctrl-rockchip driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mfd/rk628.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPIO0_BASE 0xD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPIO1_BASE 0xE0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO2_BASE 0xF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPIO3_BASE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPIO_MAX_REGISTER (GPIO3_BASE + GPIO_VER_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* GPIO control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_SWPORT_DR_L 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_SWPORT_DR_H 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_SWPORT_DDR_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_SWPORT_DDR_H 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_INTEN_L 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_INTEN_H 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_INTMASK_L 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_INTMASK_H 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPIO_INTTYPE_L 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPIO_INTTYPE_H 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIO_INT_POLARITY_L 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIO_INT_POLARITY_H 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO_INT_BOTHEDGE_L 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO_INT_BOTHEDGE_H 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO_DEBOUNCE_L 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO_DEBOUNCE_H 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_DBCLK_DIV_EN_L 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_DBCLK_DIV_EN_H 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_INT_STATUS 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_INT_RAWSTATUS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO_PORTS_EOI_L 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_PORTS_EOI_H 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_EXT_PORT 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_VER_ID 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPIO_REG_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPIO_REG_HIGH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* GPIO control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO_INTMASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPIO_PORTS_EOI 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BANK_OFFSET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IRQ_CHIP(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [IRQCHIP_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = "rk628-"#fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .irq_bus_lock = rk628_irq_lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .irq_bus_sync_unlock = rk628_irq_sync_unlock,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .irq_disable = rk628_irq_disable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .irq_enable = rk628_irq_enable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_set_type = rk628_irq_set_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct rk628_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct rk628_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const unsigned int pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int iomux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct rk628_pin_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pinctrl_gpio_range grange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct rk628_pctrl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int mask_regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int polarity_regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int level_regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int bothedge_regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rk628_pctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl_desc pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct rk628_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct rk628_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regmap *grf_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct rk628_pin_bank *pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum rk628_pinmux_option {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINMUX_FUNC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINMUX_FUNC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PINCTRL_GROUP(a, b, c, d) { .name = a, .pins = b, .npins = c, .iomux_base = d}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PINCTRL_BANK(a, b, c) { .name = a, .reg_base = b, .nr_pins = c}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum rk628_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char *gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "gpio0a0", "gpio0a1", "gpio0a2", "gpio0a3", "gpio0a4", "gpio0a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "gpio0a6", "gpio0a7", "gpio0b0", "gpio0b1", "gpio0b2", "gpio0b3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "gpio1a0", "gpio1a1", "gpio1a2", "gpio1a3", "gpio1a4", "gpio1a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "gpio1a6", "gpio1a7", "gpio1b0", "gpio1b1", "gpio1b2", "gpio1b3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "gpio1b4", "gpio1b5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "gpio2a0", "gpio2a1", "gpio2a2", "gpio2a3", "gpio2a4", "gpio2a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "gpio2a6", "gpio2a7", "gpio2b0", "gpio2b1", "gpio2b2", "gpio2b3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "gpio2b4", "gpio2b5", "gpio2b6", "gpio2b7", "gpio2c0", "gpio2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "gpio2c3", "gpio2c4", "gpio2c5", "gpio2c6", "gpio2c7", "gpio1a0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "gpio3a1", "gpio3a2", "gpio3a3", "gpio3a4", "gpio3a5", "gpio3a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "gpio3a7", "gpio3b0", "gpio3b1", "gpio3b2", "gpio3b3", "gpio3b4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct rk628_pin_function rk628_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .groups = gpio_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ngroups = ARRAY_SIZE(gpio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GPIO_HIGH_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GPIO_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) GPIO_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GPIO0_A0 = BANK_OFFSET * 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GPIO0_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GPIO0_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GPIO0_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GPIO0_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GPIO0_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GPIO0_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GPIO0_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GPIO0_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GPIO0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GPIO0_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GPIO0_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GPIO1_A0 = BANK_OFFSET * 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GPIO1_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GPIO1_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GPIO1_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GPIO1_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GPIO1_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GPIO1_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GPIO1_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GPIO1_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GPIO1_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GPIO1_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) GPIO1_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GPIO1_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GPIO1_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GPIO2_A0 = BANK_OFFSET * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GPIO2_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GPIO2_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GPIO2_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) GPIO2_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GPIO2_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GPIO2_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GPIO2_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) GPIO2_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) GPIO2_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GPIO2_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GPIO2_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GPIO2_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GPIO2_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) GPIO2_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GPIO2_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GPIO2_C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) GPIO2_C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GPIO2_C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GPIO2_C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GPIO2_C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) GPIO2_C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) GPIO2_C6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GPIO2_C7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GPIO3_A0 = BANK_OFFSET * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GPIO3_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GPIO3_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GPIO3_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GPIO3_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GPIO3_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GPIO3_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GPIO3_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GPIO3_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GPIO3_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GPIO3_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GPIO3_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GPIO3_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) I2SM_SCK = BANK_OFFSET * 4 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) I2SM_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) I2SM_LR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) RXDDC_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RXDDC_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) HDMIRX_CE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct pinctrl_pin_desc rk628_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(GPIO0_A0, "gpio0a0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(GPIO0_A1, "gpio0a1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(GPIO0_A2, "gpio0a2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(GPIO0_A3, "gpio0a3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(GPIO0_A4, "gpio0a4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(GPIO0_A5, "gpio0a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(GPIO0_A6, "gpio0a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(GPIO0_A7, "gpio0a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(GPIO0_B0, "gpio0b0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(GPIO0_B1, "gpio0b1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(GPIO0_B2, "gpio0b2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(GPIO0_B3, "gpio0b3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(GPIO1_A0, "gpio1a0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(GPIO1_A1, "gpio1a1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(GPIO1_A2, "gpio1a2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(GPIO1_A3, "gpio1a3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(GPIO1_A4, "gpio1a4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(GPIO1_A5, "gpio1a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(GPIO1_A6, "gpio1a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(GPIO1_A7, "gpio1a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(GPIO1_B0, "gpio1b0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(GPIO1_B1, "gpio1b1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(GPIO1_B2, "gpio1b2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(GPIO1_B3, "gpio1b3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(GPIO1_B4, "gpio1b4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(GPIO1_B5, "gpio1b5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(GPIO2_A0, "gpio2a0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(GPIO2_A1, "gpio2a1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(GPIO2_A2, "gpio2a2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(GPIO2_A3, "gpio2a3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(GPIO2_A4, "gpio2a4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(GPIO2_A5, "gpio2a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(GPIO2_A6, "gpio2a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(GPIO2_A7, "gpio2a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(GPIO2_B0, "gpio2b0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(GPIO2_B1, "gpio2b1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(GPIO2_B2, "gpio2b2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(GPIO2_B3, "gpio2b3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(GPIO2_B4, "gpio2b4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(GPIO2_B5, "gpio2b5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(GPIO2_B6, "gpio2b6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(GPIO2_B7, "gpio2b7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(GPIO2_C0, "gpio2c0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(GPIO2_C1, "gpio2c1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(GPIO2_C2, "gpio2c2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(GPIO2_C3, "gpio2c3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(GPIO2_C4, "gpio2c4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(GPIO2_C5, "gpio2c5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(GPIO2_C6, "gpio2c6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(GPIO2_C7, "gpio2c7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(GPIO3_A0, "gpio3a0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(GPIO3_A1, "gpio3a1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(GPIO3_A2, "gpio3a2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(GPIO3_A3, "gpio3a3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(GPIO3_A4, "gpio3a4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(GPIO3_A5, "gpio3a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(GPIO3_A6, "gpio3a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(GPIO3_A7, "gpio3a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(GPIO3_B0, "gpio3b0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(GPIO3_B1, "gpio3b1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(GPIO3_B2, "gpio3b2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(GPIO3_B3, "gpio3b3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(GPIO3_B4, "gpio3b4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(I2SM_SCK, "i2sm_sck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(I2SM_D, "i2sm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(I2SM_LR, "i2sm_lr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(RXDDC_SCL, "rxddc_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(RXDDC_SDA, "rxddc_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(HDMIRX_CE, "hdmirx_cec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct rk628_pin_group rk628_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_GROUP("gpio0a0", { GPIO0_A0 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_GROUP("gpio0a1", { GPIO0_A1 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_GROUP("gpio0a2", { GPIO0_A2 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_GROUP("gpio0a3", { GPIO0_A3 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_GROUP("gpio0a4", { GPIO0_A4 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_GROUP("gpio0a5", { GPIO0_A5 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_GROUP("gpio0a6", { GPIO0_A6 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_GROUP("gpio0a7", { GPIO0_A7 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_GROUP("gpio0b0", { GPIO0_B0 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_GROUP("gpio0b1", { GPIO0_B1 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_GROUP("gpio0b2", { GPIO0_B2 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_GROUP("gpio0b3", { GPIO0_B3 }, 1, GRF_GPIO0AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_GROUP("gpio1a0", { GPIO1_A0 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_GROUP("gpio1a1", { GPIO1_A1 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_GROUP("gpio1a2", { GPIO1_A2 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_GROUP("gpio1a3", { GPIO1_A3 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_GROUP("gpio1a4", { GPIO1_A4 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_GROUP("gpio1a5", { GPIO1_A5 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_GROUP("gpio1a6", { GPIO1_A6 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_GROUP("gpio1a7", { GPIO1_A7 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_GROUP("gpio1b0", { GPIO1_B0 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_GROUP("gpio1b1", { GPIO1_B1 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_GROUP("gpio1b2", { GPIO1_B2 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_GROUP("gpio1b3", { GPIO1_B3 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_GROUP("gpio1b4", { GPIO1_B4 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_GROUP("gpio1b5", { GPIO1_B5 }, 1, GRF_GPIO1AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_GROUP("gpio2a0", { GPIO2_A0 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_GROUP("gpio2a1", { GPIO2_A1 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_GROUP("gpio2a2", { GPIO2_A2 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_GROUP("gpio2a3", { GPIO2_A3 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_GROUP("gpio2a4", { GPIO2_A4 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_GROUP("gpio2a5", { GPIO2_A5 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_GROUP("gpio2a6", { GPIO2_A6 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_GROUP("gpio2a7", { GPIO2_A7 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_GROUP("gpio2b0", { GPIO2_B0 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_GROUP("gpio2b1", { GPIO2_B1 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_GROUP("gpio2b2", { GPIO2_B2 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_GROUP("gpio2b3", { GPIO2_B3 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_GROUP("gpio2b4", { GPIO2_B4 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_GROUP("gpio2b5", { GPIO2_B5 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_GROUP("gpio2b6", { GPIO2_B6 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_GROUP("gpio2b7", { GPIO2_B7 }, 1, GRF_GPIO2AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_GROUP("gpio2c0", { GPIO2_C0 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_GROUP("gpio2c1", { GPIO2_C1 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_GROUP("gpio2c2", { GPIO2_C2 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_GROUP("gpio2c3", { GPIO2_C3 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_GROUP("gpio2c4", { GPIO2_C4 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_GROUP("gpio2c5", { GPIO2_C5 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_GROUP("gpio2c6", { GPIO2_C6 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_GROUP("gpio2c7", { GPIO2_C7 }, 1, GRF_GPIO2C_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_GROUP("gpio3a0", { GPIO3_A0 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_GROUP("gpio3a1", { GPIO3_A1 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_GROUP("gpio3a2", { GPIO3_A2 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_GROUP("gpio3a3", { GPIO3_A3 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_GROUP("gpio3a4", { GPIO3_A4 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_GROUP("gpio3a5", { GPIO3_A5 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_GROUP("gpio3a6", { GPIO3_A6 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_GROUP("gpio3a7", { GPIO3_A7 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_GROUP("gpio3b0", { GPIO3_B0 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_GROUP("gpio3b1", { GPIO3_B1 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_GROUP("gpio3b2", { GPIO3_B2 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_GROUP("gpio3b3", { GPIO3_B3 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_GROUP("gpio3b4", { GPIO3_B4 }, 1, GRF_GPIO3AB_SEL_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_GROUP("i2sm_sck", { I2SM_SCK }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_GROUP("i2sm_d", { I2SM_D }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_GROUP("i2sm_lr", { I2SM_LR }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_GROUP("rxddc_scl", { RXDDC_SCL }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_GROUP("rxddc_sda", { RXDDC_SDA }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_GROUP("hdmirx_cec", { HDMIRX_CE }, 1, GRF_SYSTEM_CON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct rk628_pin_bank rk628_pin_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_BANK("rk628-gpio0", GPIO0_BASE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_BANK("rk628-gpio1", GPIO1_BASE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_BANK("rk628-gpio2", GPIO2_BASE, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_BANK("rk628-gpio3", GPIO3_BASE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* generic gpio chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int rk628_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct rk628_pin_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int data_reg, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data_reg = bank->reg_base + GPIO_EXT_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = regmap_read(pci->regmap, data_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val >>= offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(pci->dev, "%s bank->name=%s dir_reg=0x%x offset=%x value=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __func__, bank->name, data_reg, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void rk628_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct rk628_pin_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int data_reg, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (offset / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) data_reg = bank->reg_base + GPIO_SWPORT_DR_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data_reg = bank->reg_base + GPIO_SWPORT_DR_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val = BIT(offset + 16) | BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val = BIT(offset + 16) | (0xffff & ~BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = regmap_write(pci->regmap, data_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pr_err("%s: regmap write failed! bank->name=%s data_reg=0x%x offset=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __func__, bank->name, data_reg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int rk628_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int rk628_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rk628_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int rk628_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct rk628_pin_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int dir_reg, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (offset / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = regmap_read(pci->regmap, dir_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val = BIT(offset) & val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int rk628_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct rk628_pin_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!bank->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) virq = irq_create_mapping(bank->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_err("map interruptr fail, bank->irq=%d\n", bank->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return (virq) ? : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct gpio_chip rk628_gpiolib_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .label = "rk628-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .get_direction = rk628_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .get = rk628_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .set = rk628_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .direction_input = rk628_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .direction_output = rk628_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .to_irq = rk628_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* generic pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int rk628_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return pci->num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const char *rk628_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return pci->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int rk628_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *pins = pci->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *num_pins = pci->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const struct pinctrl_ops rk628_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .get_groups_count = rk628_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .get_group_name = rk628_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .get_group_pins = rk628_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int rk628_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return pci->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const char *rk628_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return pci->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int rk628_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int *const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *groups = pci->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *num_groups = pci->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int rk628_calc_mux_offset(struct rk628_pctrl_info *pci, int mux, int reg, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int val = 0, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case GRF_SYSTEM_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) regmap_read(pci->grf_regmap, reg, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) val = BIT(offset) | orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val = ~BIT(offset) & orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case GRF_GPIO0AB_SEL_CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (offset >= 4 && offset < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) offset += offset - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else if (offset > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case GRF_GPIO1AB_SEL_CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (offset == 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) offset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (offset > 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case GRF_GPIO2AB_SEL_CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case GRF_GPIO2C_SEL_CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val = 0x3 << ((offset*2) + 16) | (mux ? BIT(offset*2) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case GRF_GPIO3AB_SEL_CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (offset > 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int rk628_pinctrl_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned int func_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int mux = pci->functions[func_selector].mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int offset = pci->groups[group_selector].pins[0] % BANK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int reg = pci->groups[group_selector].iomux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_dbg(pci->dev, "functions[%d]:%s mux=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) func_selector, pci->functions[func_selector].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mux ? "func" : "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) val = rk628_calc_mux_offset(pci, mux, reg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(pci->dev, "groups[%d]:%s pin-number=%d reg=0x%x write-val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) group_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pci->groups[group_selector].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pci->groups[group_selector].pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = regmap_write(pci->grf_regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(pci->dev, "%s regmap write failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int rk628_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct rk628_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int pin_offset, dir_reg, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) chip = range->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pin_offset = offset - range->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (pin_offset / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pin_offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) val = BIT(pin_offset + 16) | (0xffff & ~BIT(pin_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = BIT(pin_offset + 16) | BIT(pin_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = regmap_write(pci->regmap, dir_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(pci->dev, "regmap update failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct pinmux_ops rk628_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .get_functions_count = rk628_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .get_function_name = rk628_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .get_function_groups = rk628_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .set_mux = rk628_pinctrl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .gpio_set_direction = rk628_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int rk628_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pr_err("no support %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int rk628_set_slew_rate(struct rk628_pctrl_info *pci, int pin, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int gpio = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* gpio0b_sl(0-3) gpio1b_sl(0-3 -5) gpio3a_sl(4-7)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) char valid_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 32 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 32 + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 32 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 32 + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 32 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 32 + 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 96 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 96 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 96 + 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 96 + 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int val, ret, offset = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (i = 0; i < sizeof(valid_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (gpio == valid_gpio[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) offset = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (offset == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(pci->dev, "pin%u don't support set slew rate\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val = BIT(offset + 16) | BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) val = BIT(offset + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_dbg(pci->dev, " offset=%d 0x%x\n", offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = regmap_write(pci->grf_regmap, GRF_GPIO_SR_CON, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __func__, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int rk628_calc_pull_reg_and_value(struct rk628_pctrl_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int pull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int gpio2_regs[] = { GRF_GPIO2A_P_CON, GRF_GPIO2B_P_CON, GRF_GPIO2C_P_CON };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int gpio3_regs[] = { GRF_GPIO3A_P_CON, GRF_GPIO3B_P_CON };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int valid_pinnum[] = { 8, 8, 24, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int offset = pin - range->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) switch (range->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (pull == GPIO_PULL_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_err(pci->dev, "pin%u don't support pull up!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (offset == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(pci->dev, "pin%u don't support pull!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *reg = GRF_GPIO0A_P_CON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (pull == GPIO_PULL_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(pci->dev, "pin%u don't support pull up!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (offset == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(pci->dev, "pin%u don't support pull!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *reg = GRF_GPIO1A_P_CON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (pull == GPIO_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pull = GPIO_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else if (pull == GPIO_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pull = GPIO_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *reg = gpio2_regs[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) offset = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (pull == GPIO_PULL_UP && (offset == 2 || offset == 11 || offset == 12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_err(pci->dev, "pin%u don't support pull up!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } else if (pull == GPIO_PULL_DOWN && (offset == 9 || offset == 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(pci->dev, "pin%u don't support pull down!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (pull == GPIO_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pull = GPIO_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) else if (pull == GPIO_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pull = GPIO_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if ((offset > 7 && offset < valid_pinnum[range->id]) || offset < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) *reg = gpio3_regs[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) offset = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int rk628_calc_strength_reg_and_value(struct rk628_pctrl_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int valid_pinnum[] = { 8, 8, 24, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int gpio_regs[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { GRF_GPIO0B_D_CON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { GRF_GPIO1B_D_CON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) GRF_GPIO2A_D0_CON, GRF_GPIO2A_D1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) GRF_GPIO2B_D0_CON, GRF_GPIO2B_D1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) GRF_GPIO2C_D0_CON, GRF_GPIO2C_D1_CON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GRF_GPIO3A_D0_CON, GRF_GPIO3A_D1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) GRF_GPIO3B_D_CON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int offset = pin - range->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) switch (range->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(pci->dev, "pin%u don't support driver strength settings!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) offset -= valid_pinnum[range->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) *val = 0x3 << (2 * offset + 16) | strength << (2 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *reg = gpio_regs[range->id][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) *reg = gpio_regs[range->id][offset / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) offset = offset % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) *val = 0x7 << (4 * offset + 16) | strength << (4 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int rk628_calc_schmitt_reg_and_value(struct rk628_pctrl_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) int gpio2_regs[] = {GRF_GPIO2A_SMT, GRF_GPIO2B_SMT, GRF_GPIO2C_SMT};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int gpio3_reg = GRF_GPIO3AB_SMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int valid_pinnum[] = { 0, 0, 24, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int offset = pin - range->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) switch (range->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (offset < valid_pinnum[range->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *reg = gpio2_regs[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) offset = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *val = BIT(offset + 16) | enable << (offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) *reg = gpio3_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *val = BIT(offset + 16) | enable << (offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pin, *reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dev_err(pci->dev, "pin%u don't support schmitt settings!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int rk628_set_pull(struct rk628_pctrl_info *pci, int pin, int pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int ret, reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = rk628_calc_pull_reg_and_value(pci, pin, pull, ®, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = regmap_write(pci->grf_regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) __func__, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int rk628_set_drive_perpin(struct rk628_pctrl_info *pci, int pin, int strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int ret, reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = rk628_calc_strength_reg_and_value(pci, pin, strength, ®, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = regmap_write(pci->grf_regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __func__, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int rk628_set_schmitt(struct rk628_pctrl_info *pci, int pin, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int ret, reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = rk628_calc_schmitt_reg_and_value(pci, pin, enable, ®, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = regmap_write(pci->grf_regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) __func__, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int rk628_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 i, arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) rk628_set_drive_perpin(pci, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) rk628_set_pull(pci, pin, GPIO_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "PIN_CONFIG_BIAS_PULL_PIN_DEFAULT not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rk628_set_pull(pci, pin, GPIO_PULL_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) rk628_set_pull(pci, pin, GPIO_PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) rk628_set_slew_rate(pci, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) rk628_set_schmitt(pci, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) rk628_gpio_direction_output(range->gc, pin - range->pin_base, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(pci->dev, "Properties not supported param=%d\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static const struct pinconf_ops rk628_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .pin_config_get = rk628_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .pin_config_set = rk628_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static struct pinctrl_desc rk628_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .name = "rk628-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .pctlops = &rk628_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .pmxops = &rk628_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .confops = &rk628_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int rk628_pinctrl_create_function(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct rk628_pctrl_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct device_node *func_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct rk628_pin_function *func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) char *func_sel[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "vop_dclk0", "i2sm0_input", "rxdcc_input0", "hdmirx_cec0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "force_jtag_dis", "uart_iomux_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (of_property_read_string(func_np, "function", &func->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) func->mux_option = PINMUX_FUNC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* for signals input select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (!strcmp(func_sel[i], func->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) func->mux_option = PINMUX_FUNC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_dbg(dev, "%s func->name=%s\n", __func__, func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) npins = of_property_count_strings(func_np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (npins < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_err(dev, "invalid pin list in %s node", func_np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) for (i = 0; i < npins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) const char *gname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = of_property_read_string_index(func_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "pins", i, &gname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "failed to read pin name %d from %s node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) i, func_np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_dbg(dev, "%s func->groups[%d]=%s\n", __func__, i, gname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) func->groups[i] = gname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) func->ngroups = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int rk628_pinctrl_parse_gpiobank(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct rk628_pctrl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct device_node *dev_np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct device_node *cfg_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct rk628_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) for_each_child_of_node(dev_np, cfg_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (of_get_child_count(cfg_np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!of_find_property(cfg_np, "gpio-controller", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) bank = pci->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) for (i = 0; i < pci->nr_banks; ++i, ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (strcmp(bank->name, cfg_np->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bank->of_node = cfg_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) bank->clk = devm_get_clk_from_child(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) bank->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (IS_ERR(bank->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return PTR_ERR(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) clk_prepare(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (count == pci->nr_banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct rk628_pin_function *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rk628_pinctrl_create_functions(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct rk628_pctrl_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) unsigned int *cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct rk628_pin_function *functions, *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct device_node *dev_np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct device_node *cfg_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int func_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) const char *func_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Iterate over all the child nodes of the pin controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * and create pin groups and pin function lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) for_each_child_of_node(dev_np, cfg_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!of_get_child_count(cfg_np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (!of_find_property(cfg_np, "function", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!of_property_read_string(cfg_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "function", &func_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!strncmp("gpio", func_name, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_dbg(dev, "%s: count=%d %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) __func__, func_cnt, func_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ++func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ++func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_dbg(dev, "total_count=%d, count %d for gpio function.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) func_cnt, func_cnt - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) functions = devm_kzalloc(dev, func_cnt * sizeof(*functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) func = functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * Iterate over all the child nodes of the pin controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * and create pin groups and pin function lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) func_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for_each_child_of_node(dev_np, cfg_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!of_get_child_count(cfg_np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (!of_property_read_string(cfg_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) "function", &func_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (!strncmp("gpio", func_name, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = rk628_pinctrl_create_function(dev, pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) cfg_np, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ++func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ++func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* init gpio func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) *(func) = rk628_functions[MUX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) func->mux_option = PINMUX_FUNC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_dbg(dev, "count %d is for %s function\n", func_cnt, func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ++func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ++func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) *cnt = func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static int rk628_pinctrl_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct rk628_pctrl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct rk628_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) unsigned int func_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = rk628_pinctrl_parse_gpiobank(dev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) functions = rk628_pinctrl_create_functions(dev, pci, &func_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (IS_ERR(functions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_err(dev, "failed to parse pin functions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return PTR_ERR(functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pci->functions = functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pci->num_functions = func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const struct regmap_range rk628_pinctrl_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) regmap_reg_range(GPIO2_BASE, GPIO2_BASE + GPIO_VER_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) regmap_reg_range(GPIO3_BASE, GPIO3_BASE + GPIO_VER_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const struct regmap_access_table rk628_pinctrl_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .yes_ranges = rk628_pinctrl_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .n_yes_ranges = ARRAY_SIZE(rk628_pinctrl_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const struct regmap_config rk628_pinctrl_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .name = "pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .max_register = GPIO_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .rd_table = &rk628_pinctrl_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static void rk628_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) unsigned long hwirq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (hwirq / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) hwirq = hwirq - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) offset = GPIO_REG_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) offset = GPIO_REG_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) bank->mask_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static void rk628_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) unsigned long hwirq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (hwirq / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) hwirq = hwirq - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) offset = GPIO_REG_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) offset = GPIO_REG_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) bank->mask_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static int rk628_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) unsigned long hwirq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (hwirq / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) hwirq = hwirq - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) offset = GPIO_REG_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) offset = GPIO_REG_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) bank->bothedge_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) bank->bothedge_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) bank->level_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) bank->polarity_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) bank->bothedge_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) bank->level_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) bank->polarity_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bank->bothedge_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) bank->level_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) bank->polarity_regs[offset] |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) bank->bothedge_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) bank->level_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) bank->polarity_regs[offset] &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev_err(pci->dev, "irq type invalid!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void rk628_irq_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mutex_lock(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static void rk628_irq_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) unsigned long hwirq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u32 offset, inten, level, polarity, bothedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (hwirq / 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) hwirq = hwirq - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) offset = GPIO_REG_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) offset = GPIO_REG_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) inten = (bank->reg_base + GPIO_INTEN_L + ((offset) * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) level = (bank->reg_base + GPIO_INTTYPE_L + ((offset) * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) polarity = (bank->reg_base + GPIO_INT_POLARITY_L + ((offset) * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) bothedge = (bank->reg_base + GPIO_INT_BOTHEDGE_L + ((offset) * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = regmap_write(pci->regmap, level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) bank->level_regs[offset] | BIT(hwirq + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) level, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = regmap_write(pci->regmap, polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) bank->polarity_regs[offset] | BIT(hwirq + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) polarity, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ret = regmap_write(pci->regmap, bothedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) bank->bothedge_regs[offset] | BIT(hwirq + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) bothedge, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = regmap_write(pci->regmap, inten,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) bank->mask_regs[offset] | BIT(hwirq + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) inten, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mutex_unlock(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) enum rk628_irqchip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) IRQCHIP_gpio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) IRQCHIP_gpio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) IRQCHIP_gpio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) IRQCHIP_gpio3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct irq_chip rk628_irq_chip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) IRQ_CHIP(gpio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) IRQ_CHIP(gpio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) IRQ_CHIP(gpio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) IRQ_CHIP(gpio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int rk628_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct rk628_pin_bank *bank = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) irq_set_chip_data(virq, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) irq_set_chip(virq, &bank->irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) irq_set_nested_thread(virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const struct irq_domain_ops rk628_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .map = rk628_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static irqreturn_t rk628_irq_demux_thread(int irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct rk628_pin_bank *bank = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct rk628_pctrl_info *pci = bank->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) u32 pend, low_bit, high_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = regmap_read(pci->regmap, bank->reg_base + GPIO_INT_STATUS, &pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) low_bit = pend & 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) high_bit = (pend >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) (low_bit << 16) | low_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) (high_bit << 16) | high_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) while (pend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) unsigned int irq, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) irq = __ffs(pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) pend &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) virq = irq_linear_revmap(bank->domain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (!virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) dev_err(pci->dev, "unmapped irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) handle_nested_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static int rk628_interrupts_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct rk628_pctrl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct rk628_pin_bank *bank = pci->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) for (i = 0; i < pci->nr_banks; ++i, ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) mutex_init(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ret = clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) bank->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) bank->irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) bank->irq_chip = rk628_irq_chip[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) bank->domain = irq_domain_add_linear(bank->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) bank->nr_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) &rk628_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (!bank->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) "could not initialize irq domain for bank %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) bank->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = request_threaded_irq(bank->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) rk628_irq_demux_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) bank->name, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "Failed to request IRQ %d for %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) bank->irq, bank->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static int rk628_gpiolib_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct rk628_pctrl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct rk628_pin_bank *bank = pci->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) for (i = 0; i < pci->nr_banks; ++i, ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) bank->gpio_chip = rk628_gpiolib_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) bank->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) gc = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) gc->ngpio = bank->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) gc->of_node = bank->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) gc->label = bank->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ret = devm_gpiochip_add_data(&pdev->dev, gc, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) "failed to register gpio_chip %s, error code: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) gc->label, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static int rk628_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct rk628_pctrl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct rk628_pin_bank *pin_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pci->grf_regmap = rk628->grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pci->pinctrl_desc = rk628_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) pci->groups = rk628_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) pci->num_groups = ARRAY_SIZE(rk628_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pci->pinctrl_desc.pins = rk628_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pci->pinctrl_desc.npins = ARRAY_SIZE(rk628_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pci->pin_banks = rk628_pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pci->nr_banks = ARRAY_SIZE(rk628_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) platform_set_drvdata(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = rk628_pinctrl_parse_dt(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) pci->regmap = devm_regmap_init_i2c(rk628->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) &rk628_pinctrl_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (IS_ERR(pci->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ret = PTR_ERR(pci->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dev_err(dev, "failed to allocate register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* Add gpiochip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ret = rk628_gpiolib_register(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dev_err(&pdev->dev, "Couldn't add gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* Add pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (IS_ERR(pci->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) dev_err(&pdev->dev, "Couldn't add pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return PTR_ERR(pci->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) for (bank = 0; bank < pci->nr_banks; ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) pin_bank = &pci->pin_banks[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pin_bank->grange.name = pin_bank->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) pin_bank->grange.id = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) pin_bank->grange.pin_base = BANK_OFFSET * bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) pin_bank->grange.base = pin_bank->gpio_chip.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pin_bank->grange.gc = &pin_bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) pinctrl_add_gpio_range(pci->pctl, &pin_bank->grange);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rk628_interrupts_register(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static const struct of_device_id rk628_pinctrl_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) { .compatible = "rockchip,rk628-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) MODULE_DEVICE_TABLE(of, rk628_pinctrl_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static struct platform_driver rk628_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .probe = rk628_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .name = "rk628-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .of_match_table = of_match_ptr(rk628_pinctrl_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) module_platform_driver(rk628_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) MODULE_DESCRIPTION("RK628 pin control and GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) MODULE_AUTHOR("Weixin Zhou <zwx@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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