^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pistachio SoC pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PADS_SCHMITT_EN0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PADS_PU_PD0 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PADS_PU_PD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PADS_PU_PD_HIGHZ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PADS_PU_PD_UP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PADS_PU_PD_DOWN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PADS_PU_PD_BUS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PADS_FUNCTION_SELECT0 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PADS_FUNCTION_SELECT1 0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PADS_FUNCTION_SELECT2 0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PADS_SCENARIO_SELECT 0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PADS_SLEW_RATE0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PADS_DRIVE_STRENGTH0 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PADS_DRIVE_STRENGTH_REG(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PADS_DRIVE_STRENGTH_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PADS_DRIVE_STRENGTH_2MA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PADS_DRIVE_STRENGTH_4MA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PADS_DRIVE_STRENGTH_8MA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PADS_DRIVE_STRENGTH_12MA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_BIT_EN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_OUTPUT_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_OUTPUT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO_INPUT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_INPUT_POLARITY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_INTERRUPT_TYPE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_INTERRUPT_TYPE_LEVEL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_INTERRUPT_TYPE_EDGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPIO_INTERRUPT_EDGE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPIO_INTERRUPT_EDGE_SINGLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPIO_INTERRUPT_EDGE_DUAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO_INTERRUPT_EN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO_INTERRUPT_STATUS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pistachio_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const int *scenarios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int nscenarios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int scenario_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int scenario_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int scenario_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pistachio_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int mux_option[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct pistachio_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct pistachio_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pistachio_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct pistachio_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct pistachio_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct pistachio_gpio_bank *gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PISTACHIO_PIN_MFIO(p) (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PISTACHIO_PIN_TCK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PISTACHIO_PIN_TRSTN 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PISTACHIO_PIN_TDI 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PISTACHIO_PIN_TMS 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PISTACHIO_PIN_TDO 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PISTACHIO_PIN_JTAG_COMPLY 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PISTACHIO_PIN_SAFE_MODE 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PISTACHIO_PIN_POR_DISABLE 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PISTACHIO_PIN_RESETN 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct pinctrl_pin_desc pistachio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MFIO_PIN_DESC(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MFIO_PIN_DESC(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MFIO_PIN_DESC(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MFIO_PIN_DESC(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MFIO_PIN_DESC(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MFIO_PIN_DESC(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MFIO_PIN_DESC(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MFIO_PIN_DESC(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MFIO_PIN_DESC(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MFIO_PIN_DESC(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MFIO_PIN_DESC(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MFIO_PIN_DESC(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MFIO_PIN_DESC(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MFIO_PIN_DESC(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MFIO_PIN_DESC(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MFIO_PIN_DESC(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MFIO_PIN_DESC(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MFIO_PIN_DESC(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MFIO_PIN_DESC(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MFIO_PIN_DESC(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MFIO_PIN_DESC(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MFIO_PIN_DESC(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MFIO_PIN_DESC(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MFIO_PIN_DESC(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MFIO_PIN_DESC(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MFIO_PIN_DESC(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MFIO_PIN_DESC(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MFIO_PIN_DESC(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MFIO_PIN_DESC(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MFIO_PIN_DESC(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MFIO_PIN_DESC(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MFIO_PIN_DESC(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MFIO_PIN_DESC(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MFIO_PIN_DESC(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MFIO_PIN_DESC(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MFIO_PIN_DESC(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MFIO_PIN_DESC(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MFIO_PIN_DESC(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MFIO_PIN_DESC(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MFIO_PIN_DESC(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MFIO_PIN_DESC(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MFIO_PIN_DESC(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MFIO_PIN_DESC(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MFIO_PIN_DESC(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MFIO_PIN_DESC(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MFIO_PIN_DESC(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MFIO_PIN_DESC(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MFIO_PIN_DESC(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MFIO_PIN_DESC(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MFIO_PIN_DESC(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MFIO_PIN_DESC(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MFIO_PIN_DESC(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MFIO_PIN_DESC(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MFIO_PIN_DESC(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MFIO_PIN_DESC(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MFIO_PIN_DESC(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MFIO_PIN_DESC(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MFIO_PIN_DESC(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MFIO_PIN_DESC(58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MFIO_PIN_DESC(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MFIO_PIN_DESC(60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MFIO_PIN_DESC(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MFIO_PIN_DESC(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MFIO_PIN_DESC(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MFIO_PIN_DESC(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MFIO_PIN_DESC(65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MFIO_PIN_DESC(66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MFIO_PIN_DESC(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MFIO_PIN_DESC(68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MFIO_PIN_DESC(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MFIO_PIN_DESC(70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MFIO_PIN_DESC(71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MFIO_PIN_DESC(72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MFIO_PIN_DESC(73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MFIO_PIN_DESC(74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MFIO_PIN_DESC(75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MFIO_PIN_DESC(76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MFIO_PIN_DESC(77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MFIO_PIN_DESC(78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MFIO_PIN_DESC(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MFIO_PIN_DESC(80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MFIO_PIN_DESC(81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MFIO_PIN_DESC(82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MFIO_PIN_DESC(83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MFIO_PIN_DESC(84),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MFIO_PIN_DESC(85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MFIO_PIN_DESC(86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MFIO_PIN_DESC(87),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MFIO_PIN_DESC(88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MFIO_PIN_DESC(89),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const pistachio_spim0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "mfio30", "mfio55", "mfio56", "mfio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const char * const pistachio_spim1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const char * const pistachio_spis_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "mfio11", "mfio12", "mfio13", "mfio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const char *const pistachio_sdhost_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "mfio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char * const pistachio_i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "mfio28", "mfio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const pistachio_i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "mfio30", "mfio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const pistachio_i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "mfio32", "mfio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char * const pistachio_i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "mfio34", "mfio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const pistachio_audio_clk_in_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "mfio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const char * const pistachio_i2s_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "mfio42", "mfio43", "mfio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const char * const pistachio_debug_raw_cca_ind_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "mfio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "mfio38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "mfio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char * const pistachio_debug_agc_done_0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "mfio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char * const pistachio_debug_agc_done_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "mfio41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const pistachio_debug_ed_cca_ind_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "mfio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char * const pistachio_debug_s2l_done_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "mfio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char * const pistachio_i2s_dac_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "mfio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char * const pistachio_audio_sync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "mfio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const char * const pistachio_audio_trigger_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "mfio46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const char * const pistachio_i2s_in_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "mfio53", "mfio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const char * const pistachio_uart0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "mfio55", "mfio56", "mfio57", "mfio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const pistachio_uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "mfio59", "mfio60", "mfio1", "mfio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const char * const pistachio_spdif_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "mfio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const char * const pistachio_spdif_in_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "mfio62", "mfio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const int pistachio_spdif_in_scenarios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PISTACHIO_PIN_MFIO(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PISTACHIO_PIN_MFIO(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const char * const pistachio_eth_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "mfio69", "mfio70", "mfio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const char * const pistachio_ir_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "mfio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const char * const pistachio_pwmpdm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "mfio73", "mfio74", "mfio75", "mfio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const char * const pistachio_mips_trace_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "mfio15", "mfio63", "mfio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const char * const pistachio_mips_trace_dint_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "mfio16", "mfio64", "mfio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const int pistachio_mips_trace_dint_scenarios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PISTACHIO_PIN_MFIO(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PISTACHIO_PIN_MFIO(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PISTACHIO_PIN_MFIO(74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char * const pistachio_mips_trace_trigout_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "mfio17", "mfio65", "mfio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char * const pistachio_mips_trace_trigin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "mfio18", "mfio66", "mfio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const int pistachio_mips_trace_trigin_scenarios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PISTACHIO_PIN_MFIO(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PISTACHIO_PIN_MFIO(66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PISTACHIO_PIN_MFIO(76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const char * const pistachio_mips_trace_dm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "mfio19", "mfio67", "mfio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const char * const pistachio_mips_probe_n_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "mfio20", "mfio68", "mfio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const int pistachio_mips_probe_n_scenarios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PISTACHIO_PIN_MFIO(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PISTACHIO_PIN_MFIO(68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PISTACHIO_PIN_MFIO(78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const char * const pistachio_mips_trace_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const char * const pistachio_sram_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "mfio73", "mfio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char * const pistachio_rom_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "mfio75", "mfio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char * const pistachio_rpu_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "mfio77", "mfio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const char * const pistachio_mips_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "mfio79", "mfio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const char * const pistachio_eth_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "mfio81", "mfio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const char * const pistachio_usb_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "mfio83", "mfio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const char * const pistachio_sdhost_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "mfio85", "mfio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char * const pistachio_socif_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "mfio87", "mfio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const pistachio_mdc_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "mfio77", "mfio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const char * const pistachio_ddr_debug_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "mfio79", "mfio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const char * const pistachio_dreq0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "mfio81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const char * const pistachio_dreq1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "mfio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const char * const pistachio_dreq2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "mfio87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const char * const pistachio_dreq3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "mfio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const char * const pistachio_dreq4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "mfio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const char * const pistachio_dreq5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "mfio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const char * const pistachio_mips_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "mfio83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const char * const pistachio_audio_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "mfio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const char * const pistachio_rpu_v_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "mfio85",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const char * const pistachio_rpu_l_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "mfio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const char * const pistachio_sys_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "mfio87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const char * const pistachio_wifi_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "mfio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const char * const pistachio_bt_pll_lock_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "mfio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FUNCTION(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .groups = pistachio_##_name##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .groups = pistachio_##_name##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .scenarios = pistachio_##_name##_scenarios, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .scenario_reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .scenario_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .scenario_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) enum pistachio_mux_option {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PISTACHIO_FUNCTION_NONE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PISTACHIO_FUNCTION_SPIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PISTACHIO_FUNCTION_SPIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PISTACHIO_FUNCTION_SPIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PISTACHIO_FUNCTION_SDHOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PISTACHIO_FUNCTION_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PISTACHIO_FUNCTION_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PISTACHIO_FUNCTION_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PISTACHIO_FUNCTION_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PISTACHIO_FUNCTION_AUDIO_CLK_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PISTACHIO_FUNCTION_I2S_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PISTACHIO_FUNCTION_I2S_DAC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PISTACHIO_FUNCTION_AUDIO_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PISTACHIO_FUNCTION_AUDIO_TRIGGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PISTACHIO_FUNCTION_I2S_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PISTACHIO_FUNCTION_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PISTACHIO_FUNCTION_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PISTACHIO_FUNCTION_SPDIF_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PISTACHIO_FUNCTION_SPDIF_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PISTACHIO_FUNCTION_ETH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PISTACHIO_FUNCTION_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PISTACHIO_FUNCTION_PWMPDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PISTACHIO_FUNCTION_MIPS_TRACE_DM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PISTACHIO_FUNCTION_SRAM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PISTACHIO_FUNCTION_ROM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PISTACHIO_FUNCTION_RPU_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PISTACHIO_FUNCTION_MIPS_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PISTACHIO_FUNCTION_ETH_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PISTACHIO_FUNCTION_USB_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PISTACHIO_FUNCTION_SDHOST_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PISTACHIO_FUNCTION_SOCIF_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PISTACHIO_FUNCTION_MDC_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PISTACHIO_FUNCTION_DDR_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PISTACHIO_FUNCTION_DREQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PISTACHIO_FUNCTION_DREQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PISTACHIO_FUNCTION_DREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PISTACHIO_FUNCTION_DREQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PISTACHIO_FUNCTION_DREQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PISTACHIO_FUNCTION_DREQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PISTACHIO_FUNCTION_SYS_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PISTACHIO_FUNCTION_BT_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct pistachio_function pistachio_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) FUNCTION(spim0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) FUNCTION(spim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) FUNCTION(spis),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) FUNCTION(sdhost),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) FUNCTION(audio_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) FUNCTION(i2s_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) FUNCTION(i2s_dac_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) FUNCTION(audio_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) FUNCTION(audio_trigger),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) FUNCTION(i2s_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) FUNCTION(spdif_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) FUNCTION(eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) FUNCTION(ir),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) FUNCTION(pwmpdm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) FUNCTION(mips_trace_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) FUNCTION(mips_trace_trigout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) FUNCTION(mips_trace_dm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) FUNCTION(mips_trace_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) FUNCTION(sram_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) FUNCTION(rom_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) FUNCTION(rpu_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) FUNCTION(mips_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) FUNCTION(eth_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) FUNCTION(usb_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) FUNCTION(sdhost_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) FUNCTION(socif_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) FUNCTION(mdc_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) FUNCTION(ddr_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) FUNCTION(dreq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) FUNCTION(dreq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) FUNCTION(dreq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) FUNCTION(dreq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) FUNCTION(dreq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) FUNCTION(dreq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) FUNCTION(mips_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) FUNCTION(audio_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) FUNCTION(rpu_v_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) FUNCTION(rpu_l_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) FUNCTION(sys_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) FUNCTION(wifi_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) FUNCTION(bt_pll_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) FUNCTION(debug_raw_cca_ind),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) FUNCTION(debug_ed_sec20_cca_ind),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) FUNCTION(debug_ed_sec40_cca_ind),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) FUNCTION(debug_agc_done_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) FUNCTION(debug_agc_done_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) FUNCTION(debug_ed_cca_ind),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) FUNCTION(debug_s2l_done),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define PIN_GROUP(_pin, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .pin = PISTACHIO_PIN_##_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .mux_option = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PISTACHIO_FUNCTION_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PISTACHIO_FUNCTION_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PISTACHIO_FUNCTION_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .mux_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .mux_mask = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MFIO_PIN_GROUP(_pin, _func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .name = "mfio" #_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .pin = PISTACHIO_PIN_MFIO(_pin), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .mux_option = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PISTACHIO_FUNCTION_##_func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PISTACHIO_FUNCTION_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PISTACHIO_FUNCTION_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .mux_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .mux_mask = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .name = "mfio" #_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .pin = PISTACHIO_PIN_MFIO(_pin), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .mux_option = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PISTACHIO_FUNCTION_##_f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PISTACHIO_FUNCTION_##_f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PISTACHIO_FUNCTION_##_f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mux_reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .mux_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .mux_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const struct pistachio_pin_group pistachio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MFIO_PIN_GROUP(0, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PADS_FUNCTION_SELECT0, 0, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PADS_FUNCTION_SELECT0, 2, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MFIO_PIN_GROUP(3, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MFIO_PIN_GROUP(4, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MFIO_PIN_GROUP(5, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MFIO_PIN_GROUP(6, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MFIO_PIN_GROUP(7, SPIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MFIO_PIN_GROUP(8, SPIM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MFIO_PIN_GROUP(9, SPIM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MFIO_PIN_GROUP(10, SPIM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MFIO_PIN_GROUP(11, SPIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MFIO_PIN_GROUP(12, SPIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MFIO_PIN_GROUP(13, SPIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MFIO_PIN_GROUP(14, SPIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PADS_FUNCTION_SELECT0, 4, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PADS_FUNCTION_SELECT0, 6, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PADS_FUNCTION_SELECT0, 8, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PADS_FUNCTION_SELECT0, 10, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PADS_FUNCTION_SELECT0, 12, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PADS_FUNCTION_SELECT0, 14, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PADS_FUNCTION_SELECT0, 16, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PADS_FUNCTION_SELECT0, 18, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MFIO_PIN_GROUP(23, SDHOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MFIO_PIN_GROUP(24, SDHOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MFIO_PIN_GROUP(25, SDHOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MFIO_PIN_GROUP(26, SDHOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MFIO_PIN_GROUP(27, SDHOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PADS_FUNCTION_SELECT0, 20, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PADS_FUNCTION_SELECT0, 21, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PADS_FUNCTION_SELECT0, 22, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PADS_FUNCTION_SELECT0, 23, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MFIO_PIN_GROUP(32, I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MFIO_PIN_GROUP(33, I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MFIO_PIN_GROUP(34, I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MFIO_PIN_GROUP(35, I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PADS_FUNCTION_SELECT0, 24, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PADS_FUNCTION_SELECT0, 25, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PADS_FUNCTION_SELECT0, 26, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PADS_FUNCTION_SELECT0, 27, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PADS_FUNCTION_SELECT0, 28, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PADS_FUNCTION_SELECT0, 29, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PADS_FUNCTION_SELECT0, 30, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PADS_FUNCTION_SELECT0, 31, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MFIO_PIN_GROUP(44, I2S_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PADS_FUNCTION_SELECT1, 0, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MFIO_PIN_GROUP(47, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MFIO_PIN_GROUP(48, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MFIO_PIN_GROUP(49, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MFIO_PIN_GROUP(50, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MFIO_PIN_GROUP(51, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MFIO_PIN_GROUP(52, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) MFIO_PIN_GROUP(53, I2S_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PADS_FUNCTION_SELECT1, 1, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PADS_FUNCTION_SELECT1, 3, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PADS_FUNCTION_SELECT1, 5, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PADS_FUNCTION_SELECT1, 7, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PADS_FUNCTION_SELECT1, 9, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MFIO_PIN_GROUP(59, UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MFIO_PIN_GROUP(60, UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MFIO_PIN_GROUP(61, SPDIF_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MFIO_PIN_GROUP(62, SPDIF_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PADS_FUNCTION_SELECT1, 10, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PADS_FUNCTION_SELECT1, 12, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PADS_FUNCTION_SELECT1, 14, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PADS_FUNCTION_SELECT1, 16, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PADS_FUNCTION_SELECT1, 18, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PADS_FUNCTION_SELECT1, 20, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PADS_FUNCTION_SELECT1, 22, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PADS_FUNCTION_SELECT1, 24, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) MFIO_PIN_GROUP(71, ETH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MFIO_PIN_GROUP(72, IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PADS_FUNCTION_SELECT1, 26, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PADS_FUNCTION_SELECT1, 28, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PADS_FUNCTION_SELECT1, 30, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PADS_FUNCTION_SELECT2, 0, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PADS_FUNCTION_SELECT2, 2, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PADS_FUNCTION_SELECT2, 4, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PADS_FUNCTION_SELECT2, 6, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PADS_FUNCTION_SELECT2, 8, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PADS_FUNCTION_SELECT2, 10, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PADS_FUNCTION_SELECT2, 12, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PADS_FUNCTION_SELECT2, 14, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PADS_FUNCTION_SELECT2, 16, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PADS_FUNCTION_SELECT2, 18, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PADS_FUNCTION_SELECT2, 20, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PADS_FUNCTION_SELECT2, 22, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PADS_FUNCTION_SELECT2, 24, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PADS_FUNCTION_SELECT2, 26, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PIN_GROUP(TCK, "tck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PIN_GROUP(TRSTN, "trstn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PIN_GROUP(TDI, "tdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PIN_GROUP(TMS, "tms"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PIN_GROUP(TDO, "tdo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PIN_GROUP(SAFE_MODE, "safe_mode"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PIN_GROUP(POR_DISABLE, "por_disable"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PIN_GROUP(RESETN, "resetn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return readl(pctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) writel(val, pctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return readl(bank->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) writel(val, bank->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 reg, unsigned int bit, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * For most of the GPIO registers, bit 16 + X must be set in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * write bit X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) gpio_writel(bank, (0x10000 | val) << bit, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static inline void gpio_enable(struct pistachio_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static inline void gpio_disable(struct pistachio_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return pctl->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) *pins = &pctl->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const struct pinctrl_ops pistachio_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .get_groups_count = pistachio_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .get_group_name = pistachio_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .get_group_pins = pistachio_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return pctl->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return pctl->functions[func].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) *groups = pctl->functions[func].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) *num_groups = pctl->functions[func].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned func, unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) const struct pistachio_pin_group *pg = &pctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) const struct pistachio_function *pf = &pctl->functions[func];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (pg->mux_reg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (pg->mux_option[i] == func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (i == ARRAY_SIZE(pg->mux_option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) group, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) val = pctl_readl(pctl, pg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) val &= ~(pg->mux_mask << pg->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) val |= i << pg->mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pctl_writel(pctl, val, pg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (pf->scenarios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) for (i = 0; i < pf->nscenarios; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (pf->scenarios[i] == group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (WARN_ON(i == pf->nscenarios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) val = pctl_readl(pctl, pf->scenario_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) val &= ~(pf->scenario_mask << pf->scenario_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) val |= i << pf->scenario_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pctl_writel(pctl, val, pf->scenario_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct pinmux_ops pistachio_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .get_functions_count = pistachio_pinmux_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .get_function_name = pistachio_pinmux_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .get_function_groups = pistachio_pinmux_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .set_mux = pistachio_pinmux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 val, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) arg = !!(val & PADS_SLEW_RATE_BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PADS_DRIVE_STRENGTH_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) switch (val & PADS_DRIVE_STRENGTH_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case PADS_DRIVE_STRENGTH_2MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) arg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case PADS_DRIVE_STRENGTH_4MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) arg = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case PADS_DRIVE_STRENGTH_8MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) arg = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case PADS_DRIVE_STRENGTH_12MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) arg = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_dbg(pctl->dev, "Property %u not supported\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 drv, val, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) val |= PADS_SCHMITT_EN_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val &= ~PADS_SCHMITT_EN_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) val |= PADS_SLEW_RATE_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) val &= ~PADS_SLEW_RATE_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) val &= ~(PADS_DRIVE_STRENGTH_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PADS_DRIVE_STRENGTH_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) drv = PADS_DRIVE_STRENGTH_2MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) drv = PADS_DRIVE_STRENGTH_4MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) drv = PADS_DRIVE_STRENGTH_8MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) drv = PADS_DRIVE_STRENGTH_12MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "Drive strength %umA not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_err(pctl->dev, "Property %u not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const struct pinconf_ops pistachio_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .pin_config_get = pistachio_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .pin_config_set = pistachio_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static struct pinctrl_desc pistachio_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .name = "pistachio-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .pctlops = &pistachio_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .pmxops = &pistachio_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .confops = &pistachio_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) reg = GPIO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) reg = GPIO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return !!(gpio_readl(bank, reg) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int pistachio_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) gpio_enable(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int pistachio_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pistachio_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) gpio_enable(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static void pistachio_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct pistachio_gpio_bank *bank = irqd_to_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static void pistachio_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct pistachio_gpio_bank *bank = irqd_to_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static void pistachio_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct pistachio_gpio_bank *bank = irqd_to_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pistachio_gpio_direction_input(chip, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pistachio_gpio_irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct pistachio_gpio_bank *bank = irqd_to_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) GPIO_INTERRUPT_TYPE_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) GPIO_INTERRUPT_EDGE_SINGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) GPIO_INTERRUPT_TYPE_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) GPIO_INTERRUPT_EDGE_SINGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GPIO_INTERRUPT_TYPE_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GPIO_INTERRUPT_EDGE_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) GPIO_INTERRUPT_TYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GPIO_INTERRUPT_TYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static void pistachio_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) gpio_readl(bank, GPIO_INTERRUPT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) for_each_set_bit(pin, &pending, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define GPIO_BANK(_bank, _pin_base, _npins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .pin_base = _pin_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .npins = _npins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .gpio_chip = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .label = "GPIO" #_bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .request = gpiochip_generic_request, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .free = gpiochip_generic_free, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .get_direction = pistachio_gpio_get_direction, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .direction_input = pistachio_gpio_direction_input, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .direction_output = pistachio_gpio_direction_output, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .get = pistachio_gpio_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .set = pistachio_gpio_set, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .base = _pin_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .ngpio = _npins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .irq_chip = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .name = "GPIO" #_bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .irq_startup = pistachio_gpio_irq_startup, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .irq_ack = pistachio_gpio_irq_ack, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .irq_mask = pistachio_gpio_irq_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .irq_unmask = pistachio_gpio_irq_unmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .irq_set_type = pistachio_gpio_irq_set_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct device_node *node = pctl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct pistachio_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) for (i = 0; i < pctl->nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) char child_name[sizeof("gpioXX")];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) snprintf(child_name, sizeof(child_name), "gpio%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) child = of_get_child_by_name(node, child_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_err(pctl->dev, "No node for bank %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!of_find_property(child, "gpio-controller", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "No gpio-controller property for bank %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) irq = irq_of_parse_and_map(child, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) bank = &pctl->gpio_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) bank->pctl = pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bank->base = pctl->base + GPIO_BANK_BASE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) bank->gpio_chip.parent = pctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) bank->gpio_chip.of_node = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) girq = &bank->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) girq->chip = &bank->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) girq->parent_handler = pistachio_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) girq->parents = devm_kcalloc(pctl->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = gpiochip_add_data(&bank->gpio_chip, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = gpiochip_add_pin_range(&bank->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_name(pctl->dev), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) bank->pin_base, bank->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) gpiochip_remove(&bank->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) for (; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) bank = &pctl->gpio_banks[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) gpiochip_remove(&bank->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const struct of_device_id pistachio_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) { .compatible = "img,pistachio-system-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static int pistachio_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct pistachio_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_set_drvdata(&pdev->dev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (IS_ERR(pctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return PTR_ERR(pctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) pctl->pins = pistachio_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pctl->npins = ARRAY_SIZE(pistachio_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) pctl->functions = pistachio_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) pctl->groups = pistachio_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pctl->ngroups = ARRAY_SIZE(pistachio_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) pctl->gpio_banks = pistachio_gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pistachio_pinctrl_desc.pins = pctl->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pistachio_pinctrl_desc.npins = pctl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (IS_ERR(pctl->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_err(&pdev->dev, "Failed to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return PTR_ERR(pctl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return pistachio_gpio_register(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static struct platform_driver pistachio_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = "pistachio-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .of_match_table = pistachio_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .probe = pistachio_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static int __init pistachio_pinctrl_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return platform_driver_register(&pistachio_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) arch_initcall(pistachio_pinctrl_register);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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