^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pinctrl-palmas.c -- TI PALMAS series pin control driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mfd/palmas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PALMAS_PIN_GPIO0_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PALMAS_PIN_GPIO3_CHRG_DET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PALMAS_PIN_GPIO4_SYSEN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PALMAS_PIN_GPIO6_SYSEN2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PALMAS_PIN_GPIO8_SIM1RSTI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PALMAS_PIN_GPIO9_LOW_VBAT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PALMAS_PIN_GPIO11_RCM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PALMAS_PIN_GPIO12_SIM2RSTO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PALMAS_PIN_GPIO13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PALMAS_PIN_GPIO14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PALMAS_PIN_GPIO15_SIM2RSTI 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PALMAS_PIN_VAC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PALMAS_PIN_POWERGOOD_USB_PSEL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PALMAS_PIN_NRESWARM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PALMAS_PIN_PWRDOWN 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PALMAS_PIN_GPADC_START 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PALMAS_PIN_RESET_IN 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PALMAS_PIN_NSLEEP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PALMAS_PIN_ENABLE1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PALMAS_PIN_ENABLE2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PALMAS_PIN_INT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct palmas_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct palmas_pctrl_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct palmas *palmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int pins_current_opt[PALMAS_PIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct palmas_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct palmas_pingroup *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct pinctrl_pin_desc palmas_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(PALMAS_PIN_INT, "int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const char * const opt0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "vac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "powergood",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "nreswarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "pwrdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "gpadc_start",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "reset_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "nsleep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "enable1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "enable2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char * const opt1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "vac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "powergood",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const char * const opt2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const char * const opt3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const char * const led_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const pwm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const char * const regen_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const char * const sysen_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char * const clk32kgaudio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const id_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const vbus_det_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const chrg_det_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const vac_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "vac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const vacok_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "vac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const powergood_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "powergood",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char * const usb_psel_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "powergood",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char * const msecure_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const char * const pwrhold_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const char * const int_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char * const nreswarm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "nreswarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const char * const simrsto_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const simrsti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const char * const low_vbat_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char * const wireless_chrg1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char * const rcm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const char * const pwrdown_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "pwrdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const gpadc_start_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "gpadc_start",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char * const reset_in_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "reset_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char * const nsleep_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "nsleep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "enable1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "enable2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define FUNCTION_GROUPS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FUNCTION_GROUP(opt0, OPTION0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FUNCTION_GROUP(opt1, OPTION1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FUNCTION_GROUP(opt2, OPTION2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FUNCTION_GROUP(opt3, OPTION3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FUNCTION_GROUP(gpio, GPIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FUNCTION_GROUP(led, LED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FUNCTION_GROUP(pwm, PWM), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FUNCTION_GROUP(regen, REGEN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FUNCTION_GROUP(sysen, SYSEN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FUNCTION_GROUP(id, ID), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FUNCTION_GROUP(vbus_det, VBUS_DET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FUNCTION_GROUP(chrg_det, CHRG_DET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FUNCTION_GROUP(vac, VAC), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FUNCTION_GROUP(vacok, VACOK), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FUNCTION_GROUP(powergood, POWERGOOD), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FUNCTION_GROUP(usb_psel, USB_PSEL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FUNCTION_GROUP(msecure, MSECURE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FUNCTION_GROUP(pwrhold, PWRHOLD), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FUNCTION_GROUP(int, INT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FUNCTION_GROUP(nreswarm, NRESWARM), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FUNCTION_GROUP(simrsto, SIMRSTO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FUNCTION_GROUP(simrsti, SIMRSTI), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FUNCTION_GROUP(low_vbat, LOW_VBAT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FUNCTION_GROUP(rcm, RCM), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FUNCTION_GROUP(pwrdown, PWRDOWN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FUNCTION_GROUP(gpadc_start, GPADC_START), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FUNCTION_GROUP(reset_in, RESET_IN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) FUNCTION_GROUP(nsleep, NSLEEP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FUNCTION_GROUP(enable, ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct palmas_pin_function palmas_pin_function[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #undef FUNCTION_GROUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FUNCTION_GROUP(fname, mux) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FUNCTION_GROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum palmas_pinmux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #undef FUNCTION_GROUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FUNCTION_GROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PALMAS_PINMUX_NA = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct palmas_pins_pullup_dn_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int pullup_dn_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int pullup_dn_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int pullup_dn_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int normal_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int pull_up_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int pull_dn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct palmas_pins_od_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int od_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int od_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int od_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int od_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int od_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct palmas_pin_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enum palmas_pinmux mux_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const struct palmas_pins_pullup_dn_info *pud_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) const struct palmas_pins_od_info *od_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct palmas_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const unsigned pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned mux_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned mux_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned mux_reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned mux_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const struct palmas_pin_info *opt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .pullup_dn_reg_add = _add, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pullup_dn_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .normal_val = _nv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pull_up_val = _uv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .pull_dn_val = _dv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct palmas_pins_od_info od_##_name##_info = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .od_reg_base = PALMAS_##_rbase##_BASE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .od_reg_add = _add, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .od_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .od_enable = _ev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .od_disable = _dv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PIN_INFO(_name, _id, _pud_info, _od_info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct palmas_pin_info pin_##_name##_info = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .mux_opt = PALMAS_PINMUX_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .pud_info = _pud_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .od_info = _od_info \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PIN_INFO(gpio8, GPIO, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PIN_INFO(gpio12, GPIO, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PIN_INFO(gpio15, GPIO, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PIN_INFO(id, ID, &pud_id_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PIN_INFO(led1, LED, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PIN_INFO(led2, LED, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PIN_INFO(regen, REGEN, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PIN_INFO(sysen1, SYSEN, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PIN_INFO(sysen2, SYSEN, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PIN_INFO(int, INT, NULL, &od_int_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PIN_INFO(enable1, NA, &pud_enable1_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PIN_INFO(enable2, NA, &pud_enable2_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PIN_INFO(usb_psel, USB_PSEL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PIN_INFO(vac, VAC, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PIN_INFO(powergood, POWERGOOD, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PIN_INFO(rcm, RCM, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PALMAS_PRIMARY_SECONDARY_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PALMAS_NONE_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .pins = {PALMAS_PIN_##pin_id}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .npins = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mux_reg_base = PALMAS_##base##_BASE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .mux_reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .mux_bit_shift = _bshift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .opt = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) o0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) o1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) o2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) o3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct palmas_pingroup tps65913_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct palmas_pingroup tps80036_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) const struct palmas_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0; i < pci->num_pin_groups; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) g = &pci->pin_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (g->mux_reg_base == PALMAS_NONE_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pci->pins_current_opt[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = palmas_read(pci->palmas, g->mux_reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) g->mux_reg_add, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) g->mux_reg_add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val &= g->mux_reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pci->pins_current_opt[i] = val >> g->mux_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PALMAS_PRIMARY_SECONDARY_PAD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PALMAS_PRIMARY_SECONDARY_PAD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return pci->num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return pci->pin_groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned group, const unsigned **pins, unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *pins = pci->pin_groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *num_pins = pci->pin_groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct pinctrl_ops palmas_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .get_groups_count = palmas_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .get_group_name = palmas_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .get_group_pins = palmas_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return pci->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return pci->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned function, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *groups = pci->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *num_groups = pci->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const struct palmas_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) g = &pci->pin_groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* If direct option is provided here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (function <= PALMAS_PINMUX_OPTION3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!g->opt[function]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(pci->dev, "Pin %s does not support option %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) g->name, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) i = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!g->opt[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (g->opt[i]->mux_opt == function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(pci->dev, "Pin %s does not support option %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) g->name, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (g->mux_reg_base == PALMAS_NONE_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (WARN_ON(i != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __func__, g->mux_reg_base, g->mux_reg_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) g->mux_reg_mask, i << g->mux_bit_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) g->mux_reg_mask, i << g->mux_bit_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) g->mux_reg_add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pci->pins_current_opt[group] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const struct pinmux_ops palmas_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .get_functions_count = palmas_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .get_function_name = palmas_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .get_function_groups = palmas_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .set_mux = palmas_pinctrl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) const struct palmas_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) const struct palmas_pin_info *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int base, add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int group_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (pci->pin_groups[group_nr].pins[0] == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (group_nr == pci->num_pin_groups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "Pinconf is not supported for pin-id %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) g = &pci->pin_groups[group_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) opt = g->opt[pci->pins_current_opt[group_nr]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!opt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "Pinconf is not supported for pin %s\n", g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!opt->pud_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "PULL control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) base = opt->pud_info->pullup_dn_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) add = opt->pud_info->pullup_dn_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = palmas_read(pci->palmas, base, add, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rval = val & opt->pud_info->pullup_dn_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if ((opt->pud_info->normal_val >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) (opt->pud_info->normal_val == rval) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) (param == PIN_CONFIG_BIAS_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else if ((opt->pud_info->pull_up_val >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) (opt->pud_info->pull_up_val == rval) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) (param == PIN_CONFIG_BIAS_PULL_UP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else if ((opt->pud_info->pull_dn_val >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) (opt->pud_info->pull_dn_val == rval) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) (param == PIN_CONFIG_BIAS_PULL_DOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!opt->od_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "OD control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) base = opt->od_info->od_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) add = opt->od_info->od_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = palmas_read(pci->palmas, base, add, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rval = val & opt->od_info->od_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) arg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if ((opt->od_info->od_disable >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (opt->od_info->od_disable == rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) else if ((opt->od_info->od_enable >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) (opt->od_info->od_enable == rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (arg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "OD control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const struct palmas_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) const struct palmas_pin_info *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int base, add, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int group_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (pci->pin_groups[group_nr].pins[0] == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (group_nr == pci->num_pin_groups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "Pinconf is not supported for pin-id %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) g = &pci->pin_groups[group_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) opt = g->opt[pci->pins_current_opt[group_nr]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!opt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "Pinconf is not supported for pin %s\n", g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) param_val = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (!opt->pud_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "PULL control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) base = opt->pud_info->pullup_dn_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) add = opt->pud_info->pullup_dn_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mask = opt->pud_info->pullup_dn_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (param == PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) rval = opt->pud_info->normal_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else if (param == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) rval = opt->pud_info->pull_up_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) rval = opt->pud_info->pull_dn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (rval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "PULL control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!opt->od_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "OD control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) base = opt->od_info->od_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) add = opt->od_info->od_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mask = opt->od_info->od_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (param_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) rval = opt->od_info->od_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) rval = opt->od_info->od_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (rval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_err(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "OD control not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) g->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_err(pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) __func__, base, add, mask, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) add, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct pinconf_ops palmas_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .pin_config_get = palmas_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .pin_config_set = palmas_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static struct pinctrl_desc palmas_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .pctlops = &palmas_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .pmxops = &palmas_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .confops = &palmas_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct palmas_pinctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) const struct palmas_pingroup *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static struct palmas_pinctrl_data tps65913_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .pin_groups = tps65913_pingroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct palmas_pinctrl_data tps80036_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .pin_groups = tps80036_pingroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct of_device_id palmas_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int palmas_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct palmas_pctrl_chip_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bool enable_dvfs1 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) bool enable_dvfs2 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pinctrl_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "ti,palmas-enable-dvfs1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "ti,palmas-enable-dvfs2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pci->palmas = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pci->pins = palmas_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pci->functions = palmas_pin_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pci->num_functions = ARRAY_SIZE(palmas_pin_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pci->pin_groups = pinctrl_data->pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pci->num_pin_groups = pinctrl_data->num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) platform_set_drvdata(pdev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = palmas_pinctrl_get_pin_mux(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "Reading pinctrol option register failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) palmas_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) palmas_pinctrl_desc.pins = palmas_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (IS_ERR(pci->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return PTR_ERR(pci->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static struct platform_driver palmas_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .name = "palmas-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .of_match_table = palmas_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .probe = palmas_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) module_platform_driver(palmas_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) MODULE_DESCRIPTION("Palmas pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MODULE_ALIAS("platform:palmas-pinctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags