^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Oxford Semiconductor OXNAS SoC Family pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on pinctrl-pic32.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Joshua Henderson, <joshua.henderson@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PINS_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* OX810 Regmap Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PINMUX_810_PRIMARY_SEL0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PINMUX_810_SECONDARY_SEL0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PINMUX_810_TERTIARY_SEL0 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PINMUX_810_PRIMARY_SEL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PINMUX_810_SECONDARY_SEL1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PINMUX_810_TERTIARY_SEL1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PINMUX_810_PULLUP_CTRL0 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PINMUX_810_PULLUP_CTRL1 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* OX820 Regmap Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PINMUX_820_BANK_OFFSET 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PINMUX_820_SECONDARY_SEL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PINMUX_820_TERTIARY_SEL 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PINMUX_820_QUATERNARY_SEL 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PINMUX_820_DEBUG_SEL 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PINMUX_820_ALTERNATIVE_SEL 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PINMUX_820_PULLUP_CTRL 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* GPIO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define INPUT_VALUE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OUTPUT_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_PENDING 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OUTPUT_SET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OUTPUT_CLEAR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OUTPUT_EN_SET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OUTPUT_EN_CLEAR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RE_IRQ_ENABLE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FE_IRQ_ENABLE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct oxnas_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct oxnas_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct oxnas_desc_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct oxnas_desc_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int fct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct oxnas_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct oxnas_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct oxnas_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct oxnas_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct oxnas_gpio_bank *gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct oxnas_pinctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pinctrl_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct oxnas_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(16, "gpio16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(17, "gpio17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(18, "gpio18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(19, "gpio19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(20, "gpio20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(21, "gpio21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(22, "gpio22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(23, "gpio23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(24, "gpio24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(25, "gpio25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(26, "gpio26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(27, "gpio27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(28, "gpio28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(29, "gpio29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(30, "gpio30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(31, "gpio31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(32, "gpio32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(33, "gpio33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(34, "gpio34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(16, "gpio16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(17, "gpio17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(18, "gpio18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(19, "gpio19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(20, "gpio20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(21, "gpio21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(22, "gpio22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(23, "gpio23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(24, "gpio24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(25, "gpio25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(26, "gpio26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(27, "gpio27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(28, "gpio28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(29, "gpio29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(30, "gpio30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(31, "gpio31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(32, "gpio32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(33, "gpio33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(34, "gpio34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(35, "gpio35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(36, "gpio36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(37, "gpio37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(38, "gpio38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(39, "gpio39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(40, "gpio40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(41, "gpio41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(42, "gpio42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(43, "gpio43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(44, "gpio44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(45, "gpio45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(46, "gpio46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(47, "gpio47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(48, "gpio48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(49, "gpio49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const oxnas_ox810se_fct0_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "gpio20", "gpio21", "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "gpio28", "gpio29", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "gpio32", "gpio33", "gpio34"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char * const oxnas_ox810se_fct3_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "gpio22", "gpio23", "gpio24", "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "gpio26", "gpio27", "gpio28", "gpio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "gpio30", "gpio31", "gpio32", "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "gpio34"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const char * const oxnas_ox820_fct0_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "gpio20", "gpio21", "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "gpio28", "gpio29", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "gpio36", "gpio37", "gpio38", "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "gpio40", "gpio41", "gpio42", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "gpio44", "gpio45", "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "gpio48", "gpio49"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const oxnas_ox820_fct1_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "gpio3", "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "gpio20", "gpio21", "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "gpio24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const oxnas_ox820_fct4_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "gpio5", "gpio6", "gpio7", "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "gpio40", "gpio41", "gpio42", "gpio43"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char * const oxnas_ox820_fct5_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "gpio28", "gpio29", "gpio30", "gpio31"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FUNCTION(_name, _gr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .groups = oxnas_##_gr##_group, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct oxnas_function oxnas_ox810se_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FUNCTION(gpio, ox810se_fct0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FUNCTION(fct3, ox810se_fct3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct oxnas_function oxnas_ox820_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FUNCTION(gpio, ox820_fct0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FUNCTION(fct1, ox820_fct1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FUNCTION(fct4, ox820_fct4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FUNCTION(fct5, ox820_fct5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .pin = _pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .bank = _pin / PINS_PER_BANK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .functions = (struct oxnas_desc_function[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __VA_ARGS__, { } }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OXNAS_PINCTRL_FUNCTION(_name, _fct) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .fct = _fct, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OXNAS_PINCTRL_GROUP(0, gpio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) OXNAS_PINCTRL_GROUP(1, gpio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) OXNAS_PINCTRL_GROUP(2, gpio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) OXNAS_PINCTRL_GROUP(3, gpio3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) OXNAS_PINCTRL_GROUP(4, gpio4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) OXNAS_PINCTRL_GROUP(5, gpio5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) OXNAS_PINCTRL_GROUP(6, gpio6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) OXNAS_PINCTRL_GROUP(7, gpio7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) OXNAS_PINCTRL_GROUP(8, gpio8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) OXNAS_PINCTRL_GROUP(9, gpio9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) OXNAS_PINCTRL_GROUP(10, gpio10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) OXNAS_PINCTRL_GROUP(11, gpio11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) OXNAS_PINCTRL_GROUP(12, gpio12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) OXNAS_PINCTRL_GROUP(13, gpio13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) OXNAS_PINCTRL_GROUP(14, gpio14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) OXNAS_PINCTRL_GROUP(15, gpio15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) OXNAS_PINCTRL_GROUP(16, gpio16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) OXNAS_PINCTRL_GROUP(17, gpio17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) OXNAS_PINCTRL_GROUP(18, gpio18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) OXNAS_PINCTRL_GROUP(19, gpio19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) OXNAS_PINCTRL_GROUP(20, gpio20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) OXNAS_PINCTRL_GROUP(21, gpio21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) OXNAS_PINCTRL_GROUP(22, gpio22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) OXNAS_PINCTRL_GROUP(23, gpio23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) OXNAS_PINCTRL_GROUP(24, gpio24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) OXNAS_PINCTRL_GROUP(25, gpio25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) OXNAS_PINCTRL_GROUP(26, gpio26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) OXNAS_PINCTRL_GROUP(27, gpio27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) OXNAS_PINCTRL_GROUP(28, gpio28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) OXNAS_PINCTRL_GROUP(29, gpio29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) OXNAS_PINCTRL_GROUP(30, gpio30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) OXNAS_PINCTRL_GROUP(31, gpio31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) OXNAS_PINCTRL_GROUP(32, gpio32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) OXNAS_PINCTRL_GROUP(33, gpio33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) OXNAS_PINCTRL_GROUP(34, gpio34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) OXNAS_PINCTRL_FUNCTION(fct3, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct oxnas_pin_group oxnas_ox820_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) OXNAS_PINCTRL_GROUP(0, gpio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) OXNAS_PINCTRL_GROUP(1, gpio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) OXNAS_PINCTRL_GROUP(2, gpio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) OXNAS_PINCTRL_GROUP(3, gpio3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) OXNAS_PINCTRL_GROUP(4, gpio4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OXNAS_PINCTRL_GROUP(5, gpio5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) OXNAS_PINCTRL_GROUP(6, gpio6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) OXNAS_PINCTRL_GROUP(7, gpio7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OXNAS_PINCTRL_GROUP(8, gpio8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) OXNAS_PINCTRL_GROUP(9, gpio9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) OXNAS_PINCTRL_GROUP(10, gpio10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) OXNAS_PINCTRL_GROUP(11, gpio11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) OXNAS_PINCTRL_GROUP(12, gpio12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) OXNAS_PINCTRL_GROUP(13, gpio13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) OXNAS_PINCTRL_GROUP(14, gpio14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) OXNAS_PINCTRL_GROUP(15, gpio15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) OXNAS_PINCTRL_GROUP(16, gpio16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) OXNAS_PINCTRL_GROUP(17, gpio17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) OXNAS_PINCTRL_GROUP(18, gpio18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) OXNAS_PINCTRL_GROUP(19, gpio19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) OXNAS_PINCTRL_GROUP(20, gpio20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) OXNAS_PINCTRL_GROUP(21, gpio21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) OXNAS_PINCTRL_GROUP(22, gpio22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) OXNAS_PINCTRL_GROUP(23, gpio23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) OXNAS_PINCTRL_FUNCTION(fct1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) OXNAS_PINCTRL_GROUP(24, gpio24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) OXNAS_PINCTRL_FUNCTION(fct1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) OXNAS_PINCTRL_FUNCTION(fct4, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) OXNAS_PINCTRL_GROUP(25, gpio25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) OXNAS_PINCTRL_GROUP(26, gpio26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) OXNAS_PINCTRL_GROUP(27, gpio27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) OXNAS_PINCTRL_GROUP(28, gpio28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OXNAS_PINCTRL_FUNCTION(fct5, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) OXNAS_PINCTRL_GROUP(29, gpio29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) OXNAS_PINCTRL_FUNCTION(fct5, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) OXNAS_PINCTRL_GROUP(30, gpio30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) OXNAS_PINCTRL_FUNCTION(fct5, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) OXNAS_PINCTRL_GROUP(31, gpio31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) OXNAS_PINCTRL_FUNCTION(fct5, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) OXNAS_PINCTRL_GROUP(32, gpio32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) OXNAS_PINCTRL_GROUP(33, gpio33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) OXNAS_PINCTRL_GROUP(34, gpio34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) OXNAS_PINCTRL_GROUP(35, gpio35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) OXNAS_PINCTRL_GROUP(36, gpio36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) OXNAS_PINCTRL_GROUP(37, gpio37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) OXNAS_PINCTRL_GROUP(38, gpio38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) OXNAS_PINCTRL_GROUP(39, gpio39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) OXNAS_PINCTRL_GROUP(40, gpio40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) OXNAS_PINCTRL_GROUP(41, gpio41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) OXNAS_PINCTRL_GROUP(42, gpio42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) OXNAS_PINCTRL_GROUP(43, gpio43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) OXNAS_PINCTRL_FUNCTION(gpio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) OXNAS_PINCTRL_FUNCTION(fct4, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) OXNAS_PINCTRL_GROUP(44, gpio44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) OXNAS_PINCTRL_GROUP(45, gpio45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) OXNAS_PINCTRL_GROUP(46, gpio46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) OXNAS_PINCTRL_GROUP(47, gpio47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) OXNAS_PINCTRL_GROUP(48, gpio48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) OXNAS_PINCTRL_GROUP(49, gpio49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) OXNAS_PINCTRL_FUNCTION(gpio, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return &pctl->gpio_banks[pin / PINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return pctl->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *pins = &pctl->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct pinctrl_ops oxnas_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .get_groups_count = oxnas_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .get_group_name = oxnas_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .get_group_pins = oxnas_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return pctl->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return pctl->functions[func].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *groups = pctl->functions[func].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *num_groups = pctl->functions[func].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int func, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) const struct oxnas_pin_group *pg = &pctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const struct oxnas_function *pf = &pctl->functions[func];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) const char *fname = pf->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct oxnas_desc_function *functions = pg->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 mask = BIT(pg->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) while (functions->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!strcmp(functions->name, fname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_dbg(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "setting function %s bank %d pin %d fct %d mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fname, pg->bank, pg->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) functions->fct, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) (pg->bank ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_810_PRIMARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_810_PRIMARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (functions->fct == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (pg->bank ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_810_SECONDARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_810_SECONDARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (functions->fct == 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (pg->bank ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_810_TERTIARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_810_TERTIARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) (functions->fct == 3 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) functions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int func, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const struct oxnas_pin_group *pg = &pctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const struct oxnas_function *pf = &pctl->functions[func];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) const char *fname = pf->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct oxnas_desc_function *functions = pg->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 mask = BIT(pg->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) while (functions->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!strcmp(functions->name, fname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_dbg(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "setting function %s bank %d pin %d fct %d mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fname, pg->bank, pg->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) functions->fct, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) offset + PINMUX_820_SECONDARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (functions->fct == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) offset + PINMUX_820_TERTIARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) (functions->fct == 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) offset + PINMUX_820_QUATERNARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) (functions->fct == 3 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) offset + PINMUX_820_DEBUG_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) (functions->fct == 4 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) offset + PINMUX_820_ALTERNATIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (functions->fct == 5 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mask : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) functions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 mask = BIT(offset - bank->gpio_chip.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) offset, bank->gpio_chip.base, bank->id, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) (bank->id ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_810_PRIMARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_810_PRIMARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) (bank->id ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_810_SECONDARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_810_SECONDARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (bank->id ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_810_TERTIARY_SEL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_810_TERTIARY_SEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 mask = BIT(offset - bank->gpio_chip.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) offset, bank->gpio_chip.base, bank->id, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) bank_offset + PINMUX_820_SECONDARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) bank_offset + PINMUX_820_TERTIARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) bank_offset + PINMUX_820_QUATERNARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bank_offset + PINMUX_820_DEBUG_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) bank_offset + PINMUX_820_ALTERNATIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int oxnas_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int oxnas_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int oxnas_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) oxnas_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct gpio_chip *chip = range->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) oxnas_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) oxnas_gpio_direction_output(chip, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .get_functions_count = oxnas_pinmux_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .get_function_name = oxnas_pinmux_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .get_function_groups = oxnas_pinmux_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .set_mux = oxnas_ox810se_pinmux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .gpio_set_direction = oxnas_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .get_functions_count = oxnas_pinmux_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .get_function_name = oxnas_pinmux_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .get_function_groups = oxnas_pinmux_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .set_mux = oxnas_ox820_pinmux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .gpio_request_enable = oxnas_ox820_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .gpio_set_direction = oxnas_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 mask = BIT(pin - bank->gpio_chip.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (bank->id ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_810_PULLUP_CTRL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_810_PULLUP_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) arg = !!(arg & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 mask = BIT(pin - bank->gpio_chip.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = regmap_read(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) bank_offset + PINMUX_820_PULLUP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) arg = !!(arg & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u32 offset = pin - bank->gpio_chip.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pin, bank->gpio_chip.base, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_dbg(pctl->dev, " pullup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (bank->id ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_810_PULLUP_CTRL1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_810_PULLUP_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(pctl->dev, "Property %u not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 offset = pin - bank->gpio_chip.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pin, bank->gpio_chip.base, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_dbg(pctl->dev, " pullup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) regmap_write_bits(pctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bank_offset + PINMUX_820_PULLUP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_err(pctl->dev, "Property %u not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .pin_config_get = oxnas_ox810se_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .pin_config_set = oxnas_ox810se_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .pin_config_get = oxnas_ox820_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .pin_config_set = oxnas_ox820_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static void oxnas_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writel(mask, bank->reg_base + IRQ_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static void oxnas_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned int type = irqd_get_trigger_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bank->reg_base + RE_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) bank->reg_base + FE_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static void oxnas_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) unsigned int type = irqd_get_trigger_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bank->reg_base + RE_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bank->reg_base + FE_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) oxnas_gpio_direction_input(chip, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) oxnas_gpio_irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void oxnas_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) stat = readl(bank->reg_base + IRQ_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) for_each_set_bit(pin, &stat, BITS_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define GPIO_BANK(_bank) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .gpio_chip = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .label = "GPIO" #_bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .request = gpiochip_generic_request, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .free = gpiochip_generic_free, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .get_direction = oxnas_gpio_get_direction, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .direction_input = oxnas_gpio_direction_input, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .direction_output = oxnas_gpio_direction_output, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .get = oxnas_gpio_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .set = oxnas_gpio_set, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .ngpio = PINS_PER_BANK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .base = GPIO_BANK_START(_bank), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .can_sleep = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .irq_chip = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .name = "GPIO" #_bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .irq_startup = oxnas_gpio_irq_startup, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .irq_ack = oxnas_gpio_irq_ack, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .irq_mask = oxnas_gpio_irq_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .irq_unmask = oxnas_gpio_irq_unmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .irq_set_type = oxnas_gpio_irq_set_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GPIO_BANK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GPIO_BANK(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static struct oxnas_pinctrl ox810se_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .functions = oxnas_ox810se_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .groups = oxnas_ox810se_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .gpio_banks = oxnas_gpio_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "oxnas-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .pins = oxnas_ox810se_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .npins = ARRAY_SIZE(oxnas_ox810se_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .pctlops = &oxnas_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .pmxops = &oxnas_ox810se_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .confops = &oxnas_ox810se_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct oxnas_pinctrl ox820_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .functions = oxnas_ox820_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .groups = oxnas_ox820_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .gpio_banks = oxnas_gpio_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "oxnas-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .pins = oxnas_ox820_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .npins = ARRAY_SIZE(oxnas_ox820_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .pctlops = &oxnas_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .pmxops = &oxnas_ox820_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .confops = &oxnas_ox820_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .desc = &oxnas_ox810se_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .pctl = &ox810se_pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .desc = &oxnas_ox820_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .pctl = &ox820_pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const struct of_device_id oxnas_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) { .compatible = "oxsemi,ox810se-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .data = &oxnas_ox810se_pinctrl_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { .compatible = "oxsemi,ox820-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .data = &oxnas_ox820_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int oxnas_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) const struct oxnas_pinctrl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct oxnas_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) data = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!data || !data->pctl || !data->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dev_set_drvdata(&pdev->dev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "oxsemi,sys-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (IS_ERR(pctl->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pctl->functions = data->pctl->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pctl->nfunctions = data->pctl->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pctl->groups = data->pctl->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pctl->ngroups = data->pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pctl->gpio_banks = data->pctl->gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pctl->nbanks = data->pctl->nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (IS_ERR(pctl->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_err(&pdev->dev, "Failed to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return PTR_ERR(pctl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int oxnas_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct of_phandle_args pinspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct oxnas_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) unsigned int id, ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) 3, 0, &pinspec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dev_err(&pdev->dev, "gpio-ranges property not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) id = pinspec.args[1] / PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ngpios = pinspec.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ngpios > PINS_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bank = &oxnas_gpio_banks[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (IS_ERR(bank->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return PTR_ERR(bank->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) bank->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) bank->gpio_chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) bank->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) bank->gpio_chip.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) girq = &bank->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) girq->chip = &bank->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) girq->parent_handler = oxnas_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = gpiochip_add_data(&bank->gpio_chip, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static struct platform_driver oxnas_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .name = "oxnas-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .of_match_table = oxnas_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .probe = oxnas_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static const struct of_device_id oxnas_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { .compatible = "oxsemi,ox810se-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { .compatible = "oxsemi,ox820-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static struct platform_driver oxnas_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .name = "oxnas-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .of_match_table = oxnas_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .probe = oxnas_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int __init oxnas_gpio_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return platform_driver_register(&oxnas_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) arch_initcall(oxnas_gpio_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static int __init oxnas_pinctrl_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return platform_driver_register(&oxnas_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) arch_initcall(oxnas_pinctrl_register);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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