^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi SoCs pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: <alexandre.belloni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License: Dual MIT/GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ocelot_clrsetbits(addr, clear, set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) writel((readl(addr) & ~(clear)) | (set), (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PINCONFIG bits (sparx5 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINCONF_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCONF_SCHMITT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINCONF_DRIVE_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BIAS_PD_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BIAS_PU_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCHMITT_BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVE_BITS GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* GPIO standard registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OCELOT_GPIO_OUT_SET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OCELOT_GPIO_OUT_CLR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OCELOT_GPIO_OUT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OCELOT_GPIO_IN 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OCELOT_GPIO_OE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OCELOT_GPIO_INTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OCELOT_GPIO_INTR_ENA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OCELOT_GPIO_INTR_IDENT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OCELOT_GPIO_ALT0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OCELOT_GPIO_ALT1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OCELOT_GPIO_SD_MAP 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OCELOT_FUNC_PER_PIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FUNC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FUNC_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FUNC_IRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FUNC_IRQ0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FUNC_IRQ0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FUNC_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FUNC_IRQ1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FUNC_IRQ1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FUNC_EXT_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FUNC_MIIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FUNC_PHY_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FUNC_PCI_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FUNC_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FUNC_PTP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FUNC_PTP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FUNC_PTP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FUNC_PTP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FUNC_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FUNC_RECO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FUNC_SFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FUNC_SG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FUNC_SG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FUNC_SG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FUNC_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FUNC_SI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FUNC_TACHO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FUNC_TWI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FUNC_TWI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FUNC_TWI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FUNC_TWI_SCL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FUNC_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FUNC_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FUNC_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FUNC_PLL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FUNC_EMMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FUNC_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FUNC_RCVRD_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FUNC_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char *const ocelot_function_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [FUNC_NONE] = "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [FUNC_GPIO] = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [FUNC_IRQ0] = "irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [FUNC_IRQ0_IN] = "irq0_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [FUNC_IRQ0_OUT] = "irq0_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [FUNC_IRQ1] = "irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [FUNC_IRQ1_IN] = "irq1_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [FUNC_IRQ1_OUT] = "irq1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [FUNC_EXT_IRQ] = "ext_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [FUNC_MIIM] = "miim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [FUNC_PHY_LED] = "phy_led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [FUNC_PCI_WAKE] = "pci_wake",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [FUNC_MD] = "md",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [FUNC_PTP0] = "ptp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [FUNC_PTP1] = "ptp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [FUNC_PTP2] = "ptp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [FUNC_PTP3] = "ptp3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [FUNC_PWM] = "pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [FUNC_RECO_CLK] = "reco_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [FUNC_SFP] = "sfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [FUNC_SG0] = "sg0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [FUNC_SG1] = "sg1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [FUNC_SG2] = "sg2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [FUNC_SI] = "si",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [FUNC_SI2] = "si2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [FUNC_TACHO] = "tacho",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [FUNC_TWI] = "twi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [FUNC_TWI2] = "twi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [FUNC_TWI3] = "twi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [FUNC_TWI_SCL_M] = "twi_scl_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [FUNC_UART] = "uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [FUNC_UART2] = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [FUNC_UART3] = "uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [FUNC_PLL_STAT] = "pll_stat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [FUNC_EMMC] = "emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [FUNC_REF_CLK] = "ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [FUNC_RCVRD_CLK] = "rcvrd_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ocelot_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ocelot_pin_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char functions[OCELOT_FUNC_PER_PIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ocelot_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *pincfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ocelot_pmx_func func[FUNC_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OCELOT_P(p, f0, f1, f2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct ocelot_pin_caps ocelot_pin_##p = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pin = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .functions = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OCELOT_P(0, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) OCELOT_P(1, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) OCELOT_P(2, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) OCELOT_P(3, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) OCELOT_P(6, UART, TWI_SCL_M, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) OCELOT_P(7, UART, TWI_SCL_M, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) OCELOT_P(12, UART2, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OCELOT_P(13, UART2, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) OCELOT_P(16, TWI, NONE, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) OCELOT_P(17, TWI, TWI_SCL_M, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OCELOT_PIN(n) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .number = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "GPIO_"#n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .drv_data = &ocelot_pin_##n \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct pinctrl_pin_desc ocelot_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) OCELOT_PIN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) OCELOT_PIN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) OCELOT_PIN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) OCELOT_PIN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) OCELOT_PIN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) OCELOT_PIN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) OCELOT_PIN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) OCELOT_PIN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) OCELOT_PIN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) OCELOT_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) OCELOT_PIN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) OCELOT_PIN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) OCELOT_PIN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) OCELOT_PIN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) OCELOT_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) OCELOT_PIN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) OCELOT_PIN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) OCELOT_PIN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) OCELOT_PIN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) OCELOT_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) OCELOT_PIN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) OCELOT_PIN(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define JAGUAR2_P(p, f0, f1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct ocelot_pin_caps jaguar2_pin_##p = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .pin = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .functions = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) JAGUAR2_P(0, SG0, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) JAGUAR2_P(1, SG0, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) JAGUAR2_P(2, SG0, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) JAGUAR2_P(3, SG0, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) JAGUAR2_P(4, SG1, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) JAGUAR2_P(5, SG1, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) JAGUAR2_P(8, PTP0, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) JAGUAR2_P(9, PTP1, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) JAGUAR2_P(10, UART, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) JAGUAR2_P(11, UART, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) JAGUAR2_P(12, SG1, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) JAGUAR2_P(13, SG1, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) JAGUAR2_P(14, TWI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) JAGUAR2_P(15, TWI, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) JAGUAR2_P(16, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) JAGUAR2_P(17, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) JAGUAR2_P(18, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) JAGUAR2_P(19, PCI_WAKE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) JAGUAR2_P(22, TACHO, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) JAGUAR2_P(23, PWM, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) JAGUAR2_P(24, UART2, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) JAGUAR2_P(25, UART2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) JAGUAR2_P(26, PTP2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) JAGUAR2_P(27, PTP3, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) JAGUAR2_P(28, TWI2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) JAGUAR2_P(29, TWI2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) JAGUAR2_P(30, SG2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) JAGUAR2_P(31, SG2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) JAGUAR2_P(32, SG2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) JAGUAR2_P(33, SG2, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) JAGUAR2_P(34, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) JAGUAR2_P(35, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) JAGUAR2_P(36, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) JAGUAR2_P(37, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) JAGUAR2_P(38, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) JAGUAR2_P(39, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) JAGUAR2_P(40, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) JAGUAR2_P(41, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) JAGUAR2_P(42, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) JAGUAR2_P(43, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) JAGUAR2_P(44, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) JAGUAR2_P(45, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) JAGUAR2_P(46, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) JAGUAR2_P(47, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) JAGUAR2_P(48, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) JAGUAR2_P(49, SFP, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) JAGUAR2_P(50, SFP, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) JAGUAR2_P(51, SFP, SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) JAGUAR2_P(52, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) JAGUAR2_P(53, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) JAGUAR2_P(54, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) JAGUAR2_P(55, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) JAGUAR2_P(56, MIIM, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) JAGUAR2_P(57, MIIM, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) JAGUAR2_P(58, MIIM, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) JAGUAR2_P(59, MIIM, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) JAGUAR2_P(60, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) JAGUAR2_P(61, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) JAGUAR2_P(62, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) JAGUAR2_P(63, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define JAGUAR2_PIN(n) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .number = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "GPIO_"#n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .drv_data = &jaguar2_pin_##n \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct pinctrl_pin_desc jaguar2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) JAGUAR2_PIN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) JAGUAR2_PIN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) JAGUAR2_PIN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) JAGUAR2_PIN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) JAGUAR2_PIN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) JAGUAR2_PIN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) JAGUAR2_PIN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) JAGUAR2_PIN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) JAGUAR2_PIN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) JAGUAR2_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) JAGUAR2_PIN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) JAGUAR2_PIN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) JAGUAR2_PIN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) JAGUAR2_PIN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) JAGUAR2_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) JAGUAR2_PIN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) JAGUAR2_PIN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) JAGUAR2_PIN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) JAGUAR2_PIN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) JAGUAR2_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) JAGUAR2_PIN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) JAGUAR2_PIN(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) JAGUAR2_PIN(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) JAGUAR2_PIN(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) JAGUAR2_PIN(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) JAGUAR2_PIN(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) JAGUAR2_PIN(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) JAGUAR2_PIN(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) JAGUAR2_PIN(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) JAGUAR2_PIN(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) JAGUAR2_PIN(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) JAGUAR2_PIN(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) JAGUAR2_PIN(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) JAGUAR2_PIN(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) JAGUAR2_PIN(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) JAGUAR2_PIN(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) JAGUAR2_PIN(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) JAGUAR2_PIN(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) JAGUAR2_PIN(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) JAGUAR2_PIN(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) JAGUAR2_PIN(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) JAGUAR2_PIN(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) JAGUAR2_PIN(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) JAGUAR2_PIN(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) JAGUAR2_PIN(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) JAGUAR2_PIN(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) JAGUAR2_PIN(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) JAGUAR2_PIN(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) JAGUAR2_PIN(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) JAGUAR2_PIN(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) JAGUAR2_PIN(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) JAGUAR2_PIN(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) JAGUAR2_PIN(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) JAGUAR2_PIN(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) JAGUAR2_PIN(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) JAGUAR2_PIN(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) JAGUAR2_PIN(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) JAGUAR2_PIN(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) JAGUAR2_PIN(58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) JAGUAR2_PIN(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) JAGUAR2_PIN(60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) JAGUAR2_PIN(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) JAGUAR2_PIN(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) JAGUAR2_PIN(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SPARX5_P(p, f0, f1, f2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct ocelot_pin_caps sparx5_pin_##p = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .pin = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .functions = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SPARX5_P(0, SG0, PLL_STAT, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SPARX5_P(1, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SPARX5_P(2, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SPARX5_P(3, SG0, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SPARX5_P(4, SG1, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SPARX5_P(5, SG1, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SPARX5_P(8, PTP0, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SPARX5_P(10, UART, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SPARX5_P(11, UART, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SPARX5_P(12, SG1, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SPARX5_P(13, SG1, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SPARX5_P(14, TWI, TWI_SCL_M, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SPARX5_P(15, TWI, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) SPARX5_P(16, SI, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) SPARX5_P(17, SI, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SPARX5_P(18, SI, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SPARX5_P(23, PWM, UART3, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SPARX5_P(25, PTP3, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SPARX5_P(26, UART2, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SPARX5_P(27, UART2, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SPARX5_P(28, TWI2, SI, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SPARX5_P(29, TWI2, SI, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SPARX5_P(30, SG2, SI, PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SPARX5_P(31, SG2, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SPARX5_P(32, SG2, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SPARX5_P(33, SG2, SI, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SPARX5_P(37, SFP, NONE, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SPARX5_P(44, SI, SFP, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SPARX5_P(45, SI, SFP, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SPARX5_P(46, NONE, SFP, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SPARX5_P(47, NONE, SFP, EMMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SPARX5_P(48, TWI3, SI, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SPARX5_P(49, TWI3, NONE, SFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SPARX5_P(50, SFP, NONE, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SPARX5_P(51, SFP, SI, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) SPARX5_P(55, SFP, PTP3, PCI_WAKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SPARX5_P(59, MIIM, SFP, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SPARX5_P(60, RECO_CLK, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SPARX5_P(61, RECO_CLK, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SPARX5_P(63, RECO_CLK, NONE, NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SPARX5_PIN(n) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .number = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "GPIO_"#n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .drv_data = &sparx5_pin_##n \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct pinctrl_pin_desc sparx5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SPARX5_PIN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SPARX5_PIN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SPARX5_PIN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SPARX5_PIN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SPARX5_PIN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SPARX5_PIN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SPARX5_PIN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SPARX5_PIN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SPARX5_PIN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SPARX5_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SPARX5_PIN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SPARX5_PIN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SPARX5_PIN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SPARX5_PIN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SPARX5_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SPARX5_PIN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SPARX5_PIN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SPARX5_PIN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SPARX5_PIN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SPARX5_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SPARX5_PIN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) SPARX5_PIN(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SPARX5_PIN(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SPARX5_PIN(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SPARX5_PIN(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SPARX5_PIN(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SPARX5_PIN(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SPARX5_PIN(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SPARX5_PIN(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SPARX5_PIN(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SPARX5_PIN(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SPARX5_PIN(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SPARX5_PIN(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SPARX5_PIN(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SPARX5_PIN(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SPARX5_PIN(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SPARX5_PIN(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SPARX5_PIN(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SPARX5_PIN(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SPARX5_PIN(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SPARX5_PIN(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) SPARX5_PIN(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SPARX5_PIN(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SPARX5_PIN(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SPARX5_PIN(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SPARX5_PIN(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SPARX5_PIN(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SPARX5_PIN(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SPARX5_PIN(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SPARX5_PIN(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SPARX5_PIN(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SPARX5_PIN(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SPARX5_PIN(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SPARX5_PIN(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SPARX5_PIN(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SPARX5_PIN(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SPARX5_PIN(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SPARX5_PIN(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SPARX5_PIN(58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SPARX5_PIN(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SPARX5_PIN(60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SPARX5_PIN(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SPARX5_PIN(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SPARX5_PIN(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ARRAY_SIZE(ocelot_function_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ocelot_function_names[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned *const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *groups = info->func[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *num_groups = info->func[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int pin, unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (function == p->functions[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int selector, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int p = pin->pin % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) f = ocelot_pin_function_idx(info, group, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (f < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * f is encoded on two bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * ALT[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * This is racy because both registers can't be updated at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * but it doesn't matter much for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Note: ALT0/ALT1 are organized specially for 64 gpio targets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) BIT(p), f << p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) BIT(p), f << (p - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int pin, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int p = pin % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) input ? 0 : BIT(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int p = offset % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regmap_update_bits(info->map, REG_ALT(0, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) BIT(p), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regmap_update_bits(info->map, REG_ALT(1, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) BIT(p), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct pinmux_ops ocelot_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .get_functions_count = ocelot_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .get_function_name = ocelot_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .get_function_groups = ocelot_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .set_mux = ocelot_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .gpio_set_direction = ocelot_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .gpio_request_enable = ocelot_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return info->desc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return info->desc->pins[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *pins = &info->desc->pins[group].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (info->pincfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case PINCONF_BIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *val = regcfg & BIAS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case PINCONF_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *val = regcfg & SCHMITT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case PINCONF_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *val = regcfg & DRIVE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (info->pincfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case PINCONF_BIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ocelot_clrsetbits(regaddr, BIAS_BITS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case PINCONF_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case PINCONF_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (val <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int val, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (param == PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) val = (val == 0 ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) val = (val & BIAS_PD_BIT ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else /* PIN_CONFIG_BIAS_PULL_UP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val = (val & BIAS_PU_BIT ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val = (val & SCHMITT_BIT ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val = !!(val & BIT(pin % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) val = val & BIT(pin % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (param == PIN_CONFIG_OUTPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) val = !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *config = pinconf_to_config_packed(param, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 param, arg, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int cfg, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (cfg = 0; cfg < num_configs; cfg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) param = pinconf_to_config_param(configs[cfg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) arg = pinconf_to_config_argument(configs[cfg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) BIAS_PD_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) arg = arg ? SCHMITT_BIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) err = ocelot_hw_set_value(info, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINCONF_DRIVE_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) p = pin % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) regmap_write(info->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) REG(OCELOT_GPIO_OUT_SET, info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) BIT(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) regmap_write(info->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) REG(OCELOT_GPIO_OUT_CLR, info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) BIT(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) regmap_update_bits(info->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) REG(OCELOT_GPIO_OE, info, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) BIT(p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) param == PIN_CONFIG_INPUT_ENABLE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 0 : BIT(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const struct pinconf_ops ocelot_confops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .pin_config_get = ocelot_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .pin_config_set = ocelot_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct pinctrl_ops ocelot_pctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .get_groups_count = ocelot_pctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .get_group_name = ocelot_pctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .get_group_pins = ocelot_pctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static struct pinctrl_desc ocelot_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .name = "ocelot-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .pins = ocelot_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .npins = ARRAY_SIZE(ocelot_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .pctlops = &ocelot_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .pmxops = &ocelot_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct pinctrl_desc jaguar2_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .name = "jaguar2-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .pins = jaguar2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .npins = ARRAY_SIZE(jaguar2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .pctlops = &ocelot_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .pmxops = &ocelot_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct pinctrl_desc sparx5_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "sparx5-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .pins = sparx5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .npins = ARRAY_SIZE(sparx5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .pctlops = &ocelot_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .pmxops = &ocelot_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .confops = &ocelot_confops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int ocelot_create_group_func_map(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct ocelot_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int f, npins, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) for (f = 0; f < FUNC_MAX; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) for (npins = 0, i = 0; i < info->desc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ocelot_pin_function_idx(info, i, f) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pins[npins++] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) info->func[f].ngroups = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!info->func[f].groups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) kfree(pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) for (i = 0; i < npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) info->func[f].groups[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) info->desc->pins[pins[i]].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) kfree(pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int ocelot_pinctrl_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct ocelot_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret = ocelot_create_group_func_map(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_err(&pdev->dev, "Unable to create group func map.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (IS_ERR(info->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(&pdev->dev, "Failed to register pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return PTR_ERR(info->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return !!(val & BIT(offset % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) BIT(offset % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) BIT(offset % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int ocelot_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (val & BIT(offset % 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int ocelot_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int ocelot_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned int pin = BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const struct gpio_chip ocelot_gpiolib_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .set = ocelot_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .get = ocelot_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .get_direction = ocelot_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .direction_input = ocelot_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .direction_output = ocelot_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static void ocelot_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned int gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) BIT(gpio % 32), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static void ocelot_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned int gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) BIT(gpio % 32), BIT(gpio % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void ocelot_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) unsigned int gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) BIT(gpio % 32), BIT(gpio % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static struct irq_chip ocelot_eoi_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .irq_mask = ocelot_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .irq_eoi = ocelot_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .irq_unmask = ocelot_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .irq_set_type = ocelot_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static struct irq_chip ocelot_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .irq_mask = ocelot_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .irq_ack = ocelot_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .irq_unmask = ocelot_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .irq_set_type = ocelot_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) type &= IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (type & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) handle_fasteoi_irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) handle_edge_irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void ocelot_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct irq_chip *parent_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct ocelot_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) unsigned int reg = 0, irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) unsigned long irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) for (i = 0; i < info->stride; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) regmap_read(info->map, id_reg + 4 * i, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) chained_irq_enter(parent_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) irqs = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) for_each_set_bit(irq, &irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) min(32U, info->desc->npins - 32 * i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) generic_handle_irq(irq_linear_revmap(chip->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) irq + 32 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) chained_irq_exit(parent_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static int ocelot_gpiochip_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct ocelot_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) info->gpio_chip = ocelot_gpiolib_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) gc = &info->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) gc->ngpio = info->desc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) gc->base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) gc->of_node = info->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) gc->label = "ocelot-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) irq = irq_of_parse_and_map(gc->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) girq->chip = &ocelot_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) girq->parent_handler = ocelot_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return devm_gpiochip_add_data(&pdev->dev, gc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const struct of_device_id ocelot_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int ocelot_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct ocelot_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) base = devm_ioremap_resource(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) platform_get_resource(pdev, IORESOURCE_MEM, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_err(dev, "Failed to ioremap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) info->stride = 1 + (info->desc->npins - 1) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) info->map = devm_regmap_init_mmio(dev, base, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (IS_ERR(info->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_err(dev, "Failed to create regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return PTR_ERR(info->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_set_drvdata(dev, info->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Pinconf registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (info->desc->confops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) info->pincfg = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = ocelot_pinctrl_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = ocelot_gpiochip_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_info(dev, "driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct platform_driver ocelot_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .name = "pinctrl-ocelot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .probe = ocelot_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) builtin_platform_driver(ocelot_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags