^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* MCP23S08 SPI/I2C GPIO driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinctrl-mcp23s08.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Registers are all 8 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * The mcp23s17 has twice as many bits, and can be configured to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * with either 16 bit registers or with two adjacent 8 bit banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCP_IODIR 0x00 /* init/reset: all ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCP_IPOL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCP_GPINTEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCP_DEFVAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCP_INTCON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCP_IOCON 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define IOCON_MIRROR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define IOCON_SEQOP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define IOCON_HAEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define IOCON_ODR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define IOCON_INTPOL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define IOCON_INTCC (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCP_GPPU 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCP_INTF 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCP_INTCAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCP_GPIO 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCP_OLAT 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct reg_default mcp23x08_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {.reg = MCP_IODIR, .def = 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {.reg = MCP_IPOL, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {.reg = MCP_GPINTEN, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {.reg = MCP_DEFVAL, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {.reg = MCP_INTCON, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {.reg = MCP_IOCON, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {.reg = MCP_GPPU, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {.reg = MCP_OLAT, .def = 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct regmap_range mcp23x08_volatile_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .range_min = MCP_INTF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .range_max = MCP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct regmap_access_table mcp23x08_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .yes_ranges = &mcp23x08_volatile_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .n_yes_ranges = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct regmap_range mcp23x08_precious_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .range_min = MCP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .range_max = MCP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct regmap_access_table mcp23x08_precious_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .yes_ranges = &mcp23x08_precious_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .n_yes_ranges = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct regmap_config mcp23x08_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .volatile_table = &mcp23x08_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .precious_table = &mcp23x08_precious_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg_defaults = mcp23x08_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .max_register = MCP_OLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) EXPORT_SYMBOL_GPL(mcp23x08_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct reg_default mcp23x17_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {.reg = MCP_IODIR << 1, .def = 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {.reg = MCP_IPOL << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {.reg = MCP_GPINTEN << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {.reg = MCP_DEFVAL << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {.reg = MCP_INTCON << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {.reg = MCP_IOCON << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {.reg = MCP_GPPU << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {.reg = MCP_OLAT << 1, .def = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct regmap_range mcp23x17_volatile_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .range_min = MCP_INTF << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .range_max = MCP_GPIO << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct regmap_access_table mcp23x17_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .yes_ranges = &mcp23x17_volatile_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .n_yes_ranges = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct regmap_range mcp23x17_precious_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .range_min = MCP_INTCAP << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .range_max = MCP_GPIO << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct regmap_access_table mcp23x17_precious_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .yes_ranges = &mcp23x17_precious_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .n_yes_ranges = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct regmap_config mcp23x17_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .max_register = MCP_OLAT << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .volatile_table = &mcp23x17_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .precious_table = &mcp23x17_precious_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .reg_defaults = mcp23x17_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) EXPORT_SYMBOL_GPL(mcp23x17_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int mask, bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 val = enabled ? 0xffff : 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int pin, bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 mask = BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return mcp_set_mask(mcp, reg, mask, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct pinctrl_pin_desc mcp23x08_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct pinctrl_pin_desc mcp23x17_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct pinctrl_ops mcp_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .get_groups_count = mcp_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .get_group_name = mcp_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .get_group_pins = mcp_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int data, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = mcp_read(mcp, MCP_GPPU, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) status = (data & BIT(pin)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return status ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct pinconf_ops mcp_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .pin_config_get = mcp_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .pin_config_set = mcp_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct mcp23s08 *mcp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct mcp23s08 *mcp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int status, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* REVISIT reading this clears any IRQ ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = mcp_read(mcp, MCP_GPIO, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mcp->cached_gpio = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) status = !!(status & (1 << offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return mcp_set_mask(mcp, MCP_OLAT, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mcp23s08 *mcp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __mcp23s08_set(mcp, mask, !!value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct mcp23s08 *mcp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) status = __mcp23s08_set(mcp, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static irqreturn_t mcp23s08_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct mcp23s08 *mcp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int child_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool intf_set, intcap_changed, gpio_bit_changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) defval_changed, gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (mcp_read(mcp, MCP_INTF, &intf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (intf == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* There is no interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (mcp_read(mcp, MCP_INTCAP, &intcap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (mcp_read(mcp, MCP_INTCON, &intcon))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (mcp_read(mcp, MCP_DEFVAL, &defval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* This clears the interrupt(configurable on S18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (mcp_read(mcp, MCP_GPIO, &gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gpio_orig = mcp->cached_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mcp->cached_gpio = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_dbg(mcp->chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) intcap, intf, gpio_orig, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) for (i = 0; i < mcp->chip.ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* We must check all of the inputs on the chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * otherwise we may not notice a change on >=2 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * On at least the mcp23s17, INTCAP is only updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * one byte at a time(INTCAPA and INTCAPB are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * not written to at the same time - only on a per-bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * basis).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * INTF only contains the single bit that caused the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * interrupt per-bank. On the mcp23s17, there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * INTFA and INTFB. If two pins are changed on the A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * side at the same time, INTF will only have one bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * set. If one pin on the A side and one pin on the B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * side are changed at the same time, INTF will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * two bits set. Thus, INTF can't be the only check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * to see if the input has changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) intf_set = intf & BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (i < 8 && intf_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) intcap_mask = 0x00FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) else if (i >= 8 && intf_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) intcap_mask = 0xFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) intcap_mask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) intcap_changed = (intcap_mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (intcap & BIT(i))) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (intcap_mask & (BIT(i) & gpio_orig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gpio_set = BIT(i) & gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) gpio_bit_changed = (BIT(i) & gpio_orig) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (BIT(i) & gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) defval_changed = (BIT(i) & intcon) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ((BIT(i) & gpio) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) (BIT(i) & defval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (((gpio_bit_changed || intcap_changed) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (BIT(i) & mcp->irq_rise) && gpio_set) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ((gpio_bit_changed || intcap_changed) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (BIT(i) & mcp->irq_fall) && !gpio_set) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) defval_changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) handle_nested_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void mcp23s08_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct mcp23s08 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int pos = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void mcp23s08_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct mcp23s08 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int pos = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct mcp23s08 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int pos = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mcp_set_bit(mcp, MCP_INTCON, pos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mcp->irq_rise |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mcp->irq_fall |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else if (type & IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mcp_set_bit(mcp, MCP_INTCON, pos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mcp->irq_rise |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mcp->irq_fall &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else if (type & IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mcp_set_bit(mcp, MCP_INTCON, pos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mcp->irq_rise &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mcp->irq_fall |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else if (type & IRQ_TYPE_LEVEL_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mcp_set_bit(mcp, MCP_INTCON, pos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else if (type & IRQ_TYPE_LEVEL_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mcp_set_bit(mcp, MCP_INTCON, pos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void mcp23s08_irq_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct mcp23s08 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regcache_cache_only(mcp->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void mcp23s08_irq_bus_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct mcp23s08 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) regcache_cache_only(mcp->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) regcache_sync(mcp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct gpio_chip *chip = &mcp->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (mcp->irq_active_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) irqflags |= IRQF_TRIGGER_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) irqflags |= IRQF_TRIGGER_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mcp23s08_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) irqflags, dev_name(chip->parent), mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mcp->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int addr, unsigned int type, unsigned int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int status, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bool mirror = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bool open_drain = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mutex_init(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mcp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mcp->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mcp->irq_active_high = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mcp->irq_chip.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mcp->chip.direction_input = mcp23s08_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mcp->chip.get = mcp23s08_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mcp->chip.direction_output = mcp23s08_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mcp->chip.set = mcp23s08_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mcp->chip.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mcp->chip.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mcp->chip.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mcp->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mcp->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mcp->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * and MCP_IOCON.HAEN = 1, so we work with all chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = mcp_read(mcp, MCP_IOCON, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mcp->irq_controller =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) device_property_read_bool(dev, "interrupt-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (mcp->irq && mcp->irq_controller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mcp->irq_active_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) device_property_read_bool(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "microchip,irq-active-high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mirror = device_property_read_bool(dev, "microchip,irq-mirror");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) open_drain = device_property_read_bool(dev, "drive-open-drain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mcp->irq_active_high || open_drain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* mcp23s17 has IOCON twice, make sure they are in sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) status |= IOCON_HAEN | (IOCON_HAEN << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (mcp->irq_active_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (mirror)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (open_drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) status |= IOCON_ODR | (IOCON_ODR << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) status |= IOCON_INTCC | (IOCON_INTCC << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = mcp_write(mcp, MCP_IOCON, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (mcp->irq && mcp->irq_controller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct gpio_irq_chip *girq = &mcp->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) girq->chip = &mcp->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return dev_err_probe(dev, ret, "can't add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mcp->pinctrl_desc.npins = mcp->chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (mcp->pinctrl_desc.npins == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mcp->pinctrl_desc.pins = mcp23x08_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else if (mcp->pinctrl_desc.npins == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mcp->pinctrl_desc.pins = mcp23x17_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mcp->pinctrl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (IS_ERR(mcp->pctldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (mcp->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = mcp23s08_irq_setup(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return dev_err_probe(dev, ret, "can't setup IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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