^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim max96755f pin control driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/max96755f.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct max96755f_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct config_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct max96755f_group_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct config_desc *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct max96755f_function_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 gpio_out_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 gpio_tx_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 gpio_rx_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 gpio_tx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 gpio_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int max96755f_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int function, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) func = pinmux_generic_get_function(pctldev, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (func->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct max96755f_function_data *fdata = func->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regmap_update_bits(mpctl->regmap, GPIO_A_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (fdata->gpio_tx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regmap_update_bits(mpctl->regmap, GPIO_B_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GPIO_TX_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (fdata->gpio_rx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_update_bits(mpctl->regmap, GPIO_C_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GPIO_RX_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (grp->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct max96755f_group_data *gdata = grp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) for (i = 0; i < gdata->num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct config_desc *config = &gdata->configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_update_bits(mpctl->regmap, config->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) config->mask, config->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_info(mpctl->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int max96755f_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int gpio_a_reg, gpio_b_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) regmap_read(mpctl->regmap, GPIO_A_REG(pin), &gpio_a_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_read(mpctl->regmap, GPIO_B_REG(pin), &gpio_b_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (FIELD_GET(OUT_TYPE, gpio_b_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) arg = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) arg = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) arg = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) arg = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int max96755f_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 res_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PULL_UPDN_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FIELD_PREP(PULL_UPDN_SEL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case 40000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) res_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case 1000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) res_cfg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PULL_UPDN_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FIELD_PREP(PULL_UPDN_SEL, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case 40000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) res_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case 1000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) res_cfg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PULL_UPDN_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FIELD_PREP(PULL_UPDN_SEL, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GPIO_OUT_DIS | GPIO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FIELD_PREP(GPIO_OUT_DIS, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FIELD_PREP(GPIO_OUT, arg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct pinconf_ops max96755f_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .pin_config_get = max96755f_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .pin_config_set = max96755f_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct pinmux_ops max96755f_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .set_mux = max96755f_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct pinctrl_ops max96755f_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct pinctrl_pin_desc max96755f_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(16, "gpio16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(17, "gpio17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(18, "gpio18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(19, "gpio19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(20, "gpio20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int gpio0_pins[] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int gpio1_pins[] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int gpio2_pins[] = {2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int gpio3_pins[] = {3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int gpio4_pins[] = {4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int gpio5_pins[] = {5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int gpio6_pins[] = {6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int gpio7_pins[] = {7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int gpio8_pins[] = {8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int gpio9_pins[] = {9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int gpio10_pins[] = {10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int gpio11_pins[] = {11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int gpio12_pins[] = {12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int gpio13_pins[] = {13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int gpio14_pins[] = {14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int gpio15_pins[] = {15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int gpio16_pins[] = {16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int gpio17_pins[] = {17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int gpio18_pins[] = {18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int gpio19_pins[] = {19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int gpio20_pins[] = {20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int i2c_pins[] = {19, 20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int uart_pins[] = {19, 20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GROUP_DESC(nm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = #nm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pins = nm ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_pins = ARRAY_SIZE(nm ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GROUP_DESC_CONFIG(nm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = #nm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .pins = nm ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_pins = ARRAY_SIZE(nm ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .data = (void *)(const struct max96755f_group_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .configs = nm ## _configs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .num_configs = ARRAY_SIZE(nm ## _configs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct config_desc gpio0_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x0005, LOCK_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x0048, LOC_MS_EN, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct config_desc gpio1_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x0005, ERRB_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct config_desc gpio4_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x070, SPI_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct config_desc gpio5_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x006, RCLKEN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct config_desc gpio7_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0x0002, AUD_TX_EN_X, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x0002, AUD_TX_EN_Y, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct config_desc gpio8_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x0002, AUD_TX_EN_X, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x0002, AUD_TX_EN_Y, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct config_desc gpio9_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 0x0002, AUD_TX_EN_X, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 0x0002, AUD_TX_EN_Y, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct config_desc gpio10_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 0x0001, IIC_2_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0x0003, UART_2_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0x0140, AUD_RX_EN, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct config_desc gpio11_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x0001, IIC_2_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x0003, UART_2_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x0140, AUD_RX_EN, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct config_desc gpio12_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x0140, AUD_RX_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct config_desc gpio13_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x0005, PU_LF0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct config_desc gpio14_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x0005, PU_LF1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct config_desc gpio15_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x0005, PU_LF2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct config_desc gpio16_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x0005, PU_LF3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct config_desc gpio17_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x0001, IIC_1_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 0x0003, UART_1_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct config_desc gpio18_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x0001, IIC_1_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0x0003, UART_1_EN, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct group_desc max96755f_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GROUP_DESC_CONFIG(gpio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GROUP_DESC_CONFIG(gpio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GROUP_DESC(gpio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GROUP_DESC(gpio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GROUP_DESC_CONFIG(gpio4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GROUP_DESC_CONFIG(gpio5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GROUP_DESC(gpio6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GROUP_DESC_CONFIG(gpio7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GROUP_DESC_CONFIG(gpio8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GROUP_DESC_CONFIG(gpio9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GROUP_DESC_CONFIG(gpio10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GROUP_DESC_CONFIG(gpio11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GROUP_DESC_CONFIG(gpio12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GROUP_DESC_CONFIG(gpio13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GROUP_DESC_CONFIG(gpio14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GROUP_DESC_CONFIG(gpio15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GROUP_DESC_CONFIG(gpio16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GROUP_DESC_CONFIG(gpio17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GROUP_DESC_CONFIG(gpio18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GROUP_DESC(gpio19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GROUP_DESC(gpio20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GROUP_DESC(i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GROUP_DESC(uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const char *gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "gpio6", "gpio7", "gpio8", "gpio9", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const char *i2c_groups[] = { "i2c" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char *uart_groups[] = { "uart" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define FUNCTION_DESC(fname, gname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .group_names = gname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .num_group_names = ARRAY_SIZE(gname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define FUNCTION_DESC_GPIO() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "GPIO", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .data = (void *)(const struct max96755f_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define FUNCTION_DESC_GPIO_RX(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "GPIO_RX_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .data = (void *)(const struct max96755f_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .gpio_rx_en = 1, .gpio_rx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FUNCTION_DESC_GPIO_TX(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "GPIO_TX_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .data = (void *)(const struct max96755f_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct function_desc max96755f_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) FUNCTION_DESC_GPIO_TX(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) FUNCTION_DESC_GPIO_TX(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) FUNCTION_DESC_GPIO_TX(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) FUNCTION_DESC_GPIO_TX(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) FUNCTION_DESC_GPIO_TX(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) FUNCTION_DESC_GPIO_TX(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) FUNCTION_DESC_GPIO_TX(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) FUNCTION_DESC_GPIO_TX(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) FUNCTION_DESC_GPIO_TX(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) FUNCTION_DESC_GPIO_TX(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) FUNCTION_DESC_GPIO_TX(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) FUNCTION_DESC_GPIO_TX(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FUNCTION_DESC_GPIO_TX(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) FUNCTION_DESC_GPIO_TX(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) FUNCTION_DESC_GPIO_TX(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) FUNCTION_DESC_GPIO_TX(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) FUNCTION_DESC_GPIO_TX(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) FUNCTION_DESC_GPIO_TX(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) FUNCTION_DESC_GPIO_TX(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) FUNCTION_DESC_GPIO_TX(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) FUNCTION_DESC_GPIO_TX(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) FUNCTION_DESC_GPIO_RX(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) FUNCTION_DESC_GPIO_RX(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) FUNCTION_DESC_GPIO_RX(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) FUNCTION_DESC_GPIO_RX(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) FUNCTION_DESC_GPIO_RX(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) FUNCTION_DESC_GPIO_RX(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) FUNCTION_DESC_GPIO_RX(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FUNCTION_DESC_GPIO_RX(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) FUNCTION_DESC_GPIO_RX(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) FUNCTION_DESC_GPIO_RX(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) FUNCTION_DESC_GPIO_RX(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) FUNCTION_DESC_GPIO_RX(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) FUNCTION_DESC_GPIO_RX(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) FUNCTION_DESC_GPIO_RX(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FUNCTION_DESC_GPIO_RX(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) FUNCTION_DESC_GPIO_RX(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) FUNCTION_DESC_GPIO_RX(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) FUNCTION_DESC_GPIO_RX(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) FUNCTION_DESC_GPIO_RX(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) FUNCTION_DESC_GPIO_RX(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FUNCTION_DESC_GPIO_RX(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) FUNCTION_DESC_GPIO(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) FUNCTION_DESC(I2C, i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) FUNCTION_DESC(UART, uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int max96755f_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct max96755f_pinctrl *mpctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct pinctrl_desc *pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!mpctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mpctl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) platform_set_drvdata(pdev, mpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mpctl->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!mpctl->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!pctl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pctl_desc->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pctl_desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pctl_desc->pctlops = &max96755f_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pctl_desc->pmxops = &max96755f_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pctl_desc->confops = &max96755f_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pctl_desc->pins = max96755f_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pctl_desc->npins = ARRAY_SIZE(max96755f_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &mpctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return dev_err_probe(dev, ret, "failed to register pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < ARRAY_SIZE(max96755f_groups); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) const struct group_desc *group = &max96755f_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = pinctrl_generic_add_group(mpctl->pctl, group->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) group->pins, group->num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) group->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "failed to register group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) group->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for (i = 0; i < ARRAY_SIZE(max96755f_functions); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) const struct function_desc *func = &max96755f_functions[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = pinmux_generic_add_function(mpctl->pctl, func->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) func->group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) func->num_group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) func->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "failed to register function %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return pinctrl_enable(mpctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct of_device_id max96755f_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { .compatible = "maxim,max96755f-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_DEVICE_TABLE(of, max96755f_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct platform_driver max96755f_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .name = "max96755f-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .of_match_table = max96755f_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .probe = max96755f_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) module_platform_driver(max96755f_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_DESCRIPTION("Maxim max96755f pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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