^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim MAX96745 pin control driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/max96745.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct max96745_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct max96745_function_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 gpio_out_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 gpio_io_rx_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 gpio_tx_en_a:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 gpio_tx_en_b:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 gpio_rx_en_a:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 gpio_rx_en_b:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 gpio_tx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 gpio_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int max96745_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int function, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct max96745_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) func = pinmux_generic_get_function(pctldev, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (func->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct max96745_function_data *data = func->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) regmap_update_bits(mpctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GPIO_A_REG(grp->pins[i]), GPIO_OUT_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FIELD_PREP(GPIO_OUT_DIS, data->gpio_out_dis));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (data->gpio_tx_en_a || data->gpio_tx_en_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) regmap_update_bits(mpctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GPIO_B_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GPIO_TX_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FIELD_PREP(GPIO_TX_ID, data->gpio_tx_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (data->gpio_rx_en_a || data->gpio_rx_en_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_update_bits(mpctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GPIO_C_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GPIO_RX_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FIELD_PREP(GPIO_RX_ID, data->gpio_rx_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regmap_update_bits(mpctl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GPIO_D_REG(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GPIO_TX_EN_A | GPIO_TX_EN_B | GPIO_IO_RX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GPIO_RX_EN_A | GPIO_RX_EN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FIELD_PREP(GPIO_TX_EN_A, data->gpio_tx_en_a) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FIELD_PREP(GPIO_TX_EN_B, data->gpio_tx_en_b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FIELD_PREP(GPIO_RX_EN_A, data->gpio_rx_en_a) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FIELD_PREP(GPIO_RX_EN_B, data->gpio_rx_en_b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FIELD_PREP(GPIO_IO_RX_EN, data->gpio_io_rx_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_info(mpctl->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct pinmux_ops max96745_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .set_mux = max96745_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct pinctrl_ops max96745_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct pinctrl_pin_desc max96745_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(8, "gpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(9, "gpio9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(10, "gpio10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(11, "gpio11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(12, "gpio12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(13, "gpio13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(14, "gpio14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(15, "gpio15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(16, "gpio16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(17, "gpio17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(18, "gpio18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(19, "gpio19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(20, "gpio20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(21, "gpio21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(22, "gpio22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(23, "gpio23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(24, "gpio24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(25, "gpio25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int gpio0_pins[] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int gpio1_pins[] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int gpio2_pins[] = {2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int gpio3_pins[] = {3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int gpio4_pins[] = {4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int gpio5_pins[] = {5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int gpio6_pins[] = {6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int gpio7_pins[] = {7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int gpio8_pins[] = {8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int gpio9_pins[] = {9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int gpio10_pins[] = {10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int gpio11_pins[] = {11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int gpio12_pins[] = {12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int gpio13_pins[] = {13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int gpio14_pins[] = {14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int gpio15_pins[] = {15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int gpio16_pins[] = {16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int gpio17_pins[] = {17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int gpio18_pins[] = {18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int gpio19_pins[] = {19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int gpio20_pins[] = {20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int gpio21_pins[] = {21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int gpio22_pins[] = {22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int gpio23_pins[] = {23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int gpio24_pins[] = {24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int gpio25_pins[] = {25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int i2c_pins[] = {3, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int uart_pins[] = {3, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GROUP_DESC(nm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = #nm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .pins = nm ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .num_pins = ARRAY_SIZE(nm ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct group_desc max96745_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GROUP_DESC(gpio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) GROUP_DESC(gpio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) GROUP_DESC(gpio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) GROUP_DESC(gpio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) GROUP_DESC(gpio4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GROUP_DESC(gpio5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GROUP_DESC(gpio6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GROUP_DESC(gpio7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GROUP_DESC(gpio8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GROUP_DESC(gpio9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GROUP_DESC(gpio10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GROUP_DESC(gpio11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GROUP_DESC(gpio12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GROUP_DESC(gpio13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GROUP_DESC(gpio14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GROUP_DESC(gpio15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GROUP_DESC(gpio16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GROUP_DESC(gpio17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GROUP_DESC(gpio18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GROUP_DESC(gpio19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GROUP_DESC(gpio20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GROUP_DESC(gpio21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GROUP_DESC(gpio22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GROUP_DESC(gpio23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GROUP_DESC(gpio24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GROUP_DESC(gpio25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GROUP_DESC(i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GROUP_DESC(uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char *gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "gpio20", "gpio21", "gpio22", "gpio23", "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const char *i2c_groups[] = { "i2c" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char *uart_groups[] = { "uart" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define FUNCTION_DESC_GPIO_TX_A(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "GPIO_TX_A_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .data = (void *)(const struct max96745_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { .gpio_out_dis = 1, .gpio_tx_en_a = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .gpio_io_rx_en = 1, .gpio_tx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FUNCTION_DESC_GPIO_TX_B(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "GPIO_TX_B_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .data = (void *)(const struct max96745_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .gpio_out_dis = 1, .gpio_tx_en_b = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .gpio_io_rx_en = 1, .gpio_tx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FUNCTION_DESC_GPIO_RX_A(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .name = "GPIO_RX_A_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .data = (void *)(const struct max96745_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .gpio_rx_en_a = 1, .gpio_rx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FUNCTION_DESC_GPIO_RX_B(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "GPIO_RX_B_"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .data = (void *)(const struct max96745_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .gpio_rx_en_b = 1, .gpio_rx_id = id } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FUNCTION_DESC_GPIO() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "GPIO", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .group_names = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_group_names = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .data = (void *)(const struct max96745_function_data []) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FUNCTION_DESC(fname, gname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .group_names = gname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .num_group_names = ARRAY_SIZE(gname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct function_desc max96745_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FUNCTION_DESC_GPIO_TX_A(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FUNCTION_DESC_GPIO_TX_A(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FUNCTION_DESC_GPIO_TX_A(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FUNCTION_DESC_GPIO_TX_A(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FUNCTION_DESC_GPIO_TX_A(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FUNCTION_DESC_GPIO_TX_A(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FUNCTION_DESC_GPIO_TX_A(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FUNCTION_DESC_GPIO_TX_A(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FUNCTION_DESC_GPIO_TX_A(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FUNCTION_DESC_GPIO_TX_A(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FUNCTION_DESC_GPIO_TX_A(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FUNCTION_DESC_GPIO_TX_A(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FUNCTION_DESC_GPIO_TX_A(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FUNCTION_DESC_GPIO_TX_A(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FUNCTION_DESC_GPIO_TX_A(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FUNCTION_DESC_GPIO_TX_A(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FUNCTION_DESC_GPIO_TX_A(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FUNCTION_DESC_GPIO_TX_A(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FUNCTION_DESC_GPIO_TX_A(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FUNCTION_DESC_GPIO_TX_A(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FUNCTION_DESC_GPIO_TX_A(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FUNCTION_DESC_GPIO_TX_A(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FUNCTION_DESC_GPIO_TX_A(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FUNCTION_DESC_GPIO_TX_A(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FUNCTION_DESC_GPIO_TX_A(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FUNCTION_DESC_GPIO_TX_A(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FUNCTION_DESC_GPIO_TX_A(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FUNCTION_DESC_GPIO_TX_A(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FUNCTION_DESC_GPIO_TX_A(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FUNCTION_DESC_GPIO_TX_A(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FUNCTION_DESC_GPIO_TX_A(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FUNCTION_DESC_GPIO_TX_A(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FUNCTION_DESC_GPIO_TX_B(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FUNCTION_DESC_GPIO_TX_B(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FUNCTION_DESC_GPIO_TX_B(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FUNCTION_DESC_GPIO_TX_B(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FUNCTION_DESC_GPIO_TX_B(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FUNCTION_DESC_GPIO_TX_B(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FUNCTION_DESC_GPIO_TX_B(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FUNCTION_DESC_GPIO_TX_B(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FUNCTION_DESC_GPIO_TX_B(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FUNCTION_DESC_GPIO_TX_B(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FUNCTION_DESC_GPIO_TX_B(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FUNCTION_DESC_GPIO_TX_B(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FUNCTION_DESC_GPIO_TX_B(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FUNCTION_DESC_GPIO_TX_B(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FUNCTION_DESC_GPIO_TX_B(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FUNCTION_DESC_GPIO_TX_B(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FUNCTION_DESC_GPIO_TX_B(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FUNCTION_DESC_GPIO_TX_B(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FUNCTION_DESC_GPIO_TX_B(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FUNCTION_DESC_GPIO_TX_B(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FUNCTION_DESC_GPIO_TX_B(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FUNCTION_DESC_GPIO_TX_B(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FUNCTION_DESC_GPIO_TX_B(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FUNCTION_DESC_GPIO_TX_B(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FUNCTION_DESC_GPIO_TX_B(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FUNCTION_DESC_GPIO_TX_B(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FUNCTION_DESC_GPIO_TX_B(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FUNCTION_DESC_GPIO_TX_B(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FUNCTION_DESC_GPIO_TX_B(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FUNCTION_DESC_GPIO_TX_B(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FUNCTION_DESC_GPIO_TX_B(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) FUNCTION_DESC_GPIO_TX_B(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FUNCTION_DESC_GPIO_RX_A(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) FUNCTION_DESC_GPIO_RX_A(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) FUNCTION_DESC_GPIO_RX_A(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) FUNCTION_DESC_GPIO_RX_A(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FUNCTION_DESC_GPIO_RX_A(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FUNCTION_DESC_GPIO_RX_A(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FUNCTION_DESC_GPIO_RX_A(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FUNCTION_DESC_GPIO_RX_A(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FUNCTION_DESC_GPIO_RX_A(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FUNCTION_DESC_GPIO_RX_A(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FUNCTION_DESC_GPIO_RX_A(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FUNCTION_DESC_GPIO_RX_A(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FUNCTION_DESC_GPIO_RX_A(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FUNCTION_DESC_GPIO_RX_A(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FUNCTION_DESC_GPIO_RX_A(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FUNCTION_DESC_GPIO_RX_A(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) FUNCTION_DESC_GPIO_RX_A(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FUNCTION_DESC_GPIO_RX_A(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FUNCTION_DESC_GPIO_RX_A(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FUNCTION_DESC_GPIO_RX_A(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FUNCTION_DESC_GPIO_RX_A(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FUNCTION_DESC_GPIO_RX_A(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) FUNCTION_DESC_GPIO_RX_A(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FUNCTION_DESC_GPIO_RX_A(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FUNCTION_DESC_GPIO_RX_A(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FUNCTION_DESC_GPIO_RX_A(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) FUNCTION_DESC_GPIO_RX_A(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FUNCTION_DESC_GPIO_RX_A(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FUNCTION_DESC_GPIO_RX_A(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) FUNCTION_DESC_GPIO_RX_A(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FUNCTION_DESC_GPIO_RX_A(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FUNCTION_DESC_GPIO_RX_A(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FUNCTION_DESC_GPIO_RX_B(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FUNCTION_DESC_GPIO_RX_B(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FUNCTION_DESC_GPIO_RX_B(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FUNCTION_DESC_GPIO_RX_B(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FUNCTION_DESC_GPIO_RX_B(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FUNCTION_DESC_GPIO_RX_B(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FUNCTION_DESC_GPIO_RX_B(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FUNCTION_DESC_GPIO_RX_B(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FUNCTION_DESC_GPIO_RX_B(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FUNCTION_DESC_GPIO_RX_B(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FUNCTION_DESC_GPIO_RX_B(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FUNCTION_DESC_GPIO_RX_B(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FUNCTION_DESC_GPIO_RX_B(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FUNCTION_DESC_GPIO_RX_B(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FUNCTION_DESC_GPIO_RX_B(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FUNCTION_DESC_GPIO_RX_B(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FUNCTION_DESC_GPIO_RX_B(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FUNCTION_DESC_GPIO_RX_B(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FUNCTION_DESC_GPIO_RX_B(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FUNCTION_DESC_GPIO_RX_B(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FUNCTION_DESC_GPIO_RX_B(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FUNCTION_DESC_GPIO_RX_B(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FUNCTION_DESC_GPIO_RX_B(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FUNCTION_DESC_GPIO_RX_B(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FUNCTION_DESC_GPIO_RX_B(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FUNCTION_DESC_GPIO_RX_B(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FUNCTION_DESC_GPIO_RX_B(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FUNCTION_DESC_GPIO_RX_B(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FUNCTION_DESC_GPIO_RX_B(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FUNCTION_DESC_GPIO_RX_B(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FUNCTION_DESC_GPIO_RX_B(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FUNCTION_DESC_GPIO_RX_B(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FUNCTION_DESC_GPIO(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FUNCTION_DESC(I2C, i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FUNCTION_DESC(UART, uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int max96745_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct max96745_pinctrl *mpctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct pinctrl_desc *pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!mpctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mpctl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) platform_set_drvdata(pdev, mpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mpctl->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!mpctl->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!pctl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pctl_desc->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pctl_desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pctl_desc->pctlops = &max96745_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pctl_desc->pmxops = &max96745_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pctl_desc->pins = max96745_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pctl_desc->npins = ARRAY_SIZE(max96745_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &mpctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return dev_err_probe(dev, ret, "failed to register pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < ARRAY_SIZE(max96745_groups); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct group_desc *group = &max96745_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = pinctrl_generic_add_group(mpctl->pctl, group->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) group->pins, group->num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) group->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "failed to register group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) group->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = 0; i < ARRAY_SIZE(max96745_functions); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const struct function_desc *func = &max96745_functions[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = pinmux_generic_add_function(mpctl->pctl, func->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) func->group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) func->num_group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) func->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "failed to register function %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return pinctrl_enable(mpctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct of_device_id max96745_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .compatible = "maxim,max96745-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DEVICE_TABLE(of, max96745_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static struct platform_driver max96745_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "max96745-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .of_match_table = max96745_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .probe = max96745_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) module_platform_driver(max96745_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_DESCRIPTION("Maxim MAX96745 pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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