^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MAX77620 pin control driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Chaitanya Bandi <bandik@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX77620_PIN_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum max77620_pin_ppdrv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MAX77620_PIN_UNCONFIG_DRV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MAX77620_PIN_OD_DRV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MAX77620_PIN_PP_DRV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct max77620_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct pinconf_generic_params max77620_cfg_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .property = "maxim,active-fps-source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .param = MAX77620_ACTIVE_FPS_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .property = "maxim,active-fps-power-up-slot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .property = "maxim,active-fps-power-down-slot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .property = "maxim,suspend-fps-source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .param = MAX77620_SUSPEND_FPS_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .property = "maxim,suspend-fps-power-up-slot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .property = "maxim,suspend-fps-power-down-slot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum max77620_alternate_pinmux_option {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MAX77620_PINMUX_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MAX77620_PINMUX_32K_OUT1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MAX77620_PINMUX_REFERENCE_OUT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct max77620_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const unsigned int pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum max77620_alternate_pinmux_option alt_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct max77620_pin_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum max77620_pin_ppdrv drv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int pull_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct max77620_fps_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int active_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int active_power_up_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int active_power_down_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int suspend_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int suspend_power_up_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int suspend_power_down_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct max77620_pctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regmap *rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int pins_current_opt[MAX77620_GPIO_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct max77620_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct max77620_pingroup *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct pinctrl_pin_desc max77620_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FUNCTION_GROUP(fname, mux) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .groups = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .ngroups = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .mux_option = MAX77620_PINMUX_##mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct max77620_pin_function max77620_pin_function[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FUNCTION_GROUP("gpio", GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FUNCTION_GROUP("32k-out1", 32K_OUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FUNCTION_GROUP("reference-out", REFERENCE_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MAX77620_PINGROUP(pg_name, pin_id, option) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .pins = {MAX77620_##pin_id}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .npins = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .alt_option = MAX77620_PINMUX_##option, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct max77620_pingroup max77620_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return mpci->num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char *max77620_pinctrl_get_group_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pinctrl_dev *pctldev, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return mpci->pin_groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int max77620_pinctrl_get_group_pins(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct pinctrl_dev *pctldev, unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const unsigned int **pins, unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *pins = mpci->pin_groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *num_pins = mpci->pin_groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct pinctrl_ops max77620_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .get_groups_count = max77620_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .get_group_name = max77620_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .get_group_pins = max77620_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return mpci->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return mpci->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *groups = mpci->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *num_groups = mpci->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int function, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (function == MAX77620_PINMUX_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else if (function == mpci->pin_groups[group].alt_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = 1 << group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) group, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) BIT(group), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct pinmux_ops max77620_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .get_functions_count = max77620_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .get_function_name = max77620_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .get_function_groups = max77620_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .set_mux = max77620_pinctrl_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = mpci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (val & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (val & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int addr, int *fps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = regmap_read(mpci->rmap, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int pin, int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int addr, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int mask, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case MAX77620_ACTIVE_FPS_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case MAX77620_SUSPEND_FPS_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mask = MAX77620_FPS_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) shift = MAX77620_FPS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) param_val = fps_config->active_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (param == MAX77620_SUSPEND_FPS_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) param_val = fps_config->suspend_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mask = MAX77620_FPS_PU_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) shift = MAX77620_FPS_PU_PERIOD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) param_val = fps_config->active_power_up_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) param_val = fps_config->suspend_power_up_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mask = MAX77620_FPS_PD_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) shift = MAX77620_FPS_PD_PERIOD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) param_val = fps_config->active_power_down_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) param_val = fps_config->suspend_power_down_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) param, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (param_val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct device *dev = mpci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct max77620_fps_config *fps_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int pu_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int pd_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int addr, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) param_val = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = param_val ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = regmap_update_bits(mpci->rmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MAX77620_REG_GPIO0 + pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MAX77620_CNFG_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto report_update_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mpci->pin_info[pin].drv_type = val ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) val = param_val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = regmap_update_bits(mpci->rmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MAX77620_REG_GPIO0 + pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MAX77620_CNFG_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto report_update_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mpci->pin_info[pin].drv_type = val ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case MAX77620_ACTIVE_FPS_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) fps_config = &mpci->fps_config[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (param_val == MAX77620_FPS_SRC_DEF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = max77620_get_default_fps(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mpci, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &fps_config->active_fps_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (param == MAX77620_ACTIVE_FPS_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fps_config->active_fps_src = param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) fps_config->active_power_up_slots = param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fps_config->active_power_down_slots = param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = max77620_set_fps_param(mpci, pin, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case MAX77620_SUSPEND_FPS_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fps_config = &mpci->fps_config[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (param_val == MAX77620_FPS_SRC_DEF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = max77620_get_default_fps(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mpci, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &fps_config->suspend_fps_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (param == MAX77620_SUSPEND_FPS_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) fps_config->suspend_fps_src = param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fps_config->suspend_power_up_slots = param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) fps_config->suspend_power_down_slots =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) BIT(pin) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) BIT(pin) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = regmap_update_bits(mpci->rmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MAX77620_REG_PUE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) BIT(pin), pu_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(dev, "PUE_GPIO update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = regmap_update_bits(mpci->rmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MAX77620_REG_PDE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BIT(pin), pd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(dev, "PDE_GPIO update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_err(dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) report_update_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(dev, "Reg 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MAX77620_REG_GPIO0 + pin, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct pinconf_ops max77620_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pin_config_get = max77620_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .pin_config_set = max77620_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct pinctrl_desc max77620_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .pctlops = &max77620_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .pmxops = &max77620_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .confops = &max77620_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int max77620_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct max77620_pctrl_info *mpci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!mpci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mpci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mpci->dev->of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mpci->rmap = max77620->rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mpci->pins = max77620_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mpci->functions = max77620_pin_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mpci->pin_groups = max77620_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) platform_set_drvdata(pdev, mpci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) max77620_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) max77620_pinctrl_desc.pins = max77620_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) max77620_pinctrl_desc.num_custom_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ARRAY_SIZE(max77620_cfg_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) max77620_pinctrl_desc.custom_params = max77620_cfg_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0; i < MAX77620_PIN_NUM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mpci->fps_config[i].active_fps_src = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mpci->fps_config[i].active_power_up_slots = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mpci->fps_config[i].active_power_down_slots = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mpci->fps_config[i].suspend_fps_src = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mpci->fps_config[i].suspend_power_up_slots = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mpci->fps_config[i].suspend_power_down_slots = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mpci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (IS_ERR(mpci->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(mpci->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int max77620_suspend_fps_param[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MAX77620_SUSPEND_FPS_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int max77620_active_fps_param[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MAX77620_ACTIVE_FPS_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int max77620_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int pin, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (p = 0; p < 3; ++p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) max77620_set_fps_param(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mpci, pin, max77620_suspend_fps_param[p]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int max77620_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int pin, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (p = 0; p < 3; ++p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) max77620_set_fps_param(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mpci, pin, max77620_active_fps_param[p]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SET_SYSTEM_SLEEP_PM_OPS(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) max77620_pinctrl_suspend, max77620_pinctrl_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct platform_device_id max77620_pinctrl_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { .name = "max77620-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { .name = "max20024-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct platform_driver max77620_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .name = "max77620-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .pm = &max77620_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .probe = max77620_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .id_table = max77620_pinctrl_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) module_platform_driver(max77620_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MODULE_ALIAS("platform:max77620-pinctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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