^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* LPC18XX SCU analog function registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC18XX_SCU_REG_ENAIO0 0xc88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC18XX_SCU_REG_ENAIO1 0xc8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC18XX_SCU_REG_ENAIO2 0xc90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* LPC18XX SCU pin register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC18XX_SCU_PIN_MODE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC18XX_SCU_PIN_EPD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC18XX_SCU_PIN_EPUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC18XX_SCU_PIN_EHS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC18XX_SCU_PIN_EZI BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC18XX_SCU_PIN_ZIF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC18XX_SCU_PIN_EHD_MASK 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC18XX_SCU_PIN_EHD_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC18XX_SCU_USB1_EPD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC18XX_SCU_USB1_EPWR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC18XX_SCU_I2C0_EFP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC18XX_SCU_I2C0_EHD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC18XX_SCU_I2C0_EZI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPC18XX_SCU_I2C0_ZIF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPC18XX_SCU_I2C0_SCL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPC18XX_SCU_I2C0_SDA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPC18XX_SCU_FUNC_PER_PIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* LPC18XX SCU pin interrupt select registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPC18XX_SCU_PINTSEL0 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPC18XX_SCU_PINTSEL1 0xe04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPC18XX_SCU_IRQ_PER_PINTSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPC18XX_GPIO_PINS_PER_PORT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LPC18XX_GPIO_PIN_INT_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPC18XX_SCU_PINTSEL_VAL(val, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* LPC18xx pin types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) TYPE_ND, /* Normal-drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) TYPE_HD, /* High-drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) TYPE_HS, /* High-speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) TYPE_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TYPE_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* LPC18xx pin functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FUNC_R, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FUNC_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FUNC_ADCTRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FUNC_CAN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FUNC_CAN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FUNC_CGU_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FUNC_CLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FUNC_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FUNC_CTIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FUNC_CTOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FUNC_DAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FUNC_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FUNC_EMC_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FUNC_ENET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FUNC_ENET_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FUNC_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FUNC_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FUNC_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FUNC_I2S0_RX_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FUNC_I2S0_RX_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FUNC_I2S0_RX_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FUNC_I2S0_RX_WS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FUNC_I2S0_TX_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FUNC_I2S0_TX_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FUNC_I2S0_TX_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FUNC_I2S0_TX_WS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FUNC_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FUNC_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FUNC_LCD_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FUNC_MCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FUNC_NMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FUNC_QEI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FUNC_SDMMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FUNC_SGPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FUNC_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FUNC_SPIFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FUNC_SSP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FUNC_SSP0_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FUNC_SSP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FUNC_TIMER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FUNC_TIMER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FUNC_TIMER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FUNC_TIMER3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FUNC_TRACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FUNC_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FUNC_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FUNC_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FUNC_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FUNC_USB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FUNC_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FUNC_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char *const lpc18xx_function_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [FUNC_R] = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [FUNC_ADC] = "adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [FUNC_ADCTRIG] = "adctrig",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [FUNC_CAN0] = "can0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [FUNC_CAN1] = "can1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [FUNC_CGU_OUT] = "cgu_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [FUNC_CLKIN] = "clkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [FUNC_CLKOUT] = "clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [FUNC_CTIN] = "ctin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [FUNC_CTOUT] = "ctout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [FUNC_DAC] = "dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [FUNC_EMC] = "emc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [FUNC_EMC_ALT] = "emc_alt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [FUNC_ENET] = "enet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [FUNC_ENET_ALT] = "enet_alt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [FUNC_GPIO] = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [FUNC_I2C0] = "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [FUNC_I2C1] = "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [FUNC_I2S1] = "i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [FUNC_LCD] = "lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [FUNC_LCD_ALT] = "lcd_alt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [FUNC_MCTRL] = "mctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [FUNC_NMI] = "nmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [FUNC_QEI] = "qei",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [FUNC_SDMMC] = "sdmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [FUNC_SGPIO] = "sgpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [FUNC_SPI] = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [FUNC_SPIFI] = "spifi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [FUNC_SSP0] = "ssp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [FUNC_SSP0_ALT] = "ssp0_alt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [FUNC_SSP1] = "ssp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [FUNC_TIMER0] = "timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [FUNC_TIMER1] = "timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [FUNC_TIMER2] = "timer2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [FUNC_TIMER3] = "timer3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [FUNC_TRACE] = "trace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [FUNC_UART0] = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [FUNC_UART1] = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [FUNC_UART2] = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [FUNC_UART3] = "uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [FUNC_USB0] = "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [FUNC_USB1] = "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct lpc18xx_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct lpc18xx_scu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct lpc18xx_pmx_func func[FUNC_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct lpc18xx_pin_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned char analog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned char type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Analog pins are required to have both bias and input disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Macros to maniupluate analog member in lpc18xx_pin_caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LPC18XX_ANALOG_PIN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LPC18XX_ANALOG_BIT_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DAC LPC18XX_ANALOG_PIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .offset = 0x##port * 32 * 4 + pin * 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .functions = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FUNC_##f0, FUNC_##f1, FUNC_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FUNC_##f3, FUNC_##f4, FUNC_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FUNC_##f6, FUNC_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .analog = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .type = TYPE_##t, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .offset = off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .functions = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FUNC_##f0, FUNC_##f1, FUNC_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FUNC_##f3, FUNC_##f4, FUNC_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FUNC_##f6, FUNC_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .analog = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .type = TYPE_##t, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Pinmuxing table taken from data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define LPC18XX_PIN_P(port, pin) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .number = 0x##port * 32 + pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "p"#port"_"#pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .drv_data = &lpc18xx_pin_p##port##_##pin \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Pin numbers for special pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PIN_CLK0 = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PIN_CLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PIN_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PIN_CLK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PIN_USB1_DM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PIN_USB1_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PIN_I2C0_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PIN_I2C0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LPC18XX_PIN(pname, n) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .number = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = #pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .drv_data = &lpc18xx_pin_##pname \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct pinctrl_pin_desc lpc18xx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) LPC18XX_PIN_P(0,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) LPC18XX_PIN_P(0,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) LPC18XX_PIN_P(1,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) LPC18XX_PIN_P(1,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) LPC18XX_PIN_P(1,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) LPC18XX_PIN_P(1,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) LPC18XX_PIN_P(1,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) LPC18XX_PIN_P(1,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) LPC18XX_PIN_P(1,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) LPC18XX_PIN_P(1,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) LPC18XX_PIN_P(1,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) LPC18XX_PIN_P(1,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) LPC18XX_PIN_P(1,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) LPC18XX_PIN_P(1,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) LPC18XX_PIN_P(1,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) LPC18XX_PIN_P(1,13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) LPC18XX_PIN_P(1,14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) LPC18XX_PIN_P(1,15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) LPC18XX_PIN_P(1,16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) LPC18XX_PIN_P(1,17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) LPC18XX_PIN_P(1,18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) LPC18XX_PIN_P(1,19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) LPC18XX_PIN_P(1,20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) LPC18XX_PIN_P(2,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) LPC18XX_PIN_P(2,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) LPC18XX_PIN_P(2,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) LPC18XX_PIN_P(2,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) LPC18XX_PIN_P(2,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) LPC18XX_PIN_P(2,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) LPC18XX_PIN_P(2,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) LPC18XX_PIN_P(2,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) LPC18XX_PIN_P(2,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) LPC18XX_PIN_P(2,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) LPC18XX_PIN_P(2,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) LPC18XX_PIN_P(2,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) LPC18XX_PIN_P(2,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) LPC18XX_PIN_P(2,13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) LPC18XX_PIN_P(3,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) LPC18XX_PIN_P(3,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) LPC18XX_PIN_P(3,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) LPC18XX_PIN_P(3,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) LPC18XX_PIN_P(3,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) LPC18XX_PIN_P(3,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) LPC18XX_PIN_P(3,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) LPC18XX_PIN_P(3,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) LPC18XX_PIN_P(3,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) LPC18XX_PIN_P(4,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) LPC18XX_PIN_P(4,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) LPC18XX_PIN_P(4,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) LPC18XX_PIN_P(4,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) LPC18XX_PIN_P(4,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) LPC18XX_PIN_P(4,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) LPC18XX_PIN_P(4,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) LPC18XX_PIN_P(4,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) LPC18XX_PIN_P(4,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) LPC18XX_PIN_P(4,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) LPC18XX_PIN_P(4,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) LPC18XX_PIN_P(5,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) LPC18XX_PIN_P(5,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) LPC18XX_PIN_P(5,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) LPC18XX_PIN_P(5,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) LPC18XX_PIN_P(5,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) LPC18XX_PIN_P(5,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) LPC18XX_PIN_P(5,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) LPC18XX_PIN_P(5,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) LPC18XX_PIN_P(6,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) LPC18XX_PIN_P(6,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) LPC18XX_PIN_P(6,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) LPC18XX_PIN_P(6,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) LPC18XX_PIN_P(6,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) LPC18XX_PIN_P(6,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) LPC18XX_PIN_P(6,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) LPC18XX_PIN_P(6,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) LPC18XX_PIN_P(6,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) LPC18XX_PIN_P(6,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) LPC18XX_PIN_P(6,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) LPC18XX_PIN_P(6,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) LPC18XX_PIN_P(6,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) LPC18XX_PIN_P(7,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) LPC18XX_PIN_P(7,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) LPC18XX_PIN_P(7,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) LPC18XX_PIN_P(7,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) LPC18XX_PIN_P(7,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) LPC18XX_PIN_P(7,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) LPC18XX_PIN_P(7,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) LPC18XX_PIN_P(7,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) LPC18XX_PIN_P(8,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) LPC18XX_PIN_P(8,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) LPC18XX_PIN_P(8,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) LPC18XX_PIN_P(8,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) LPC18XX_PIN_P(8,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) LPC18XX_PIN_P(8,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) LPC18XX_PIN_P(8,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) LPC18XX_PIN_P(8,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) LPC18XX_PIN_P(8,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) LPC18XX_PIN_P(9,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) LPC18XX_PIN_P(9,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) LPC18XX_PIN_P(9,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) LPC18XX_PIN_P(9,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) LPC18XX_PIN_P(9,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) LPC18XX_PIN_P(9,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) LPC18XX_PIN_P(9,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) LPC18XX_PIN_P(a,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) LPC18XX_PIN_P(a,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) LPC18XX_PIN_P(a,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) LPC18XX_PIN_P(a,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) LPC18XX_PIN_P(a,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) LPC18XX_PIN_P(b,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) LPC18XX_PIN_P(b,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) LPC18XX_PIN_P(b,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) LPC18XX_PIN_P(b,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) LPC18XX_PIN_P(b,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) LPC18XX_PIN_P(b,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) LPC18XX_PIN_P(b,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) LPC18XX_PIN_P(c,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) LPC18XX_PIN_P(c,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) LPC18XX_PIN_P(c,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) LPC18XX_PIN_P(c,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) LPC18XX_PIN_P(c,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) LPC18XX_PIN_P(c,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) LPC18XX_PIN_P(c,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) LPC18XX_PIN_P(c,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) LPC18XX_PIN_P(c,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) LPC18XX_PIN_P(c,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) LPC18XX_PIN_P(c,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) LPC18XX_PIN_P(c,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) LPC18XX_PIN_P(c,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) LPC18XX_PIN_P(c,13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) LPC18XX_PIN_P(c,14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) LPC18XX_PIN_P(d,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LPC18XX_PIN_P(d,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) LPC18XX_PIN_P(d,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) LPC18XX_PIN_P(d,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) LPC18XX_PIN_P(d,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) LPC18XX_PIN_P(d,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) LPC18XX_PIN_P(d,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) LPC18XX_PIN_P(d,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) LPC18XX_PIN_P(d,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) LPC18XX_PIN_P(d,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) LPC18XX_PIN_P(d,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) LPC18XX_PIN_P(d,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) LPC18XX_PIN_P(d,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) LPC18XX_PIN_P(d,13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) LPC18XX_PIN_P(d,14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) LPC18XX_PIN_P(d,15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) LPC18XX_PIN_P(d,16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) LPC18XX_PIN_P(e,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) LPC18XX_PIN_P(e,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) LPC18XX_PIN_P(e,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) LPC18XX_PIN_P(e,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) LPC18XX_PIN_P(e,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) LPC18XX_PIN_P(e,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) LPC18XX_PIN_P(e,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) LPC18XX_PIN_P(e,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) LPC18XX_PIN_P(e,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) LPC18XX_PIN_P(e,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) LPC18XX_PIN_P(e,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) LPC18XX_PIN_P(e,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) LPC18XX_PIN_P(e,12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) LPC18XX_PIN_P(e,13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) LPC18XX_PIN_P(e,14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) LPC18XX_PIN_P(e,15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) LPC18XX_PIN_P(f,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) LPC18XX_PIN_P(f,1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) LPC18XX_PIN_P(f,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) LPC18XX_PIN_P(f,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) LPC18XX_PIN_P(f,4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) LPC18XX_PIN_P(f,5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) LPC18XX_PIN_P(f,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) LPC18XX_PIN_P(f,7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) LPC18XX_PIN_P(f,8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) LPC18XX_PIN_P(f,9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) LPC18XX_PIN_P(f,10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) LPC18XX_PIN_P(f,11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) LPC18XX_PIN(clk0, PIN_CLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) LPC18XX_PIN(clk1, PIN_CLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) LPC18XX_PIN(clk2, PIN_CLK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) LPC18XX_PIN(clk3, PIN_CLK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct pinconf_generic_params lpc18xx_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (reg & LPC18XX_SCU_USB1_EPWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) *arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (reg & LPC18XX_SCU_USB1_EPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (reg & LPC18XX_SCU_USB1_EPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (pin == PIN_I2C0_SCL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) *arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case PIN_CONFIG_INPUT_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *arg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *arg = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return pin - range->pin_base + range->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) reg_val = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) reg_val >>= BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *arg += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int gpio_port, gpio_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int *arg, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int gpio, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) gpio = lpc18xx_pin_to_gpio(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (gpio < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = lpc18xx_gpio_to_pintsel_val(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * Check if this pin has been enabled as a interrupt in any of the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * PINTSEL registers. *arg indicates which interrupt number (0-7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int *arg, u32 reg, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct lpc18xx_pin_caps *pin_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (reg & LPC18XX_SCU_PIN_EPUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (reg & LPC18XX_SCU_PIN_EPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (reg & LPC18XX_SCU_PIN_EZI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (pin_cap->type == TYPE_HD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (reg & LPC18XX_SCU_PIN_EHS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) *arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (reg & LPC18XX_SCU_PIN_ZIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) *arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (pin_cap->type != TYPE_HD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) switch (*arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case 3: *arg += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case 2: *arg += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case 1: *arg += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case 0: *arg += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case PIN_CONFIG_GPIO_PIN_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (lpc18xx_pins[i].number == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return lpc18xx_pins[i].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct lpc18xx_pin_caps *pin_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int ret, arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pin_cap = lpc18xx_get_pin_caps(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!pin_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) reg = readl(scu->base + pin_cap->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (pin_cap->type == TYPE_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) else if (pin_cap->type == TYPE_USB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 param_val, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) *reg &= ~LPC18XX_SCU_USB1_EPWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) *reg |= LPC18XX_SCU_USB1_EPWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) *reg &= ~LPC18XX_SCU_USB1_EPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *reg |= LPC18XX_SCU_USB1_EPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(pctldev->dev, "Property not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 param_val, u32 *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (pin == PIN_I2C0_SCL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case PIN_CONFIG_INPUT_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (param_val == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) else if (param_val == 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_err(pctldev->dev, "Property not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 param_val, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) gpio = lpc18xx_pin_to_gpio(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (gpio < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) val = lpc18xx_gpio_to_pintsel_val(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) reg_val = readl(scu->base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writel(reg_val, scu->base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 param_val, u32 *reg, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct lpc18xx_pin_caps *pin_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *reg &= ~LPC18XX_SCU_PIN_EPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *reg |= LPC18XX_SCU_PIN_EPUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) *reg &= ~LPC18XX_SCU_PIN_EPUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *reg |= LPC18XX_SCU_PIN_EPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) *reg |= LPC18XX_SCU_PIN_EZI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *reg &= ~LPC18XX_SCU_PIN_EZI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (pin_cap->type == TYPE_HD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (param_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) *reg &= ~LPC18XX_SCU_PIN_EHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *reg |= LPC18XX_SCU_PIN_EHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (param_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *reg &= ~LPC18XX_SCU_PIN_ZIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) *reg |= LPC18XX_SCU_PIN_ZIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (pin_cap->type != TYPE_HD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) switch (param_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case 20: param_val -= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case 14: param_val -= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case 8: param_val -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) case 4: param_val -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case PIN_CONFIG_GPIO_PIN_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_err(pctldev->dev, "Property not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct lpc18xx_pin_caps *pin_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pin_cap = lpc18xx_get_pin_caps(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!pin_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) reg = readl(scu->base + pin_cap->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) param_val = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (pin_cap->type == TYPE_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else if (pin_cap->type == TYPE_USB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) writel(reg, scu->base + pin_cap->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct pinconf_ops lpc18xx_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .pin_config_get = lpc18xx_pconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .pin_config_set = lpc18xx_pconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return ARRAY_SIZE(lpc18xx_function_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return lpc18xx_function_names[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned *const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) *groups = scu->func[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) *num_groups = scu->func[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Dedicated USB1 and I2C0 pins doesn't support muxing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (pin->type == TYPE_USB1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (function == FUNC_USB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (pin->type == TYPE_I2C0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (function == FUNC_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) offset = LPC18XX_SCU_REG_ENAIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) offset = LPC18XX_SCU_REG_ENAIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) reg = readl(scu->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) writel(reg, scu->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (function == pin->functions[func])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (func >= LPC18XX_SCU_FUNC_PER_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) reg = readl(scu->base + pin->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) writel(reg | func, scu->base + pin->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) lpc18xx_function_names[function]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const struct pinmux_ops lpc18xx_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .get_functions_count = lpc18xx_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .get_function_name = lpc18xx_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .get_function_groups = lpc18xx_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .set_mux = lpc18xx_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return ARRAY_SIZE(lpc18xx_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return lpc18xx_pins[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) *pins = &lpc18xx_pins[group].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const struct pinctrl_ops lpc18xx_pctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .get_groups_count = lpc18xx_pctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .get_group_name = lpc18xx_pctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .get_group_pins = lpc18xx_pctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static struct pinctrl_desc lpc18xx_scu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .name = "lpc18xx/43xx-scu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .pins = lpc18xx_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .npins = ARRAY_SIZE(lpc18xx_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .pctlops = &lpc18xx_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .pmxops = &lpc18xx_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .confops = &lpc18xx_pconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .num_custom_params = ARRAY_SIZE(lpc18xx_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .custom_params = lpc18xx_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .custom_conf_items = lpc18xx_conf_items,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (function == FUNC_DAC && p->analog == DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (function == FUNC_ADC && p->analog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (function == FUNC_USB1 && p->type == TYPE_USB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (function == p->functions[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int lpc18xx_create_group_func_map(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct lpc18xx_scu_data *scu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) u16 pins[ARRAY_SIZE(lpc18xx_pins)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int func, ngroups, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) for (func = 0; func < FUNC_MAX; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (lpc18xx_valid_pin_function(i, func))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) pins[ngroups++] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) scu->func[func].ngroups = ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) scu->func[func].groups = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ngroups, sizeof(char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!scu->func[func].groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) for (i = 0; i < ngroups; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static int lpc18xx_scu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct lpc18xx_scu_data *scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!scu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) scu->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (IS_ERR(scu->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return PTR_ERR(scu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) scu->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (IS_ERR(scu->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dev_err(&pdev->dev, "Input clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return PTR_ERR(scu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_err(&pdev->dev, "Unable to create group func map.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = clk_prepare_enable(scu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(&pdev->dev, "Unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) platform_set_drvdata(pdev, scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (IS_ERR(scu->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_err(&pdev->dev, "Could not register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) clk_disable_unprepare(scu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return PTR_ERR(scu->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const struct of_device_id lpc18xx_scu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) { .compatible = "nxp,lpc1850-scu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static struct platform_driver lpc18xx_scu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .probe = lpc18xx_scu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .name = "lpc18xx-scu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .of_match_table = lpc18xx_scu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) builtin_platform_driver(lpc18xx_scu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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