^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/pinctrl/pinctrl-lantiq.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __PINCTRL_LANTIQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __PINCTRL_LANTIQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LTQ_MAX_MUX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MFPR_FUNC_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum ltq_pinconf_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) LTQ_PINCONF_PARAM_PULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LTQ_PINCONF_PARAM_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LTQ_PINCONF_PARAM_DRIVE_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LTQ_PINCONF_PARAM_SLEW_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LTQ_PINCONF_PARAM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ltq_cfg_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const char *property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum ltq_pinconf_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct ltq_mfp_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const unsigned short func[LTQ_MAX_MUX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct ltq_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const unsigned mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ltq_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct ltq_pinmux_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pinctrl_dev *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* we need to manage up to 5 pad controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *membase[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* the descriptor for the subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct pinctrl_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* we expose our pads to the subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pinctrl_pin_desc *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* the number of pads. this varies between socs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int num_pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* these are our multifunction pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct ltq_mfp_pin *mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int num_mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* a number of multifunction pins can be grouped together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct ltq_pin_group *grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int num_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* a mapping between function string and id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct ltq_pmx_func *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int num_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* the pinconf options that we are able to read from the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct ltq_cfg_param *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int num_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* the pad controller can have a irq mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const unsigned *exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int num_exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* we need 5 clocks max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *clk[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* soc specific callback used to apply muxing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum ltq_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GPIO0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GPIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GPIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GPIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GPIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GPIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GPIO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GPIO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GPIO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GPIO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GPIO10, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GPIO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GPIO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GPIO13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GPIO14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) GPIO15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GPIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GPIO17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) GPIO18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GPIO19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GPIO20, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GPIO21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GPIO22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GPIO23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GPIO24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GPIO25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) GPIO26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GPIO27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GPIO28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GPIO29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GPIO30, /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GPIO31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) GPIO32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GPIO33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GPIO34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GPIO35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GPIO36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) GPIO37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) GPIO38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) GPIO39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) GPIO40, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GPIO41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) GPIO42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GPIO43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GPIO44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GPIO45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GPIO46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GPIO47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GPIO48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GPIO49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GPIO50, /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GPIO51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GPIO52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GPIO53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GPIO54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GPIO55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GPIO56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GPIO57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GPIO58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GPIO59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GPIO60, /* 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GPIO61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) GPIO62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GPIO63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GPIO64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GPIO65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) GPIO66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) GPIO67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) GPIO68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) GPIO69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GPIO70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GPIO71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GPIO72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GPIO73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GPIO74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GPIO75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GPIO76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GPIO77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GPIO78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GPIO79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GPIO80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GPIO81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GPIO82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GPIO83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GPIO84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GPIO85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GPIO86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GPIO87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GPIO88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern int ltq_pinctrl_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ltq_pinmux_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern int ltq_pinctrl_unregister(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif /* __PINCTRL_LANTIQ_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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