^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the Gemini pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This is a group-only pin controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRIVER_NAME "pinctrl-gemini"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * struct gemini_pin_conf - information about configuring a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @pin: the pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @reg: config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @mask: the bits affecting the configuration of the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct gemini_pin_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * struct gemini_pmx - state holder for the gemini pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @dev: a pointer back to containing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @virtbase: the offset to the controller in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @map: regmap to access registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @is_3512: whether the SoC/package is the 3512 variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @is_3516: whether the SoC/package is the 3516 variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @flash_pin: whether the flash pin (extended pins for parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * flash) is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @confs: pin config information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @nconfs: number of pin config information items
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct gemini_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool is_3512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool is_3516;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool flash_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct gemini_pin_conf *confs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int nconfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * struct gemini_pin_group - describes a Gemini pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @pins: an array of discrete physical pins used in this group, taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * from the driver-local pin enumeration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @num_pins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @mask: bits to clear to enable this when doing pin muxing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @value: bits to set to enable this when doing pin muxing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @driving_mask: bitmask for the IO Pad driving register for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * group, if it supports altering the driving strength of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * its lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct gemini_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 driving_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Some straight-forward control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GLOBAL_WORD_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GLOBAL_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GLOBAL_STATUS_FLPIN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GLOBAL_IODRIVE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GLOBAL_GMAC_CTRL_SKEW 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GLOBAL_GMAC0_DATA_SKEW 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GLOBAL_GMAC1_DATA_SKEW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Global Miscellaneous Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * This register controls all Gemini pad/pin multiplexing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * It is a tricky register though:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * be brought back online, so it means permanent disablement of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * corresponding pads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * - For the bits named *_DISABLE, once you enable something, it cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * DISABLED again. So you select a flash configuration once, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * you are stuck with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GLOBAL_MISC_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Not really used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Activated with GMAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* This will be the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TVC_CLK_PAD_ENABLE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCI_CLK_PAD_ENABLE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LPC_CLK_PAD_ENABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TVC_PADS_ENABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SSP_PADS_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LCD_PADS_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LPC_PADS_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCI_PADS_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IDE_PADS_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRAM_PADS_POWERDOWN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NAND_PADS_DISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PFLASH_PADS_DISABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SFLASH_PADS_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PADS_MAXBIT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Ordered by bit index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const gemini_padgroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "serial flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "parallel flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "NAND flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "DRAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "LPC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "LCD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "SSP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "TVC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) NULL, NULL, NULL, NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "LPC CLK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "PCI CLK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "TVC CLK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) NULL, NULL, NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "GMAC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct pinctrl_pin_desc gemini_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Row A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(0, "A1 VREF CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(2, "A3 DRAM CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(3, "A4 DRAM CK N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(4, "A5 DRAM A5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(5, "A6 DRAM CKE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(6, "A7 DRAM DQ11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(7, "A8 DRAM DQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(8, "A9 DRAM DQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(9, "A10 DRAM DQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(11, "A12 DRAM BA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(12, "A13 DRAM A2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(13, "A14 PCI GNT1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(14, "A15 PCI REQ9 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(15, "A16 PCI REQ2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(16, "A17 PCI REQ3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(17, "A18 PCI AD31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Row B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(18, "B1 VCCK CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(19, "B2 PWR EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(20, "B3 RTC CLKI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(21, "B4 DRAM A4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(22, "B5 DRAM A6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(23, "B6 DRAM A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(24, "B7 DRAM DQS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(25, "B8 DRAM DQ15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(26, "B9 DRAM DQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(27, "B10 DRAM DQS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(28, "B11 DRAM WE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(29, "B12 DRAM A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(30, "B13 DRAM A3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(31, "B14 PCI GNT0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(32, "B15 PCI GNT3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(33, "B16 PCI REQ1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(34, "B17 PCI AD30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(35, "B18 PCI AD29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Row C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(37, "C2 XTALI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(38, "C3 PWR BTN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(39, "C4 RTC CLKO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(40, "C5 DRAM A7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(41, "C6 DRAM A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(42, "C7 DRAM DQ10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(43, "C8 DRAM DQ14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(44, "C9 DRAM DQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(45, "C10 DRAM DQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(46, "C11 DRAM CAS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(47, "C12 DRAM A0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(48, "C13 PCI INT0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(49, "C14 EXT RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(50, "C15 PCI GNT2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(51, "C16 PCI AD28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(52, "C17 PCI AD27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(53, "C18 PCI AD26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Row D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(54, "D1 AVCCKHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(55, "D2 AGNDIOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(56, "D3 XTALO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(57, "D4 AVCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(58, "D5 DRAM A8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(59, "D6 DRAM A9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(60, "D7 DRAM DQ9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(61, "D8 DRAM DQ13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(62, "D9 DRAM DQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(63, "D10 DRAM A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(64, "D11 DRAM RAS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(65, "D12 DRAM A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(66, "D13 PCI INTC N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(67, "D14 PCI CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(68, "D15 PCI AD25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(69, "D16 PCI AD24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(70, "D17 PCI CBE3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(71, "D18 PCI AD23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Row E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(72, "E1 AVCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(73, "E2 EBG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(74, "E3 AVCC3IOHB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(75, "E4 REXT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(76, "E5 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(77, "E6 DRAM DQM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(78, "E7 DRAM DQ8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(79, "E8 DRAM DQ12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(80, "E9 DRAM DQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(81, "E10 DRAM DQM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(82, "E11 DRAM BA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(83, "E12 PCI INTA N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(84, "E13 PCI INTB N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(85, "E14 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(86, "E15 PCI AD22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(87, "E16 PCI AD21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(88, "E17 PCI AD20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(89, "E18 PCI AD19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Row F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(90, "F1 SATA0 RXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(91, "F2 SATA0 RXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(92, "F3 AGNDK 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(93, "F4 AVCC3 S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(94, "F5 AVCCK P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(95, "F6 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(98, "F9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(99, "F10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(102, "F13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(103, "F14 PCI AD18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(104, "F15 PCI AD17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(105, "F16 PCI AD16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(106, "F17 PCI CBE2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(107, "F18 PCI FRAME N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Row G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(108, "G1 SATA0 TXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(109, "G2 SATA0 TXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(110, "G3 AGNDK 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(111, "G4 AVCCK 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(112, "G5 TEST CLKOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(113, "G6 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(114, "G7 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(116, "G9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(117, "G10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(119, "G12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(120, "G13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(121, "G14 PCI IRDY N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(122, "G15 PCI TRDY N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(124, "G17 PCI STOP N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(125, "G18 PCI PAR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Row H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(126, "H1 SATA1 TXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(127, "H2 SATA1 TXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(128, "H3 AGNDK 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(129, "H4 AVCCK 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(130, "H5 AVCCK S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(131, "H6 AVCCKHB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(132, "H7 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(133, "H8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(134, "H9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(135, "H10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(136, "H11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(137, "H12 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(138, "H13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(139, "H14 PCI CBE1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(140, "H15 PCI AD15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(141, "H16 PCI AD14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(142, "H17 PCI AD13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(143, "H18 PCI AD12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Row J (for some reason I is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(144, "J1 SATA1 RXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(145, "J2 SATA1 RXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(146, "J3 AGNDK 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(147, "J4 AVCCK 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(148, "J5 IDE DA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(149, "J6 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(150, "J7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(151, "J8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(152, "J9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(153, "J10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(154, "J11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(155, "J12 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(156, "J13 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(157, "J14 PCI AD11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(158, "J15 PCI AD10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(159, "J16 PCI AD9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(160, "J17 PCI AD8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(161, "J18 PCI CBE0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Row K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(162, "K1 IDE CS1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(163, "K2 IDE CS0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(164, "K3 AVCCK 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(165, "K4 IDE DA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(166, "K5 IDE DA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(167, "K6 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(168, "K7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(169, "K8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(170, "K9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(171, "K10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(172, "K11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(173, "K12 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(174, "K13 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(175, "K14 PCI AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(176, "K15 PCI AD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(177, "K16 PCI AD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(178, "K17 PCI AD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(179, "K18 PCI AD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Row L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(180, "L1 IDE INTRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(181, "L2 IDE DMACK N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(182, "L3 IDE IORDY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(183, "L4 IDE DIOR N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(184, "L5 IDE DIOW N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(185, "L6 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(186, "L7 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(187, "L8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(188, "L9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(189, "L10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(190, "L11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(191, "L12 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(192, "L13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(193, "L14 GPIO0 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(194, "L15 GPIO0 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(195, "L16 PCI AD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(196, "L17 PCI AD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(197, "L18 PCI AD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Row M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(198, "M1 IDE DMARQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(199, "M2 IDE DD15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(200, "M3 IDE DD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(201, "M4 IDE DD14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(202, "M5 IDE DD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(203, "M6 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(204, "M7 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(206, "M9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(207, "M10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(208, "M11 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(209, "M12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(210, "M13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(211, "M14 GPIO0 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(212, "M15 GPIO0 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(213, "M16 GPIO0 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(214, "M17 GPIO0 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(215, "M18 GPIO0 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Row N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(216, "N1 IDE DD13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(217, "N2 IDE DD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(218, "N3 IDE DD12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(219, "N4 IDE DD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(220, "N5 IDE DD11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(221, "N6 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(224, "N9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(225, "N10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(226, "N11 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(227, "N12 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(228, "N13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(229, "N14 GPIO0 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(230, "N15 GPIO0 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(231, "N16 GPIO0 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(232, "N17 GPIO0 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(233, "N18 GPIO0 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Row P (for some reason O is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(234, "P1 IDE DD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(235, "P2 IDE DD10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(236, "P3 IDE DD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(237, "P4 IDE DD9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(238, "P5 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(239, "P6 USB XSCO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(243, "P10 GMAC1 TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(245, "P12 MODE SEL 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(246, "P13 GPIO1 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(247, "P14 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(248, "P15 GPIO0 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(249, "P16 GPIO0 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(250, "P17 GPIO0 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(251, "P18 GPIO0 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Row R (for some reason Q us skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(252, "R1 IDE DD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(253, "R2 IDE DD8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(254, "R3 IDE DD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(255, "R4 IDE RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(257, "R6 USB XSCI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(263, "R12 MODE SEL 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(264, "R13 MODE SEL 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(265, "R14 GPIO0 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(266, "R15 GPIO0 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(267, "R16 GPIO0 9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(268, "R17 GPIO0 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(269, "R18 GPIO0 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Row T (for some reason S is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(271, "T2 ICE0 IDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(272, "T3 ICE0 ICK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(273, "T4 ICE0 IMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(274, "T5 ICE0 IDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(275, "T6 USB RREF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(277, "T8 GMAC0 RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(278, "T9 GMAC0 CRS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(280, "T11 GMAC1 RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(281, "T12 GMAC1 CRS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(282, "T13 EXT CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(283, "T14 GPIO1 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(284, "T15 GPIO0 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(285, "T16 GPIO0 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(286, "T17 GPIO0 12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(287, "T18 GPIO0 14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Row U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(288, "U1 ICE0 IRST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(290, "U3 USB0 DP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(291, "U4 USB VCCA U20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(292, "U5 USB1 DP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(296, "U9 GMAC1 COL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(300, "U13 MODE SEL 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(301, "U14 GPIO1 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(302, "U15 GPIO0 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(303, "U16 GPIO0 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(304, "U17 GPIO0 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(305, "U18 GPIO0 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Row V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(307, "V2 USB0 DM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(308, "V3 USB GNDA U20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(309, "V4 USB1 DM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(311, "V6 GMAC0 COL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(312, "V7 GMAC0 TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(314, "V9 REF CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(318, "V13 M30 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(319, "V14 GPIO1 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(320, "V15 GPIO0 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(321, "V16 GPIO0 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(322, "V17 GPIO0 10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(323, "V18 SYS RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Digital ground */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const unsigned int gnd_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const unsigned int dram_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 78, 79, 80, 81, 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const unsigned int system_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 318, 264, 300, 245, 263, 282, 314, 323, 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const unsigned int ide_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const unsigned int sata_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 128, 127, 126, 147, 146, 145, 144, 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const unsigned int usb_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* GMII, ethernet pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const unsigned int gmii_gmac0_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const unsigned int gmii_gmac1_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const unsigned int pci_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 178, 179, 195, 196, 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Apparently the LPC interface is using the PCICLK for the clocking so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * PCI needs to be active at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const unsigned int lpc_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 285, /* LPC_LAD[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 304, /* LPC_SERIRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 286, /* LPC_LAD[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 305, /* LPC_LFRAME# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 287, /* LPC_LAD[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 268, /* LPC_LAD[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Character LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const unsigned int lcd_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const unsigned int ssp_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 285, /* SSP_97RST# SSP AC97 Reset, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 304, /* SSP_FSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 286, /* SSP_ECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 305, /* SSP_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 287, /* SSP_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 268, /* SSP_SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const unsigned int uart_rxtx_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 267, /* UART_SIN serial input, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 322, /* UART_SOUT serial output, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const unsigned int uart_modem_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 285, /* UART_NDCD DCD carrier detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 304, /* UART_NDTR DTR data terminal ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 286, /* UART_NDSR DSR data set ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 305, /* UART_NRTS RTS request to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 287, /* UART_NCTS CTS clear to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 268, /* UART_NRI RI ring indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const unsigned int tvc_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 246, /* TVC_DATA[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 319, /* TVC_DATA[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 301, /* TVC_DATA[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 283, /* TVC_DATA[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 320, /* TVC_DATA[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 302, /* TVC_DATA[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 284, /* TVC_DATA[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 266, /* TVC_DATA[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const unsigned int tvc_clk_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 265, /* TVC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* NAND flash pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const unsigned int nflash_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 253, 254, 249, 250, 232, 233, 211, 193, 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const unsigned int pflash_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 214, 215, 193, 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * The parallel flash can be set up in a 26-bit address bus mode exposing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * A[0-15] (A[15] takes the place of ALE), but it has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * used at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const unsigned int pflash_3512_pins_extended[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 214, 215, 193, 194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* The extra pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 265,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Serial flash pins CE0, CE1, DI, DO, CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const unsigned int gpio0a_3512_pins[] = { 265 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* The GPIO0B (1-4) pins overlap with TVC and ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* The GPIO0C (5-7) pins overlap with ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* The GPIO0D (9,10) pins overlap with UART RX/TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* The GPIO0F (16) pins overlap with LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const unsigned int gpio0f_3512_pins[] = { 269 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* The GPIO0J (23) pins overlap with all flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const unsigned int gpio0j_3512_pins[] = { 232 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* The GPIO0K (24,25) pins overlap with all flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* The GPIO0L (26-29) pins overlap with parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* The GPIO1B (5-10, 27) pins overlap with just IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const unsigned int gpio1b_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 180, 181, 182, 183, 184, 198, 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const unsigned int gpio1c_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 252, 253, 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* The GPIO1D (28-31) pins overlap with LCD and TVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* The GPIO2C (8-31) pins overlap with PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const unsigned int gpio2c_3512_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 140, 141, 142, 143, 157, 158, 159, 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Groups for the 3512 SoC/package */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct gemini_pin_group gemini_3512_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "gndgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .pins = gnd_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .num_pins = ARRAY_SIZE(gnd_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .name = "dramgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .pins = dram_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .num_pins = ARRAY_SIZE(dram_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .mask = DRAM_PADS_POWERDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .name = "rtcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .pins = rtc_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .num_pins = ARRAY_SIZE(rtc_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .name = "powergrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .pins = power_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .num_pins = ARRAY_SIZE(power_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = "systemgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .pins = system_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_pins = ARRAY_SIZE(system_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "vcontrolgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .pins = vcontrol_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .num_pins = ARRAY_SIZE(vcontrol_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .name = "icegrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .pins = ice_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .num_pins = ARRAY_SIZE(ice_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Conflict with some GPIO groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "idegrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pins = ide_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .num_pins = ARRAY_SIZE(ide_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Conflict with all flash usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .driving_mask = GENMASK(21, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .name = "satagrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .pins = sata_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .num_pins = ARRAY_SIZE(sata_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "usbgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .pins = usb_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .num_pins = ARRAY_SIZE(usb_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "gmii_gmac0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .pins = gmii_gmac0_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .driving_mask = GENMASK(17, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .name = "gmii_gmac1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .pins = gmii_gmac1_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Bring out RGMII on the GMAC1 pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .driving_mask = GENMASK(19, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "pcigrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .pins = pci_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .num_pins = ARRAY_SIZE(pci_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Conflict only with GPIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .driving_mask = GENMASK(23, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .name = "lpcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .pins = lpc_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .num_pins = ARRAY_SIZE(lpc_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Conflict with SSP and UART modem pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .mask = SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "lcdgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .pins = lcd_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .num_pins = ARRAY_SIZE(lcd_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* Conflict with TVC and ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .mask = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .value = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .name = "sspgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .pins = ssp_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .num_pins = ARRAY_SIZE(ssp_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Conflict with LPC and UART modem pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .mask = LPC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .value = SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "uartrxtxgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .pins = uart_rxtx_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* No conflicts except GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .name = "uartmodemgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .pins = uart_modem_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .num_pins = ARRAY_SIZE(uart_modem_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Conflict with LPC and SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * so when those are both disabled, modem UART can thrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "tvcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .pins = tvc_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .num_pins = ARRAY_SIZE(tvc_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Conflict with character LCD and ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .value = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .name = "tvcclkgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .pins = tvc_clk_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .num_pins = ARRAY_SIZE(tvc_clk_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .value = TVC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * The construction is done such that it is possible to use a serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * flash together with a NAND or parallel (NOR) flash, but it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * possible to use NAND and parallel flash together. To use serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * flash with one of the two others, the muxbits need to be flipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * around before any access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = "nflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .pins = nflash_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .num_pins = ARRAY_SIZE(nflash_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Conflict with IDE, parallel and serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "pflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .pins = pflash_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .num_pins = ARRAY_SIZE(pflash_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Conflict with IDE, NAND and serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .name = "sflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .pins = sflash_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .num_pins = ARRAY_SIZE(sflash_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Conflict with IDE, NAND and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "gpio0agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pins = gpio0a_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .num_pins = ARRAY_SIZE(gpio0a_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Conflict with TVC CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .mask = TVC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "gpio0bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .pins = gpio0b_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .num_pins = ARRAY_SIZE(gpio0b_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Conflict with TVC and ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .mask = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .name = "gpio0cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .pins = gpio0c_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .num_pins = ARRAY_SIZE(gpio0c_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Conflict with ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .name = "gpio0dgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .pins = gpio0d_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .num_pins = ARRAY_SIZE(gpio0d_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Conflict with UART RX/TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "gpio0egrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .pins = gpio0e_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .num_pins = ARRAY_SIZE(gpio0e_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Conflict with LPC, UART modem pins, SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "gpio0fgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .pins = gpio0f_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_pins = ARRAY_SIZE(gpio0f_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Conflict with LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .name = "gpio0ggrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .pins = gpio0g_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .num_pins = ARRAY_SIZE(gpio0g_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Conflict with NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .value = NAND_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "gpio0hgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .pins = gpio0h_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .num_pins = ARRAY_SIZE(gpio0h_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Conflict with parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .value = PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "gpio0igrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .pins = gpio0i_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .num_pins = ARRAY_SIZE(gpio0i_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Conflict with serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .value = SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = "gpio0jgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .pins = gpio0j_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .num_pins = ARRAY_SIZE(gpio0j_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Conflict with all flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .name = "gpio0kgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .pins = gpio0k_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .num_pins = ARRAY_SIZE(gpio0k_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Conflict with all flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .name = "gpio0lgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .pins = gpio0l_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .num_pins = ARRAY_SIZE(gpio0l_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Conflict with parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .value = PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .name = "gpio0mgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .pins = gpio0m_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .num_pins = ARRAY_SIZE(gpio0m_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Conflict with parallel and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .name = "gpio1agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .pins = gpio1a_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .num_pins = ARRAY_SIZE(gpio1a_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Conflict with IDE and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .value = PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .name = "gpio1bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .pins = gpio1b_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .num_pins = ARRAY_SIZE(gpio1b_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Conflict with IDE only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "gpio1cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .pins = gpio1c_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .num_pins = ARRAY_SIZE(gpio1c_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Conflict with IDE, parallel and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .name = "gpio1dgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .pins = gpio1d_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .num_pins = ARRAY_SIZE(gpio1d_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Conflict with LCD and TVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .name = "gpio2agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .pins = gpio2a_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Conflict with GMII GMAC1 and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .name = "gpio2bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .pins = gpio2b_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Conflict with GMII GMAC1, extended parallel flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .name = "gpio2cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .pins = gpio2c_3512_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .num_pins = ARRAY_SIZE(gpio2c_3512_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Conflict with PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .mask = PCI_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Pin names for the pinmux subsystem, 3516 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const struct pinctrl_pin_desc gemini_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Row A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINCTRL_PIN(0, "A1 AVCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINCTRL_PIN(1, "A2 DRAM CK N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINCTRL_PIN(2, "A3 DRAM CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINCTRL_PIN(3, "A4 DRAM DQM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINCTRL_PIN(4, "A5 DRAM DQ9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINCTRL_PIN(5, "A6 DRAM DQ13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINCTRL_PIN(6, "A7 DRAM DQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINCTRL_PIN(7, "A8 DRAM DQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINCTRL_PIN(8, "A9 DRAM DQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINCTRL_PIN(9, "A10 DRAM VREF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINCTRL_PIN(10, "A11 DRAM DQ24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINCTRL_PIN(11, "A12 DRAM DQ28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINCTRL_PIN(12, "A13 DRAM DQ30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINCTRL_PIN(13, "A14 DRAM DQ18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINCTRL_PIN(14, "A15 DRAM DQ21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINCTRL_PIN(15, "A16 DRAM CAS_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINCTRL_PIN(16, "A17 DRAM BA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINCTRL_PIN(17, "A18 PCI INTA N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINCTRL_PIN(18, "A19 PCI INTB N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINCTRL_PIN(19, "A20 PCI INTC N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* Row B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINCTRL_PIN(20, "B1 PWR EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINCTRL_PIN(21, "B2 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINCTRL_PIN(22, "B3 RTC CLKO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINCTRL_PIN(23, "B4 DRAM A5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINCTRL_PIN(24, "B5 DRAM A6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINCTRL_PIN(25, "B6 DRAM DQS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINCTRL_PIN(26, "B7 DRAM DQ11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINCTRL_PIN(27, "B8 DRAM DQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINCTRL_PIN(28, "B9 DRAM DQS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINCTRL_PIN(29, "B10 DRAM DQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINCTRL_PIN(30, "B11 DRAM DQS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINCTRL_PIN(31, "B12 DRAM DQ27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINCTRL_PIN(32, "B13 DRAM DQ31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINCTRL_PIN(33, "B14 DRAM DQ20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINCTRL_PIN(34, "B15 DRAM DQS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINCTRL_PIN(35, "B16 DRAM WE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINCTRL_PIN(36, "B17 DRAM A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINCTRL_PIN(37, "B18 DRAM A2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINCTRL_PIN(38, "B19 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINCTRL_PIN(39, "B20 PCI GNT0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Row C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINCTRL_PIN(40, "C1 AGNDIOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINCTRL_PIN(41, "C2 XTALI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINCTRL_PIN(42, "C3 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINCTRL_PIN(43, "C4 RTC CLKI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINCTRL_PIN(44, "C5 DRAM A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINCTRL_PIN(45, "C6 DRAM A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINCTRL_PIN(46, "C7 DRAM DQ8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINCTRL_PIN(47, "C8 DRAM DQ10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINCTRL_PIN(48, "C9 DRAM DQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINCTRL_PIN(49, "C10 DRAM DQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINCTRL_PIN(50, "C11 DRAM DQM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINCTRL_PIN(51, "C12 DRAM DQ26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINCTRL_PIN(52, "C13 DRAM DQ16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINCTRL_PIN(53, "C14 DRAM DQ22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINCTRL_PIN(54, "C15 DRAM DQM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINCTRL_PIN(55, "C16 DRAM BA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINCTRL_PIN(56, "C17 DRAM A3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINCTRL_PIN(57, "C18 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINCTRL_PIN(58, "C19 PCI GNT1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINCTRL_PIN(59, "C20 PCI REQ2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Row D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINCTRL_PIN(61, "D2 AVCCKHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINCTRL_PIN(62, "D3 XTALO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINCTRL_PIN(63, "D4 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINCTRL_PIN(64, "D5 CIR RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINCTRL_PIN(65, "D6 DRAM A7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINCTRL_PIN(66, "D7 DRAM A4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINCTRL_PIN(67, "D8 DRAM A8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINCTRL_PIN(68, "D9 DRAM CKE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINCTRL_PIN(69, "D10 DRAM DQ14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINCTRL_PIN(70, "D11 DRAM DQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINCTRL_PIN(71, "D12 DRAM DQ25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINCTRL_PIN(72, "D13 DRAM DQ17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINCTRL_PIN(73, "D14 DRAM DQ23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINCTRL_PIN(74, "D15 DRAM RAS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINCTRL_PIN(75, "D16 DRAM A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINCTRL_PIN(76, "D17 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINCTRL_PIN(77, "D18 EXT RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINCTRL_PIN(78, "D19 PCI REQ1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINCTRL_PIN(79, "D20 PCI REQ3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Row E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINCTRL_PIN(81, "E2 VREF CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINCTRL_PIN(82, "E3 CIR RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINCTRL_PIN(83, "E4 PWR BTN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINCTRL_PIN(84, "E5 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINCTRL_PIN(85, "E6 CIR TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINCTRL_PIN(86, "E7 VCCK CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINCTRL_PIN(87, "E8 DRAM A9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINCTRL_PIN(88, "E9 DRAM DQ12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINCTRL_PIN(89, "E10 DRAM DQ15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINCTRL_PIN(90, "E11 DRAM DQM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINCTRL_PIN(91, "E12 DRAM DQ29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINCTRL_PIN(92, "E13 DRAM DQ19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINCTRL_PIN(93, "E14 DRAM A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINCTRL_PIN(94, "E15 DRAM A0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINCTRL_PIN(95, "E16 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINCTRL_PIN(96, "E17 PCI INTD N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINCTRL_PIN(97, "E18 PCI GNT3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINCTRL_PIN(98, "E19 PCI AD29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINCTRL_PIN(99, "E20 PCI AD28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Row F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINCTRL_PIN(100, "F1 AVCCKHB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINCTRL_PIN(101, "F2 AVCCK P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINCTRL_PIN(102, "F3 EBG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINCTRL_PIN(103, "F4 REXT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINCTRL_PIN(104, "F5 AVCC3IOHB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINCTRL_PIN(105, "F6 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINCTRL_PIN(109, "F10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINCTRL_PIN(110, "F11 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINCTRL_PIN(114, "F15 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINCTRL_PIN(115, "F16 PCI CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINCTRL_PIN(116, "F17 PCI GNT2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINCTRL_PIN(117, "F18 PCI AD31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINCTRL_PIN(118, "F19 PCI AD26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINCTRL_PIN(119, "F20 PCI CBE3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Row G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINCTRL_PIN(120, "G1 SATA0 RXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINCTRL_PIN(121, "G2 SATA0 RXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINCTRL_PIN(122, "G3 AGNDK 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINCTRL_PIN(123, "G4 AVCCK S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINCTRL_PIN(124, "G5 AVCC3 S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINCTRL_PIN(126, "G7 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINCTRL_PIN(128, "G9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINCTRL_PIN(129, "G10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINCTRL_PIN(130, "G11 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINCTRL_PIN(131, "G12 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINCTRL_PIN(133, "G14 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINCTRL_PIN(134, "G15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINCTRL_PIN(135, "G16 PCI REQ0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINCTRL_PIN(136, "G17 PCI AD30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINCTRL_PIN(137, "G18 PCI AD24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINCTRL_PIN(138, "G19 PCI AD23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINCTRL_PIN(139, "G20 PCI AD21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Row H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINCTRL_PIN(140, "H1 SATA0 TXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINCTRL_PIN(141, "H2 SATA0 TXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINCTRL_PIN(142, "H3 AGNDK 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINCTRL_PIN(143, "H4 AVCCK 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINCTRL_PIN(144, "H5 TEST CLKOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINCTRL_PIN(145, "H6 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINCTRL_PIN(147, "H8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINCTRL_PIN(148, "H9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINCTRL_PIN(149, "H10 GDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINCTRL_PIN(150, "H11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINCTRL_PIN(151, "H12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINCTRL_PIN(152, "H13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINCTRL_PIN(153, "H14 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINCTRL_PIN(154, "H15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINCTRL_PIN(155, "H16 PCI AD27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINCTRL_PIN(156, "H17 PCI AD25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINCTRL_PIN(157, "H18 PCI AD22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINCTRL_PIN(158, "H19 PCI AD18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINCTRL_PIN(159, "H20 PCI AD17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Row J (for some reason I is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINCTRL_PIN(160, "J1 SATA1 TXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINCTRL_PIN(161, "J2 SATA1 TXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINCTRL_PIN(162, "J3 AGNDK 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINCTRL_PIN(163, "J4 AVCCK 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINCTRL_PIN(164, "J5 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINCTRL_PIN(165, "J6 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINCTRL_PIN(166, "J7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINCTRL_PIN(167, "J8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINCTRL_PIN(168, "J9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINCTRL_PIN(169, "J10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINCTRL_PIN(170, "J11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINCTRL_PIN(171, "J12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINCTRL_PIN(172, "J13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINCTRL_PIN(173, "J14 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINCTRL_PIN(174, "J15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINCTRL_PIN(175, "J16 PCI AD19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINCTRL_PIN(176, "J17 PCI AD20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINCTRL_PIN(177, "J18 PCI AD16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINCTRL_PIN(178, "J19 PCI CBE2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINCTRL_PIN(179, "J20 PCI FRAME N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Row K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINCTRL_PIN(180, "K1 SATA1 RXDP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINCTRL_PIN(181, "K2 SATA1 RXDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINCTRL_PIN(182, "K3 AGNDK 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINCTRL_PIN(183, "K4 AVCCK 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINCTRL_PIN(184, "K5 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINCTRL_PIN(185, "K6 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINCTRL_PIN(186, "K7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINCTRL_PIN(187, "K8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINCTRL_PIN(188, "K9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINCTRL_PIN(189, "K10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINCTRL_PIN(190, "K11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINCTRL_PIN(191, "K12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINCTRL_PIN(192, "K13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINCTRL_PIN(193, "K14 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINCTRL_PIN(194, "K15 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINCTRL_PIN(195, "K16 PCI TRDY N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINCTRL_PIN(196, "K17 PCI IRDY N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINCTRL_PIN(198, "K19 PCI STOP N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINCTRL_PIN(199, "K20 PCI PAR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Row L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINCTRL_PIN(200, "L1 IDE CS0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINCTRL_PIN(201, "L2 IDE DA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINCTRL_PIN(202, "L3 AVCCK 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINCTRL_PIN(203, "L4 AGND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINCTRL_PIN(204, "L5 IDE DIOR N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINCTRL_PIN(205, "L6 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINCTRL_PIN(206, "L7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINCTRL_PIN(207, "L8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINCTRL_PIN(208, "L9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINCTRL_PIN(209, "L10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINCTRL_PIN(210, "L11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINCTRL_PIN(211, "L12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINCTRL_PIN(212, "L13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINCTRL_PIN(213, "L14 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINCTRL_PIN(214, "L15 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINCTRL_PIN(215, "L16 PCI AD12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINCTRL_PIN(216, "L17 PCI AD13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINCTRL_PIN(217, "L18 PCI AD14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINCTRL_PIN(218, "L19 PCI AD15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINCTRL_PIN(219, "L20 PCI CBE1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Row M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINCTRL_PIN(220, "M1 IDE DA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINCTRL_PIN(221, "M2 IDE CS1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINCTRL_PIN(222, "M3 IDE DA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINCTRL_PIN(223, "M4 IDE DMACK N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINCTRL_PIN(224, "M5 IDE DD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINCTRL_PIN(225, "M6 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINCTRL_PIN(226, "M7 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINCTRL_PIN(227, "M8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINCTRL_PIN(228, "M9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINCTRL_PIN(229, "M10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINCTRL_PIN(230, "M11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINCTRL_PIN(231, "M12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINCTRL_PIN(232, "M13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINCTRL_PIN(233, "M14 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINCTRL_PIN(234, "M15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINCTRL_PIN(235, "M16 PCI AD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINCTRL_PIN(236, "M17 PCI AD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINCTRL_PIN(237, "M18 PCI AD9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINCTRL_PIN(238, "M19 PCI AD10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINCTRL_PIN(239, "M20 PCI AD11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Row N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINCTRL_PIN(240, "N1 IDE IORDY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINCTRL_PIN(241, "N2 IDE INTRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINCTRL_PIN(242, "N3 IDE DIOW N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINCTRL_PIN(243, "N4 IDE DD15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINCTRL_PIN(244, "N5 IDE DMARQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINCTRL_PIN(245, "N6 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINCTRL_PIN(246, "N7 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINCTRL_PIN(247, "N8 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINCTRL_PIN(248, "N9 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINCTRL_PIN(249, "N10 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINCTRL_PIN(250, "N11 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINCTRL_PIN(251, "N12 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINCTRL_PIN(252, "N13 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINCTRL_PIN(253, "N14 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINCTRL_PIN(254, "N15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINCTRL_PIN(256, "N17 PCI AD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINCTRL_PIN(257, "N18 PCI AD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINCTRL_PIN(258, "N19 PCI CBE0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINCTRL_PIN(259, "N20 PCI AD8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* Row P (for some reason O is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINCTRL_PIN(260, "P1 IDE DD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINCTRL_PIN(261, "P2 IDE DD14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINCTRL_PIN(262, "P3 IDE DD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINCTRL_PIN(263, "P4 IDE DD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINCTRL_PIN(264, "P5 IDE DD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINCTRL_PIN(265, "P6 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINCTRL_PIN(266, "P7 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINCTRL_PIN(268, "P9 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINCTRL_PIN(269, "P10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINCTRL_PIN(270, "P11 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINCTRL_PIN(271, "P12 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINCTRL_PIN(272, "P13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINCTRL_PIN(273, "P14 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINCTRL_PIN(274, "P15 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINCTRL_PIN(275, "P16 GPIO0 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINCTRL_PIN(276, "P17 GPIO0 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINCTRL_PIN(277, "P18 PCI AD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINCTRL_PIN(278, "P19 PCI AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINCTRL_PIN(279, "P20 PCI AD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Row R (for some reason Q us skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINCTRL_PIN(280, "R1 IDE DD13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINCTRL_PIN(281, "R2 IDE DD12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINCTRL_PIN(282, "R3 IDE DD10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINCTRL_PIN(283, "R4 IDE DD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINCTRL_PIN(284, "R5 ICE0 IDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINCTRL_PIN(285, "R6 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINCTRL_PIN(289, "R10 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINCTRL_PIN(290, "R11 V1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINCTRL_PIN(291, "R12 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINCTRL_PIN(292, "R13 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINCTRL_PIN(293, "R14 VCC3IOHA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINCTRL_PIN(294, "R15 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINCTRL_PIN(295, "R16 GPIO0 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINCTRL_PIN(296, "R17 GPIO0 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINCTRL_PIN(297, "R18 GPIO0 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINCTRL_PIN(298, "R19 GPIO0 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINCTRL_PIN(299, "R20 PCI AD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Row T (for some reason S is skipped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINCTRL_PIN(300, "T1 IDE DD11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PINCTRL_PIN(301, "T2 IDE DD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINCTRL_PIN(302, "T3 IDE DD8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINCTRL_PIN(303, "T4 ICE0 IDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINCTRL_PIN(304, "T5 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINCTRL_PIN(305, "T6 USB GNDA U20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINCTRL_PIN(311, "T12 GPIO1 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINCTRL_PIN(312, "T13 GPIO0 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINCTRL_PIN(313, "T14 GPIO0 9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINCTRL_PIN(314, "T15 GPIO0 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINCTRL_PIN(315, "T16 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINCTRL_PIN(316, "T17 GPIO0 14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINCTRL_PIN(317, "T18 GPIO0 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINCTRL_PIN(318, "T19 GPIO0 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINCTRL_PIN(319, "T20 GPIO0 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* Row U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINCTRL_PIN(320, "U1 IDE DD9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINCTRL_PIN(321, "U2 IDE DD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINCTRL_PIN(322, "U3 ICE0 ICK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINCTRL_PIN(323, "U4 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINCTRL_PIN(324, "U5 USB XSCO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINCTRL_PIN(327, "U8 GMAC0 TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINCTRL_PIN(330, "U11 GMAC1 CRS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINCTRL_PIN(331, "U12 EXT CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINCTRL_PIN(332, "U13 DEV DEF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINCTRL_PIN(333, "U14 GPIO0 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINCTRL_PIN(334, "U15 GPIO0 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINCTRL_PIN(335, "U16 GPIO0 10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINCTRL_PIN(336, "U17 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINCTRL_PIN(337, "U18 GPIO0 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINCTRL_PIN(338, "U19 GPIO0 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINCTRL_PIN(339, "U20 GPIO0 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* Row V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINCTRL_PIN(342, "V3 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINCTRL_PIN(343, "V4 ICE0 IRST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINCTRL_PIN(344, "V5 USB XSCI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINCTRL_PIN(345, "V6 GMAC0 COL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINCTRL_PIN(349, "V10 GMAC1 COL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINCTRL_PIN(350, "V11 GMAC1 TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINCTRL_PIN(352, "V13 MODE SEL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINCTRL_PIN(353, "V14 GPIO1 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINCTRL_PIN(354, "V15 GPIO0 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINCTRL_PIN(355, "V16 GPIO0 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINCTRL_PIN(356, "V17 GPIO0 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINCTRL_PIN(357, "V18 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINCTRL_PIN(358, "V19 GPIO0 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINCTRL_PIN(359, "V20 GPIO0 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Row W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINCTRL_PIN(360, "W1 IDE RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINCTRL_PIN(361, "W2 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINCTRL_PIN(363, "W4 USB0 DP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINCTRL_PIN(364, "W5 USB VCCA U20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINCTRL_PIN(365, "W6 USB1 DP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINCTRL_PIN(368, "W9 GMAC0 CRS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINCTRL_PIN(372, "W13 MODE SEL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINCTRL_PIN(373, "W14 MODE SEL3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINCTRL_PIN(374, "W15 GPIO1 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINCTRL_PIN(375, "W16 GPIO0 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINCTRL_PIN(376, "W17 GPIO0 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINCTRL_PIN(377, "W18 GPIO0 12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINCTRL_PIN(378, "W19 GND"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINCTRL_PIN(379, "W20 GPIO0 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Row Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINCTRL_PIN(380, "Y1 ICE0 IMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINCTRL_PIN(382, "Y3 USB0 DM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINCTRL_PIN(383, "Y4 USB RREF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINCTRL_PIN(384, "Y5 USB1 DM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINCTRL_PIN(388, "Y9 REF CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINCTRL_PIN(392, "Y13 M30 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINCTRL_PIN(393, "Y14 MODE SEL2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINCTRL_PIN(394, "Y15 GPIO1 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINCTRL_PIN(395, "Y16 GPIO0 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINCTRL_PIN(396, "Y17 GPIO0 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINCTRL_PIN(397, "Y18 SYS RESET N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINCTRL_PIN(398, "Y19 GPIO0 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINCTRL_PIN(399, "Y20 GPIO0 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Digital ground */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const unsigned int gnd_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) 361, 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static const unsigned int dram_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) 87, 88, 89, 90, 91, 92, 93, 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned int system_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) 332, 392, 372, 373, 393, 352, 331, 388, 397, 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static const unsigned int ide_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const unsigned int sata_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 144, 160, 161, 162, 163, 180, 181, 182, 183, 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const unsigned int usb_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* GMII, ethernet pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned int gmii_gmac0_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int gmii_gmac1_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const unsigned int pci_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * Apparently the LPC interface is using the PCICLK for the clocking so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * PCI needs to be active at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const unsigned int lpc_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) 355, /* LPC_LAD[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 356, /* LPC_SERIRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 377, /* LPC_LAD[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) 398, /* LPC_LFRAME# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) 316, /* LPC_LAD[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) 399, /* LPC_LAD[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Character LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const unsigned int lcd_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const unsigned int ssp_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 355, /* SSP_97RST# SSP AC97 Reset, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) 356, /* SSP_FSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) 377, /* SSP_ECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) 398, /* SSP_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) 316, /* SSP_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) 399, /* SSP_SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const unsigned int uart_rxtx_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) 313, /* UART_SIN serial input, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 335, /* UART_SOUT serial output, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static const unsigned int uart_modem_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) 355, /* UART_NDCD DCD carrier detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) 356, /* UART_NDTR DTR data terminal ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) 377, /* UART_NDSR DSR data set ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) 398, /* UART_NRTS RTS request to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) 316, /* UART_NCTS CTS clear to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) 399, /* UART_NRI RI ring indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static const unsigned int tvc_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) 353, /* TVC_DATA[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) 311, /* TVC_DATA[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) 394, /* TVC_DATA[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) 374, /* TVC_DATA[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) 354, /* TVC_DATA[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) 395, /* TVC_DATA[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) 312, /* TVC_DATA[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) 334, /* TVC_DATA[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static const unsigned int tvc_clk_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) 333, /* TVC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* NAND flash pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int nflash_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) 302, 321, 337, 358, 295, 359, 339, 275, 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static const unsigned int pflash_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) 276, 319, 275, 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * The parallel flash can be set up in a 26-bit address bus mode exposing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * A[0-15] (A[15] takes the place of ALE), but it has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * used at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static const unsigned int pflash_3516_pins_extended[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) 276, 319, 275, 298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* The extra pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* Serial flash pins CE0, CE1, DI, DO, CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* The GPIO0B (5-7) pins overlap with ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* The GPIO0D (9,10) pins overlap with UART RX/TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* The GPIO0E (16) pins overlap with LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const unsigned int gpio0e_3516_pins[] = { 314 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* The GPIO0I (23) pins overlap with all flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static const unsigned int gpio0i_3516_pins[] = { 295 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* The GPIO0J (24,25) pins overlap with all flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* The GPIO0K (30,31) pins overlap with NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* The GPIO0L (0) pins overlap with TVC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const unsigned int gpio0l_3516_pins[] = { 333 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* The GPIO1B (5-10,27) pins overlap with just IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static const unsigned int gpio1c_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) 302, 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* The GPIO1D (28-31) pins overlap with TVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* The GPIO2C (8-31) pins overlap with PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static const unsigned int gpio2c_3516_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) 157, 138, 137, 156, 118, 155, 99, 98, 136, 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* Groups for the 3516 SoC/package */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const struct gemini_pin_group gemini_3516_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .name = "gndgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .pins = gnd_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .num_pins = ARRAY_SIZE(gnd_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .name = "dramgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .pins = dram_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .num_pins = ARRAY_SIZE(dram_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .mask = DRAM_PADS_POWERDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .name = "rtcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .pins = rtc_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .num_pins = ARRAY_SIZE(rtc_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .name = "powergrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .pins = power_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .num_pins = ARRAY_SIZE(power_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .name = "cirgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .pins = cir_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .num_pins = ARRAY_SIZE(cir_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .name = "systemgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .pins = system_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .num_pins = ARRAY_SIZE(system_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .name = "vcontrolgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .pins = vcontrol_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .num_pins = ARRAY_SIZE(vcontrol_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .name = "icegrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .pins = ice_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .num_pins = ARRAY_SIZE(ice_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* Conflict with some GPIO groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .name = "idegrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .pins = ide_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .num_pins = ARRAY_SIZE(ide_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* Conflict with all flash usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .driving_mask = GENMASK(21, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .name = "satagrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .pins = sata_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .num_pins = ARRAY_SIZE(sata_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .name = "usbgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .pins = usb_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .num_pins = ARRAY_SIZE(usb_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .name = "gmii_gmac0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .pins = gmii_gmac0_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .mask = GEMINI_GMAC_IOSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .driving_mask = GENMASK(17, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .name = "gmii_gmac1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .pins = gmii_gmac1_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Bring out RGMII on the GMAC1 pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .mask = GEMINI_GMAC_IOSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .driving_mask = GENMASK(19, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .name = "pcigrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .pins = pci_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .num_pins = ARRAY_SIZE(pci_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* Conflict only with GPIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .driving_mask = GENMASK(23, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .name = "lpcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .pins = lpc_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .num_pins = ARRAY_SIZE(lpc_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Conflict with SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .mask = SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .name = "lcdgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .pins = lcd_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .num_pins = ARRAY_SIZE(lcd_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .mask = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .value = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .name = "sspgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .pins = ssp_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .num_pins = ARRAY_SIZE(ssp_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* Conflict with LPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .mask = LPC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .value = SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .name = "uartrxtxgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .pins = uart_rxtx_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* No conflicts except GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .name = "uartmodemgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .pins = uart_modem_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .num_pins = ARRAY_SIZE(uart_modem_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * Conflict with LPC and SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * so when those are both disabled, modem UART can thrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .name = "tvcgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .pins = tvc_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .num_pins = ARRAY_SIZE(tvc_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* Conflict with character LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .value = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "tvcclkgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .pins = tvc_clk_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .num_pins = ARRAY_SIZE(tvc_clk_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .value = TVC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * The construction is done such that it is possible to use a serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * flash together with a NAND or parallel (NOR) flash, but it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * possible to use NAND and parallel flash together. To use serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * flash with one of the two others, the muxbits need to be flipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * around before any access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .name = "nflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .pins = nflash_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .num_pins = ARRAY_SIZE(nflash_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* Conflict with IDE, parallel and serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .name = "pflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .pins = pflash_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .num_pins = ARRAY_SIZE(pflash_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* Conflict with IDE, NAND and serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .name = "sflashgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .pins = sflash_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .num_pins = ARRAY_SIZE(sflash_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* Conflict with IDE, NAND and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .name = "gpio0agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .pins = gpio0a_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .num_pins = ARRAY_SIZE(gpio0a_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* Conflict with TVC and ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .mask = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .name = "gpio0bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .pins = gpio0b_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .num_pins = ARRAY_SIZE(gpio0b_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* Conflict with ICE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .name = "gpio0cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .pins = gpio0c_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .num_pins = ARRAY_SIZE(gpio0c_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* Conflict with LPC, UART and SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .name = "gpio0dgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .pins = gpio0d_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .num_pins = ARRAY_SIZE(gpio0d_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* Conflict with UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .name = "gpio0egrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .pins = gpio0e_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .num_pins = ARRAY_SIZE(gpio0e_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* Conflict with LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .name = "gpio0fgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .pins = gpio0f_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .num_pins = ARRAY_SIZE(gpio0f_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Conflict with NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .value = NAND_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .name = "gpio0ggrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .pins = gpio0g_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .num_pins = ARRAY_SIZE(gpio0g_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* Conflict with parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .value = PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .name = "gpio0hgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .pins = gpio0h_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .num_pins = ARRAY_SIZE(gpio0h_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /* Conflict with serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .value = SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .name = "gpio0igrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .pins = gpio0i_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .num_pins = ARRAY_SIZE(gpio0i_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Conflict with all flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .name = "gpio0jgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .pins = gpio0j_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .num_pins = ARRAY_SIZE(gpio0j_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* Conflict with all flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .mask = LCD_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) SFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .name = "gpio0kgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .pins = gpio0k_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .num_pins = ARRAY_SIZE(gpio0k_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* Conflict with parallel and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .name = "gpio0lgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .pins = gpio0l_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .num_pins = ARRAY_SIZE(gpio0l_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Conflict with TVE CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .mask = TVC_CLK_PAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .name = "gpio1agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .pins = gpio1a_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .num_pins = ARRAY_SIZE(gpio1a_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* Conflict with IDE and parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .value = PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .name = "gpio1bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .pins = gpio1b_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .num_pins = ARRAY_SIZE(gpio1b_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* Conflict with IDE only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .name = "gpio1cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .pins = gpio1c_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .num_pins = ARRAY_SIZE(gpio1c_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Conflict with IDE, parallel and NAND flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .mask = IDE_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .name = "gpio1dgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .pins = gpio1d_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .num_pins = ARRAY_SIZE(gpio1d_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* Conflict with TVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .mask = TVC_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .name = "gpio2agrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .pins = gpio2a_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* Conflict with GMII GMAC1 and extended parallel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .name = "gpio2bgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .pins = gpio2b_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* Conflict with GMII GMAC1, extended parallel flash and LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .name = "gpio2cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .pins = gpio2c_3516_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .num_pins = ARRAY_SIZE(gpio2c_3516_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* Conflict with PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .mask = PCI_PADS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (pmx->is_3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return ARRAY_SIZE(gemini_3512_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (pmx->is_3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ARRAY_SIZE(gemini_3516_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (pmx->is_3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return gemini_3512_pin_groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (pmx->is_3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) return gemini_3516_pin_groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* The special case with the 3516 flash pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (pmx->flash_pin &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) pmx->is_3512 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) *pins = pflash_3512_pins_extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) *num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (pmx->flash_pin &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) pmx->is_3516 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) *pins = pflash_3516_pins_extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) *num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (pmx->is_3512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) *pins = gemini_3512_pin_groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) *num_pins = gemini_3512_pin_groups[selector].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (pmx->is_3516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) *pins = gemini_3516_pin_groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) *num_pins = gemini_3516_pin_groups[selector].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) seq_printf(s, " " DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static const struct pinctrl_ops gemini_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .get_groups_count = gemini_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .get_group_name = gemini_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .get_group_pins = gemini_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .pin_dbg_show = gemini_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * struct gemini_pmx_func - describes Gemini pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * @name: the name of this specific function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * @groups: corresponding pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct gemini_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) const unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static const char * const dramgrps[] = { "dramgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static const char * const rtcgrps[] = { "rtcgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static const char * const powergrps[] = { "powergrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static const char * const cirgrps[] = { "cirgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static const char * const systemgrps[] = { "systemgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const char * const vcontrolgrps[] = { "vcontrolgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const char * const icegrps[] = { "icegrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static const char * const idegrps[] = { "idegrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static const char * const satagrps[] = { "satagrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static const char * const usbgrps[] = { "usbgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static const char * const pcigrps[] = { "pcigrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static const char * const lpcgrps[] = { "lpcgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static const char * const lcdgrps[] = { "lcdgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static const char * const sspgrps[] = { "sspgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) static const char * const tvcgrps[] = { "tvcgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static const char * const nflashgrps[] = { "nflashgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static const char * const sflashgrps[] = { "sflashgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) "gpio0mgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) "gpio1dgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static const struct gemini_pmx_func gemini_pmx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .name = "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .groups = dramgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .num_groups = ARRAY_SIZE(idegrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .name = "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .groups = rtcgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .num_groups = ARRAY_SIZE(rtcgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .name = "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .groups = powergrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .num_groups = ARRAY_SIZE(powergrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* This function is strictly unavailable on 3512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .name = "cir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .groups = cirgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .num_groups = ARRAY_SIZE(cirgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .name = "system",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .groups = systemgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .num_groups = ARRAY_SIZE(systemgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .name = "vcontrol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .groups = vcontrolgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .num_groups = ARRAY_SIZE(vcontrolgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .name = "ice",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .groups = icegrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .num_groups = ARRAY_SIZE(icegrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .name = "ide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .groups = idegrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .num_groups = ARRAY_SIZE(idegrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .name = "sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .groups = satagrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .num_groups = ARRAY_SIZE(satagrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .name = "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .groups = usbgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .num_groups = ARRAY_SIZE(usbgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .name = "gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .groups = gmiigrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .num_groups = ARRAY_SIZE(gmiigrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .groups = pcigrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .num_groups = ARRAY_SIZE(pcigrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .name = "lpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .groups = lpcgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .num_groups = ARRAY_SIZE(lpcgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .name = "lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .groups = lcdgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .num_groups = ARRAY_SIZE(lcdgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .name = "ssp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .groups = sspgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .num_groups = ARRAY_SIZE(sspgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .name = "uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .groups = uartgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .num_groups = ARRAY_SIZE(uartgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .name = "tvc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .groups = tvcgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .num_groups = ARRAY_SIZE(tvcgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .name = "nflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .groups = nflashgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .num_groups = ARRAY_SIZE(nflashgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .name = "pflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .groups = pflashgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .num_groups = ARRAY_SIZE(pflashgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .name = "sflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .groups = sflashgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .num_groups = ARRAY_SIZE(sflashgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .groups = gpio0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .num_groups = ARRAY_SIZE(gpio0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .name = "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .groups = gpio1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .num_groups = ARRAY_SIZE(gpio1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .name = "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .groups = gpio2grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .num_groups = ARRAY_SIZE(gpio2grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct gemini_pmx *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) const struct gemini_pmx_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) const struct gemini_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) u32 before, after, expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) func = &gemini_pmx_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (pmx->is_3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) grp = &gemini_3512_pin_groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) else if (pmx->is_3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) grp = &gemini_3516_pin_groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) dev_err(pmx->dev, "invalid SoC type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) "ACTIVATE function \"%s\" with group \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) grp->mask | grp->value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) grp->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) /* Which bits changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) before &= PADS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) after &= PADS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) expected = before &= ~grp->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) expected |= grp->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) expected &= PADS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* Print changed states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) tmp = grp->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) for_each_set_bit(i, &tmp, PADS_MAXBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) bool enabled = !(i > 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* Did not go low though it should */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (after & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) "pin group %s could not be %s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) "probably a hardware limitation\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) gemini_padgroups[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) enabled ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) before, after, expected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) "padgroup %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) gemini_padgroups[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) enabled ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) tmp = grp->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) for_each_set_bit(i, &tmp, PADS_MAXBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) bool enabled = (i > 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* Did not go high though it should */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (!(after & BIT(i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) "pin group %s could not be %s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) "probably a hardware limitation\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) gemini_padgroups[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) enabled ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) before, after, expected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) "padgroup %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) gemini_padgroups[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) enabled ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) return ARRAY_SIZE(gemini_pmx_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) return gemini_pmx_functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) *groups = gemini_pmx_functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) *num_groups = gemini_pmx_functions[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static const struct pinmux_ops gemini_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .get_functions_count = gemini_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .get_function_name = gemini_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .get_function_groups = gemini_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .set_mux = gemini_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .pin = _n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .reg = _r, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .mask = GENMASK(_hb, _lb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const struct gemini_pin_conf gemini_confs_3512[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static const struct gemini_pin_conf gemini_confs_3516[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) const struct gemini_pin_conf *retconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) for (i = 0; i < pmx->nconfs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) retconf = &pmx->confs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (retconf->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) return retconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) const struct gemini_pin_conf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) case PIN_CONFIG_SKEW_DELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) conf = gemini_get_pin_conf(pmx, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (!conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) regmap_read(pmx->map, conf->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) val &= conf->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) val >>= (ffs(conf->mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) const struct gemini_pin_conf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) case PIN_CONFIG_SKEW_DELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (arg > 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) conf = gemini_get_pin_conf(pmx, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (!conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) "invalid pin for skew delay %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) arg <<= (ffs(conf->mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) "set pin %d to skew delay mask %08x, val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) pin, conf->mask, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) dev_err(pmx->dev, "Invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) const struct gemini_pin_group *grp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (pmx->is_3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) grp = &gemini_3512_pin_groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (pmx->is_3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) grp = &gemini_3516_pin_groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* First figure out if this group supports configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (!grp->driving_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) dev_err(pmx->dev, "pin config group \"%s\" does "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) "not support drive strength setting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) "invalid drive strength %d mA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) val <<= (ffs(grp->driving_mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) grp->driving_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) "set group %s to %d mA drive strength mask %08x val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) grp->name, arg, grp->driving_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) dev_err(pmx->dev, "invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static const struct pinconf_ops gemini_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .pin_config_get = gemini_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .pin_config_set = gemini_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .pin_config_group_set = gemini_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static struct pinctrl_desc gemini_pmx_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .pctlops = &gemini_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .pmxops = &gemini_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .confops = &gemini_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) static int gemini_pmx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) struct gemini_pmx *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* Create state holders etc for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) if (!pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) pmx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) dev_err(dev, "no parent to pin controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) map = syscon_node_to_regmap(parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) dev_err(dev, "no syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) pmx->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* Check that regmap works at first call, then no more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ret = regmap_read(map, GLOBAL_WORD_ID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) dev_err(dev, "cannot access regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) val &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (val == 0x3512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) pmx->is_3512 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) pmx->confs = gemini_confs_3512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) gemini_pmx_desc.pins = gemini_3512_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dev_info(dev, "detected 3512 chip variant\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) } else if (val == 0x3516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) pmx->is_3516 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) pmx->confs = gemini_confs_3516;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) gemini_pmx_desc.pins = gemini_3516_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) dev_info(dev, "detected 3516 chip variant\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) dev_err(dev, "unknown chip ID: %04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* Mask off relevant pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) val &= PADS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) /* Invert the meaning of the DRAM+flash pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) val ^= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) /* Print initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) tmp = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) for_each_set_bit(i, &tmp, PADS_MAXBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) (val & BIT(i)) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* Check if flash pin is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) regmap_read(map, GLOBAL_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (IS_ERR(pmx->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) dev_err(dev, "could not register pinmux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) return PTR_ERR(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) dev_info(dev, "initialized Gemini pin control driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const struct of_device_id gemini_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) { .compatible = "cortina,gemini-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static struct platform_driver gemini_pmx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .of_match_table = gemini_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .probe = gemini_pmx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) static int __init gemini_pmx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) return platform_driver_register(&gemini_pmx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) arch_initcall(gemini_pmx_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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