^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/pinctrl/pinmux-falcon.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * based on linux/drivers/pinctrl/pinmux-pxa910.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-lantiq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Multiplexer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LTQ_PADC_MUX(x) (x * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Pull Up Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LTQ_PADC_PUEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Pull Down Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LTQ_PADC_PDEN 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Slew Rate Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LTQ_PADC_SRC 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Drive Current Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LTQ_PADC_DCC 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Pad Control Availability Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LTQ_PADC_AVAIL 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define pad_r32(p, reg) ltq_r32(p + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define pad_w32(p, val, reg) ltq_w32(val, p + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define pad_w32_mask(c, clear, set, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PINS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PORT(x) (x / PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PORT_PIN(x) (x % PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MFP_FALCON(a, f0, f1, f2, f3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .name = #a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pin = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .func = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FALCON_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FALCON_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FALCON_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FALCON_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GRP_MUX(a, m, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .mux = FALCON_MUX_##m, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pins = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .npins = ARRAY_SIZE(p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum falcon_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FALCON_MUX_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FALCON_MUX_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FALCON_MUX_NTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FALCON_MUX_PPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FALCON_MUX_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FALCON_MUX_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FALCON_MUX_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FALCON_MUX_ASC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FALCON_MUX_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FALCON_MUX_HOSTIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FALCON_MUX_SLIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FALCON_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FALCON_MUX_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FALCON_MUX_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FALCON_MUX_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FALCON_MUX_NONE = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int pad_count[PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int base = bank * PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) d[i].number = base + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pad_count[bank] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct ltq_mfp_pin falcon_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const unsigned pins_por[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const unsigned pins_ntr[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const unsigned pins_ntr8k[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const unsigned pins_pps[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned pins_hrst[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const unsigned pins_mdio[] = {GPIO7, GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) GPIO12, GPIO13, GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned pins_asc0[] = {GPIO32, GPIO33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const unsigned pins_spi_cs0[] = {GPIO37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned pins_spi_cs1[] = {GPIO38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned pins_i2c[] = {GPIO39, GPIO40};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned pins_jtag[] = {GPIO41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const unsigned pins_pcm[] = {GPIO44, GPIO45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned pins_asc1[] = {GPIO44, GPIO45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct ltq_pin_group falcon_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GRP_MUX("por", RST, pins_por),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GRP_MUX("ntr", NTR, pins_ntr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GRP_MUX("ntr8k", NTR, pins_ntr8k),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GRP_MUX("pps", PPS, pins_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GRP_MUX("hrst", RST, pins_hrst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GRP_MUX("mdio", MDIO, pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GRP_MUX("bootled", LED, pins_bled),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GRP_MUX("asc0", ASC, pins_asc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GRP_MUX("spi", SPI, pins_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GRP_MUX("spi cs0", SPI, pins_spi_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GRP_MUX("spi cs1", SPI, pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GRP_MUX("i2c", I2C, pins_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GRP_MUX("jtag", JTAG, pins_jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GRP_MUX("slic", SLIC, pins_slic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GRP_MUX("pcm", PCM, pins_pcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GRP_MUX("asc1", ASC, pins_asc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char * const ltq_rst_grps[] = {"por", "hrst"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char * const ltq_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const char * const ltq_bled_grps[] = {"bootled"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const char * const ltq_i2c_grps[] = {"i2c"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char * const ltq_jtag_grps[] = {"jtag"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const char * const ltq_slic_grps[] = {"slic"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const char * const ltq_pcm_grps[] = {"pcm"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct ltq_pmx_func falcon_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* --------- pinconf related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned group, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void __iomem *mem = info->membase[PORT(pin)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *config = LTQ_PINCONF_PACK(param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case LTQ_PINCONF_PARAM_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *config = LTQ_PINCONF_PACK(param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case LTQ_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *config = LTQ_PINCONF_PACK(param, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *config = LTQ_PINCONF_PACK(param, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *config = LTQ_PINCONF_PACK(param, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum ltq_pinconf_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __iomem *mem = info->membase[PORT(pin)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) reg = LTQ_PADC_DCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case LTQ_PINCONF_PARAM_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg = LTQ_PADC_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case LTQ_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (arg == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reg = LTQ_PADC_PDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = LTQ_PADC_PUEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pr_err("%s: Invalid config param %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pinctrl_dev_get_name(pctrldev), param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pad_w32(mem, BIT(PORT_PIN(pin)), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct seq_file *s, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int port = PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) seq_printf(s, " (port %d) mux %d -- ", port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!falcon_pinconf_get(pctrldev, offset, &config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) seq_printf(s, "pull %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (int)LTQ_PINCONF_UNPACK_ARG(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!falcon_pinconf_get(pctrldev, offset, &config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) seq_printf(s, "drive-current %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (int)LTQ_PINCONF_UNPACK_ARG(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!falcon_pinconf_get(pctrldev, offset, &config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) seq_printf(s, "slew-rate %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (int)LTQ_PINCONF_UNPACK_ARG(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) desc = pin_desc_get(pctrldev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (desc->gpio_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) seq_printf(s, " owner: %s", desc->gpio_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) seq_printf(s, " not registered");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct seq_file *s, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct pinconf_ops falcon_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .pin_config_get = falcon_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .pin_config_set = falcon_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .pin_config_group_get = falcon_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .pin_config_group_set = falcon_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .pin_config_dbg_show = falcon_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct pinctrl_desc falcon_pctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .pins = falcon_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .confops = &falcon_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int mfp, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int port = PORT(info->mfp[mfp].pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if ((port >= PORTS) || (!info->membase[port]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pad_w32(info->membase[port], mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct ltq_cfg_param falcon_cfg_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct ltq_pinmux_info falcon_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .desc = &falcon_pctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .apply_mux = falcon_mux_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .params = falcon_cfg_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .num_params = ARRAY_SIZE(falcon_cfg_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* --------- register the pinctrl layer --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int pinctrl_falcon_get_range_size(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if ((id >= PORTS) || (!falcon_info.membase[id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return fls(avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pinctrl_add_gpio_range(falcon_info.pctrl, range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int pinctrl_falcon_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int pad_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* load and remap the pad resources of the different banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct platform_device *ppdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!bank || *bank >= PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (of_address_to_resource(np, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ppdev = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!ppdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(&pdev->dev, "failed to find pad pdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) put_device(&ppdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (IS_ERR(falcon_info.clk[*bank])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(&ppdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return PTR_ERR(falcon_info.clk[*bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (IS_ERR(falcon_info.membase[*bank])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return PTR_ERR(falcon_info.membase[*bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) avail = pad_r32(falcon_info.membase[*bank],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) LTQ_PADC_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pins = fls(avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pad_count += pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_enable(falcon_info.clk[*bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(&pdev->dev, "found %s with %d pads\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) res.name, pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) falcon_pctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) falcon_pctrl_desc.npins = pad_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) falcon_info.mfp = falcon_mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) falcon_info.grps = falcon_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) falcon_info.funcs = falcon_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = ltq_pinctrl_register(pdev, &falcon_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_info(&pdev->dev, "Init done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct of_device_id falcon_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .compatible = "lantiq,pinctrl-falcon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_DEVICE_TABLE(of, falcon_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct platform_driver pinctrl_falcon_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .probe = pinctrl_falcon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "pinctrl-falcon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .of_match_table = falcon_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int __init pinctrl_falcon_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return platform_driver_register(&pinctrl_falcon_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) core_initcall_sync(pinctrl_falcon_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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