^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2019 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __PINCTRL_EQUILIBRIUM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __PINCTRL_EQUILIBRIUM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* PINPAD register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define REG_PUEN 0x80 /* PULL UP Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define REG_PDEN 0x84 /* PULL DOWN Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REG_SRC 0x88 /* Slew Rate Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define REG_DCC0 0x8C /* Drive Current Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REG_DCC1 0x90 /* Drive Current Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_OD 0x94 /* Open Drain Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_AVAIL 0x98 /* Pad Control Availability Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* GPIO register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GPIO_OUT 0x0 /* Data Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GPIO_IN 0x4 /* Data Input Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GPIO_DIR 0x8 /* Direction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_IRNCR 0x20 /* IRN Capture Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPIO_OUTSET 0x40 /* Output Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_OUTCLR 0x44 /* Output Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPIO_DIRSET 0x48 /* Direction Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPIO_DIRCLR 0x4C /* Direction Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* parse given pin's driver current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO_EDGE_TRIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_LEVEL_TRIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_SINGLE_EDGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_BOTH_EDGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_POSITIVE_TRIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_NEGATIVE_TRIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EQBR_GPIO_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) OP_COUNT_NR_FUNCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) OP_ADD_FUNCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OP_COUNT_NR_FUNC_GRPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OP_ADD_FUNC_GRPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OP_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } funcs_util_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct gpio_irq_type: gpio irq configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @trig_type: level trigger or edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @edge_type: sigle edge or both edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @logic_type: positive trigger or negative trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gpio_irq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int trig_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int edge_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int logic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * struct eqbr_pmx_func: represent a pin function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @name: name of the pin function, used to lookup the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @groups: one or more names of pin groups that provide this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @nr_groups: number of groups included in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct eqbr_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * struct eqbr_pin_bank: represent a pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @membase: base address of the pin bank register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @id: bank id, to idenify the unique bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @pin_base: starting pin number of the pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @nr_pins: number of the pins of the pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @aval_pinmap: available pin bitmap of the pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct eqbr_pin_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 aval_pinmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * struct eqbr_gpio_ctrl: represent a gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @node: device node of gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @bank: pointer to corresponding pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @membase: base address of the gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @chip: gpio chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @ic: irq chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @name: gpio chip name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @virq: irq number of the gpio chip to parent's irq domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @lock: spin lock to protect gpio register write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct eqbr_gpio_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct eqbr_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct irq_chip ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raw_spinlock_t lock; /* protect gpio register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * struct eqbr_pinctrl_drv_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @dev: device instance representing the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @pctl_desc: pin controller descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @pctl_dev: pin control class device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @membase: base address of pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @pin_banks: list of pin banks of the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @nr_banks: number of pin banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @gpio_ctrls: list of gpio controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @nr_gpio_ctrls: number of gpio controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @lock: protect pinctrl register write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct eqbr_pinctrl_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct eqbr_pin_bank *pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct eqbr_gpio_ctrl *gpio_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int nr_gpio_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) raw_spinlock_t lock; /* protect pinpad register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* __PINCTRL_EQUILIBRIUM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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