^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2019 Intel Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pinctrl-equilibrium.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIN_NAME_FMT "io-%d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIN_NAME_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PAD_REG_OFF 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void eqbr_gpio_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) raw_spin_lock_irqsave(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) raw_spin_unlock_irqrestore(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void eqbr_gpio_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) gc->direction_input(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) raw_spin_lock_irqsave(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) raw_spin_unlock_irqrestore(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void eqbr_gpio_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) raw_spin_lock_irqsave(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) raw_spin_unlock_irqrestore(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) eqbr_gpio_disable_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) eqbr_gpio_ack_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void eqbr_cfg_bit(void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int offset, unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(readl(addr) | BIT(offset), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(readl(addr) & ~BIT(offset), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct eqbr_gpio_ctrl *gctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) raw_spin_lock_irqsave(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) raw_spin_unlock_irqrestore(&gctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct gpio_irq_type it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memset(&it, 0, sizeof(it));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) it.trig_type = GPIO_EDGE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) it.edge_type = GPIO_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) it.logic_type = GPIO_POSITIVE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) it.trig_type = GPIO_EDGE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) it.edge_type = GPIO_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) it.logic_type = GPIO_NEGATIVE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) it.trig_type = GPIO_EDGE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) it.edge_type = GPIO_BOTH_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) it.logic_type = GPIO_POSITIVE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) it.trig_type = GPIO_LEVEL_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) it.edge_type = GPIO_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) it.logic_type = GPIO_POSITIVE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) it.trig_type = GPIO_LEVEL_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) it.edge_type = GPIO_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) it.logic_type = GPIO_NEGATIVE_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) eqbr_irq_type_cfg(&it, gctrl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (it.trig_type == GPIO_EDGE_TRIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void eqbr_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct irq_chip *ic = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long pins, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) chained_irq_enter(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pins = readl(gctrl->membase + GPIO_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for_each_set_bit(offset, &pins, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chained_irq_exit(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gc = &gctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) gc->label = gctrl->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #if defined(CONFIG_OF_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gc->of_node = gctrl->node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!of_property_read_bool(gctrl->node, "interrupt-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gctrl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gctrl->ic.name = "gpio_irq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) girq = &gctrl->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) girq->chip = &gctrl->ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) girq->parent_handler = eqbr_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) girq->parents[0] = gctrl->virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device *dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct eqbr_gpio_ctrl *gctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) gctrl = drvdata->gpio_ctrls + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) np = gctrl->node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!gctrl->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (of_address_to_resource(np, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "Failed to get GPIO register address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) gctrl->membase = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(gctrl->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR(gctrl->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) gctrl->virq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!gctrl->virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(dev, "%s: failed to parse and map irq\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gctrl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) raw_spin_lock_init(&gctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) gctrl->membase + GPIO_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) gctrl->membase + GPIO_OUTSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gctrl->membase + GPIO_OUTCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) gctrl->membase + GPIO_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "unable to init generic GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = gpiochip_setup(dev, gctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline struct eqbr_pin_bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct eqbr_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < pctl->nr_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bank = &pctl->pin_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (pin >= bank->pin_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (pin - bank->pin_base) < bank->nr_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct pinctrl_ops eqbr_pctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int pmx, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct eqbr_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bank = find_pinbank_via_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mem = bank->membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) offset = pin - bank->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!(bank->aval_pinmap & BIT(offset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pin, bank->pin_base, bank->aval_pinmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) raw_spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel(pmx, mem + (offset * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) raw_spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int selector, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int *pinmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) func = pinmux_generic_get_function(pctldev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pinmux = grp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) for (i = 0; i < grp->num_pins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct pinmux_ops eqbr_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .set_mux = eqbr_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .gpio_request_enable = eqbr_pinmux_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int get_drv_cur(void __iomem *mem, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int pin_offset = offset % DRV_CUR_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct eqbr_gpio_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct eqbr_pin_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (pctl->gpio_ctrls[i].bank == bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return &pctl->gpio_ctrls[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct eqbr_gpio_ctrl *gctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct eqbr_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) bank = find_pinbank_via_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mem = bank->membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) offset = pin - bank->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!(bank->aval_pinmap & BIT(offset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pin, bank->pin_base, bank->aval_pinmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) raw_spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = !!(readl(mem + REG_PUEN) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val = !!(readl(mem + REG_PDEN) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val = !!(readl(mem + REG_OD) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val = get_drv_cur(mem, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = !!(readl(mem + REG_SRC) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gctrl = get_gpio_ctrls_via_bank(pctl, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!gctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bank->pin_base, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) raw_spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) raw_spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) raw_spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *config = pinconf_to_config_packed(param, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct eqbr_gpio_ctrl *gctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct eqbr_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 regval, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bank = find_pinbank_via_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "Couldn't find pin bank for pin %u\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mem = bank->membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) offset = pin - bank->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mem += REG_PUEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mem += REG_PDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mem += REG_OD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mem += REG_DRCC(offset / DRV_CUR_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) offset = (offset % DRV_CUR_PINS) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mask = GENMASK(1, 0) << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mem += REG_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) gctrl = get_gpio_ctrls_via_bank(pctl, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!gctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) bank->pin_base, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gc = &gctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) gc->direction_output(gc, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) raw_spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regval = readl(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) regval = (regval & ~mask) | ((val << offset) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel(regval, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) raw_spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int group, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int i, npins, old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (eqbr_pinconf_get(pctldev, pins[i], config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (i && old != *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) old = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int i, npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct pinconf_ops eqbr_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .pin_config_get = eqbr_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .pin_config_set = eqbr_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .pin_config_group_get = eqbr_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .pin_config_group_set = eqbr_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int nr_funcs, unsigned int *idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; i < nr_funcs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (funcs[i].name && !strcmp(funcs[i].name, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int *nr_funcs, funcs_util_ops op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const char *fn_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for_each_child_of_node(node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) prop = of_find_property(np, "groups", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (of_property_read_string(np, "function", &fn_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* some groups may not have function, it's OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbg(dev, "Group %s: not function binded!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) (char *)prop->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case OP_COUNT_NR_FUNCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *nr_funcs = *nr_funcs + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case OP_ADD_FUNCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) funcs[i].name = fn_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case OP_COUNT_NR_FUNC_GRPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) funcs[fid].nr_groups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case OP_ADD_FUNC_GRPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) for (j = 0; j < funcs[fid].nr_groups; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!funcs[fid].groups[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) funcs[fid].groups[j] = prop->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct device *dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct eqbr_pmx_func *funcs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int nr_funcs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) for (i = 0; i < nr_funcs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!funcs[i].nr_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) sizeof(*(funcs[i].groups)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!funcs[i].groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < nr_funcs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Ignore the same function with multiple groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (funcs[i].name == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = pinmux_generic_add_function(drvdata->pctl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) funcs[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) funcs[i].groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) funcs[i].nr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(dev, "Failed to register function %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) funcs[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct device *dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned int *pinmux, pin_id, pinmux_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct group_desc group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int j, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for_each_child_of_node(node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) prop = of_find_property(np, "groups", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) group.num_pins = of_property_count_u32_elems(np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (group.num_pins < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(dev, "No pins in the group: %s\n", prop->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) group.name = prop->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) group.pins = devm_kcalloc(dev, group.num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sizeof(*(group.pins)), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!group.pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!pinmux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) for (j = 0; j < group.num_pins; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(dev, "Group %s: Read intel pins id failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) group.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (pin_id >= drvdata->pctl_desc.npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) group.name, j, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) group.pins[j] = pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(dev, "Group %s: Read intel pinmux id failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) group.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pinmux[j] = pinmux_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) group.pins, group.num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pinmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(dev, "Failed to register group %s\n", group.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) memset(&group, 0, sizeof(group));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pinmux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct pinctrl_desc *pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct pinctrl_pin_desc *pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned int nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) char *pin_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pctl_desc = &drvdata->pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pctl_desc->name = "eqbr-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pctl_desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pctl_desc->pctlops = &eqbr_pctl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pctl_desc->pmxops = &eqbr_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pctl_desc->confops = &eqbr_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) raw_spin_lock_init(&drvdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) nr_pins += drvdata->pin_banks[i].nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!pin_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (i = 0; i < nr_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sprintf(pin_names, PIN_NAME_FMT, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pdesc[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pdesc[i].name = pin_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pin_names += PIN_NAME_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pctl_desc->pins = pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pctl_desc->npins = nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) &drvdata->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = eqbr_build_groups(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(dev, "Failed to build groups\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = eqbr_build_functions(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_err(dev, "Failed to build functions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return pinctrl_enable(drvdata->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int pinbank_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct eqbr_pinctrl_drv_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct eqbr_pin_bank *bank, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct device *dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct of_phandle_args spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) bank->membase = drvdata->membase + id * PAD_REG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(dev, "gpio-range not available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) bank->pin_base = spec.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) bank->nr_pins = spec.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) bank->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) id, bank->membase, bank->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) bank->nr_pins, bank->aval_pinmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct device *dev = drvdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct device_node *np_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct eqbr_gpio_ctrl *gctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct eqbr_pin_bank *banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int i, nr_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Count gpio bank number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) nr_gpio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) for_each_node_by_name(np_gpio, "gpio") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (of_device_is_available(np_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) nr_gpio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!nr_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_err(dev, "NO pin bank available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Count pin bank number and gpio controller number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!gctrls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Initialize Pin bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) for_each_node_by_name(np_gpio, "gpio") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!of_device_is_available(np_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pinbank_init(np_gpio, drvdata, banks + i, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) gctrls[i].node = np_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) gctrls[i].bank = banks + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) drvdata->pin_banks = banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) drvdata->nr_banks = nr_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) drvdata->gpio_ctrls = gctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) drvdata->nr_gpio_ctrls = nr_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int eqbr_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct eqbr_pinctrl_drv_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) drvdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (IS_ERR(drvdata->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return PTR_ERR(drvdata->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = pinbank_probe(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = pinctrl_reg(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = gpiolib_reg(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const struct of_device_id eqbr_pinctrl_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { .compatible = "intel,lgm-io" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static struct platform_driver eqbr_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .probe = eqbr_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = "eqbr-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .of_match_table = eqbr_pinctrl_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) module_platform_driver(eqbr_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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