^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Dialog DA9062 pinctrl and GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on DA9055 GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - add pinmux and pinctrl support (gpio alternate mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Documents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * [1] https://www.dialog-semiconductor.com/sites/default/files/da9062_datasheet_3v6.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/da9062/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/da9062/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * We need this get the gpio_desc from a <gpio_chip,offset> tuple to decide if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the gpio is active low without a vendor specific dt-binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../gpio/gpiolib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DA9062_TYPE(offset) (4 * (offset % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DA9062_PIN_SHIFT(offset) (4 * (offset % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DA9062_PIN_ALTERNATE 0x00 /* gpio alternate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DA9062_PIN_GPI 0x01 /* gpio in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DA9062_PIN_GPO_OD 0x02 /* gpio out open-drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DA9062_PIN_GPO_PP 0x03 /* gpio out push-pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DA9062_GPIO_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct da9062_pctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct da9062 *da9062;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int pin_config[DA9062_GPIO_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int da9062_pctl_get_pin_mode(struct da9062_pctl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val >>= DA9062_PIN_SHIFT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val &= DA9062AA_GPIO0_PIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int da9062_pctl_set_pin_mode(struct da9062_pctl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int offset, unsigned int mode_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int mode = mode_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mode &= DA9062AA_GPIO0_PIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mode <<= DA9062_PIN_SHIFT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mask = DA9062AA_GPIO0_PIN_MASK << DA9062_PIN_SHIFT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mask, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pctl->pin_config[offset] = mode_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int da9062_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int gpio_mode, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (gpio_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) switch (gpio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case DA9062_PIN_ALTERNATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case DA9062_PIN_GPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = regmap_read(regmap, DA9062AA_STATUS_B, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case DA9062_PIN_GPO_OD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case DA9062_PIN_GPO_PP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = regmap_read(regmap, DA9062AA_GPIO_MODE0_4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return !!(val & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void da9062_gpio_set(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regmap_update_bits(regmap, DA9062AA_GPIO_MODE0_4, BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) value << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int da9062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (gpio_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (gpio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case DA9062_PIN_ALTERNATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case DA9062_PIN_GPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case DA9062_PIN_GPO_OD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case DA9062_PIN_GPO_PP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int da9062_gpio_direction_input(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct gpio_desc *desc = gpiochip_get_desc(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int gpi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = da9062_pctl_set_pin_mode(pctl, offset, DA9062_PIN_GPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * If the gpio is active low we should set it in hw too. No worries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * about gpio_get() because we read and return the gpio-level. So the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * gpiolib active_low handling is still correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * 0 - active low, 1 - active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) gpi_type = !gpiod_is_active_low(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DA9062AA_GPIO0_TYPE_MASK << DA9062_TYPE(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) gpi_type << DA9062_TYPE(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int da9062_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int pin_config = pctl->pin_config[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = da9062_pctl_set_pin_mode(pctl, offset, pin_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) da9062_gpio_set(gc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int da9062_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct regmap *regmap = pctl->da9062->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * We need to meet the following restrictions [1, Figure 18]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - PIN_CONFIG_BIAS_PULL_DOWN -> only allowed if the pin is used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * gpio input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * - PIN_CONFIG_BIAS_PULL_UP -> only allowed if the pin is used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * gpio output open-drain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BIT(offset), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (gpio_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else if (gpio_mode != DA9062_PIN_GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) BIT(offset), BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (gpio_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else if (gpio_mode != DA9062_PIN_GPO_OD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BIT(offset), BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return da9062_pctl_set_pin_mode(pctl, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DA9062_PIN_GPO_OD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return da9062_pctl_set_pin_mode(pctl, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DA9062_PIN_GPO_PP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int da9062_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct da9062_pctl *pctl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct da9062 *da9062 = pctl->da9062;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return regmap_irq_get_virq(da9062->regmap_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DA9062_IRQ_GPI0 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct gpio_chip reference_gc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .get = da9062_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .set = da9062_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .get_direction = da9062_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .direction_input = da9062_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .direction_output = da9062_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .set_config = da9062_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .to_irq = da9062_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .ngpio = DA9062_GPIO_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int da9062_pctl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct device *parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct da9062_pctl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pctl->da9062 = dev_get_drvdata(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!pctl->da9062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!device_property_present(parent, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < ARRAY_SIZE(pctl->pin_config); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pctl->pin_config[i] = DA9062_PIN_GPO_PP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Currently the driver handles only the GPIO support. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * pinctrl/pinmux support can be added later if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pctl->gc = reference_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pctl->gc.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pctl->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pctl->gc.of_node = parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) platform_set_drvdata(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return devm_gpiochip_add_data(&pdev->dev, &pctl->gc, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct platform_driver da9062_pctl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .probe = da9062_pctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "da9062-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) module_platform_driver(da9062_pctl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_AUTHOR("Marco Felsch <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DESCRIPTION("DA9062 PMIC pinctrl and GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_ALIAS("platform:da9062-gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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