^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * U300 GPIO module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2012 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-coh901.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define U300_GPIO_PORT_STRIDE (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Control Register 32bit (R/W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * gives the number of GPIO pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * bit 8-2 (mask 0x000001FC) contains the core version ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define U300_GPIO_CR (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define U300_GPIO_PXPDIR (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define U300_GPIO_PXPDOR (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define U300_GPIO_PXPCR (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define U300_GPIO_PXPER (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define U300_GPIO_PXIEV (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define U300_GPIO_PXIEN (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define U300_GPIO_PXIFR (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define U300_GPIO_PXICR (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 8 bits per port, no version has more than 7 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define U300_GPIO_NUM_PORTS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define U300_GPIO_PINS_PER_PORT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct u300_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct u300_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 toggle_edge_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct u300_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 dor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 iev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Macro to expand to read a specific register found in the "gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * struct. It requires the struct u300_gpio *gpio variable to exist in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * its context. It calculates the port offset from the given pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * offset, muliplies by the port stride and adds the register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * so it provides a pointer to the desired register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define U300_PIN_REG(pin, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U300_PIN_BIT(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (1 << (pin & 0x07))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct u300_gpio_confdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 bias_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bool output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int outval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define U300_FLOATING_INPUT { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .output = false, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define U300_PULL_UP_INPUT { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .output = false, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U300_OUTPUT_LOW { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .output = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .outval = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U300_OUTPUT_HIGH { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .output = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .outval = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Initial configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct u300_gpio_confdata __initconst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Port 0, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) U300_OUTPUT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Port 1, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) U300_PULL_UP_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) U300_OUTPUT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Port 2, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) U300_PULL_UP_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) U300_PULL_UP_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Port 3, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) U300_PULL_UP_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) U300_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Port 4, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Port 5, pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Port 6, pind 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) U300_FLOATING_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val = readl(U300_PIN_REG(offset, dor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Mask out this pin, note 2 bits per setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel(val, U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 oldmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Drive mode must be set by the special mode set function, set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * push/pull mode by default if no mode has been selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* mode = 0 means input, else some mode is already set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (oldmode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(val, U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u300_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Returning -EINVAL means "supported but not available" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int u300_gpio_config_get(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum pin_config_param param = (enum pin_config_param) *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bool biasmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 drmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* One bit per pin, clamp to bool range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Mask out the two bits for this pin and shift to bits 0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) drmode = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) drmode >>= ((offset & 0x07) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (biasmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!biasmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case PIN_CONFIG_DRIVE_OPEN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) enum pin_config_param param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val = readl(U300_PIN_REG(offset, per));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val = readl(U300_PIN_REG(offset, per));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(val, U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(val, U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case PIN_CONFIG_DRIVE_OPEN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) val = readl(U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) << ((offset & 0x07) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(val, U300_PIN_REG(offset, pcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(gpio->dev, "illegal configuration requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct gpio_chip u300_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .label = "u300-gpio-chip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .get = u300_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .set = u300_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .direction_input = u300_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .direction_output = u300_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = readl(U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Set mode depending on state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (u300_gpio_get(&gpio->chip, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* High now, let's trigger on falling edge next then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Low now, let's trigger on rising edge next then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((trigger & IRQF_TRIGGER_RISING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (trigger & IRQF_TRIGGER_FALLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * The GPIO block can only trigger on falling OR rising edges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * not both. So we need to toggle the mode whenever the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * goes from one state to the other with a special state flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_dbg(gpio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "trigger on both rising and falling edge on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) port->toggle_edge_mode |= U300_PIN_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u300_toggle_trigger(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else if (trigger & IRQF_TRIGGER_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) val = readl(U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else if (trigger & IRQF_TRIGGER_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val = readl(U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void u300_gpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) d->hwirq, port->name, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val = readl(U300_PIN_REG(offset, ien));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void u300_gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val = readl(U300_PIN_REG(offset, ien));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct irq_chip u300_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .name = "u300-gpio-irqchip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .irq_enable = u300_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .irq_disable = u300_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .irq_set_type = u300_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void u300_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct irq_chip *parent_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct u300_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int pinoffset = port->number << 3; /* get the right stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) chained_irq_enter(parent_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Read event register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) val = readl(U300_PIN_REG(pinoffset, iev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Mask relevant bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val &= 0xFFU; /* 8 bits per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* ACK IRQ (clear event) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel(val, U300_PIN_REG(pinoffset, iev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Call IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (val != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int irqoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int offset = pinoffset + irqoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int pin_irq = irq_find_mapping(chip->irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pin_irq, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) generic_handle_irq(pin_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Triggering IRQ on both rising and falling edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * needs mockery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (port->toggle_edge_mode & U300_PIN_BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u300_toggle_trigger(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) chained_irq_exit(parent_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const struct u300_gpio_confdata *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Set mode: input or output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (conf->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Deactivate bias mode for output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u300_gpio_config_set(&gpio->chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Set drive mode for output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u300_gpio_config_set(&gpio->chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PIN_CONFIG_DRIVE_PUSH_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) offset, conf->outval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u300_gpio_direction_input(&gpio->chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Always set output low on input pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u300_gpio_set(&gpio->chip, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Set bias mode for input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) offset, conf->bias_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Write default config and values to all pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const struct u300_gpio_confdata *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int offset = (i*8) + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) conf = &bs335_gpio_config[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u300_gpio_init_pin(gpio, offset, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Here we map a GPIO in the local gpio_chip pin space to a pin in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * the local pinctrl pin space. The pin controller used is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * pinctrl-u300.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct coh901_pinpair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct coh901_pinpair coh901_pintable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) COH901_PINRANGE(10, 426),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) COH901_PINRANGE(11, 180),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) COH901_PINRANGE(13, 179),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) COH901_PINRANGE(14, 178),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) COH901_PINRANGE(16, 194),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) COH901_PINRANGE(17, 193),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) COH901_PINRANGE(18, 192),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) COH901_PINRANGE(19, 191),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) COH901_PINRANGE(20, 186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) COH901_PINRANGE(21, 185),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) COH901_PINRANGE(22, 184),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) COH901_PINRANGE(23, 183),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) COH901_PINRANGE(24, 182),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) COH901_PINRANGE(25, 181),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int __init u300_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct u300_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int portno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 ifr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (gpio == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) gpio->chip = u300_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) gpio->chip.base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) gpio->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (IS_ERR(gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return PTR_ERR(gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) gpio->clk = devm_clk_get(gpio->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (IS_ERR(gpio->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) err = PTR_ERR(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(gpio->dev, "could not get GPIO clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) err = clk_prepare_enable(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(gpio->dev, "could not enable GPIO clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_info(gpio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "initializing GPIO Controller COH 901 571/3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gpio->stride = U300_GPIO_PORT_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) gpio->pcr = U300_GPIO_PXPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gpio->dor = U300_GPIO_PXPDOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gpio->dir = U300_GPIO_PXPDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) gpio->per = U300_GPIO_PXPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gpio->icr = U300_GPIO_PXICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) gpio->ien = U300_GPIO_PXIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gpio->iev = U300_GPIO_PXIEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ifr = U300_GPIO_PXIFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val = readl(gpio->base + U300_GPIO_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_info(gpio->dev, "COH901571/3 block version: %d, " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "number of cores: %d totalling %d pins\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ((val & 0x000001FC) >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ((val & 0x0000FE00) >> 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ((val & 0x0000FE00) >> 9) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) gpio->base + U300_GPIO_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u300_gpio_init_coh901571(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) girq = &gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) girq->chip = &u300_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) girq->parent_handler = u300_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) girq->num_parents = U300_GPIO_NUM_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) goto err_dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct u300_gpio_port *port = &gpio->ports[portno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snprintf(port->name, 8, "gpio%d", portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) port->number = portno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) port->gpio = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) port->irq = platform_get_irq(pdev, portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) girq->parents[portno] = port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Turns off irq force (test register) for this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel(0x0, gpio->base + portno * gpio->stride + ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) girq->default_type = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) gpio->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) err = gpiochip_add_data(&gpio->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto err_dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Add pinctrl pin ranges, the pin controller must be registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct coh901_pinpair *p = &coh901_pintable[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) p->offset, p->pin_base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto err_no_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err_no_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) gpiochip_remove(&gpio->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err_dis_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) clk_disable_unprepare(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(&pdev->dev, "module ERROR:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int __exit u300_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct u300_gpio *gpio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Turn off the GPIO block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(0x00000000U, gpio->base + U300_GPIO_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) gpiochip_remove(&gpio->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) clk_disable_unprepare(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct of_device_id u300_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { .compatible = "stericsson,gpio-coh901" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct platform_driver u300_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .name = "u300-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .of_match_table = u300_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .remove = __exit_p(u300_gpio_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int __init u300_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static void __exit u300_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) platform_driver_unregister(&u300_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) arch_initcall(u300_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) module_exit(u300_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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