^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bitmain BM1880 SoC Pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BM1880_REG_MUX 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct bm1880_pinctrl - driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @base: Pinctrl base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @pctrldev: Pinctrl device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @groups: Pingroups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @ngroups: Number of @groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @funcs: Pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @nfuncs: Number of @funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @pinconf: Pinconf data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct bm1880_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pinctrl_dev *pctrldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct bm1880_pctrl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const struct bm1880_pinmux_function *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct bm1880_pinconf_data *pinconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * struct bm1880_pctrl_group - pinctrl group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @name: Name of the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @pins: Array of pins belonging to this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @npins: Number of @pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct bm1880_pctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * struct bm1880_pinmux_function - a pinmux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @name: Name of the pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @groups: List of pingroups for this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @ngroups: Number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @mux_val: Selector for this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @mux: Offset of function specific mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @mux_shift: Shift for function specific selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct bm1880_pinmux_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 mux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * struct bm1880_pinconf_data - pinconf data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @drv_bits: Drive strength bit width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct bm1880_pinconf_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 drv_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct pinctrl_pin_desc bm1880_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(0, "MIO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(1, "MIO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(2, "MIO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(3, "MIO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(4, "MIO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(5, "MIO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(6, "MIO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(7, "MIO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(8, "MIO8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(9, "MIO9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(10, "MIO10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(11, "MIO11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(12, "MIO12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(13, "MIO13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(14, "MIO14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(15, "MIO15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(16, "MIO16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(17, "MIO17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(18, "MIO18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(19, "MIO19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(20, "MIO20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(21, "MIO21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(22, "MIO22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(23, "MIO23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(24, "MIO24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(25, "MIO25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(26, "MIO26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(27, "MIO27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(28, "MIO28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(29, "MIO29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(30, "MIO30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(31, "MIO31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(32, "MIO32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(33, "MIO33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(34, "MIO34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(35, "MIO35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(36, "MIO36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(37, "MIO37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(38, "MIO38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(39, "MIO39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(40, "MIO40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(41, "MIO41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(42, "MIO42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(43, "MIO43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(44, "MIO44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(45, "MIO45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(46, "MIO46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(47, "MIO47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(48, "MIO48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(49, "MIO49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(50, "MIO50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(51, "MIO51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(52, "MIO52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(53, "MIO53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(54, "MIO54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(55, "MIO55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(56, "MIO56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(57, "MIO57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(58, "MIO58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(59, "MIO59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(60, "MIO60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(61, "MIO61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(62, "MIO62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(63, "MIO63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(64, "MIO64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(65, "MIO65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(66, "MIO66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(67, "MIO67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(68, "MIO68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(69, "MIO69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(70, "MIO70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(71, "MIO71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(72, "MIO72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(73, "MIO73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(74, "MIO74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(75, "MIO75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(76, "MIO76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(77, "MIO77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(78, "MIO78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(79, "MIO79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(80, "MIO80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(81, "MIO81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(82, "MIO82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(83, "MIO83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(84, "MIO84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(85, "MIO85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(86, "MIO86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(87, "MIO87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(88, "MIO88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(89, "MIO89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(90, "MIO90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(91, "MIO91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(92, "MIO92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(93, "MIO93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(94, "MIO94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(95, "MIO95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(96, "MIO96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(97, "MIO97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(98, "MIO98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(99, "MIO99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(100, "MIO100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(101, "MIO101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(102, "MIO102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(103, "MIO103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(104, "MIO104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(105, "MIO105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(106, "MIO106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(107, "MIO107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(108, "MIO108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(109, "MIO109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(110, "MIO110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(111, "MIO111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) enum bm1880_pinmux_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) F_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 10, 11, 12, 13, 14, 15, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 25, 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 36, 37, 38, 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned int pwm0_pins[] = { 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned int pwm1_pins[] = { 30 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned int pwm2_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int pwm3_pins[] = { 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const unsigned int pwm4_pins[] = { 43 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const unsigned int pwm5_pins[] = { 44 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const unsigned int pwm6_pins[] = { 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const unsigned int pwm7_pins[] = { 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned int pwm8_pins[] = { 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const unsigned int pwm9_pins[] = { 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const unsigned int pwm10_pins[] = { 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned int pwm11_pins[] = { 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned int pwm12_pins[] = { 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const unsigned int pwm13_pins[] = { 52 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const unsigned int pwm14_pins[] = { 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int pwm15_pins[] = { 54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const unsigned int pwm16_pins[] = { 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const unsigned int pwm17_pins[] = { 56 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const unsigned int pwm18_pins[] = { 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const unsigned int pwm19_pins[] = { 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const unsigned int pwm20_pins[] = { 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const unsigned int pwm21_pins[] = { 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned int pwm22_pins[] = { 61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const unsigned int pwm23_pins[] = { 62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const unsigned int pwm24_pins[] = { 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const unsigned int pwm25_pins[] = { 98 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned int pwm26_pins[] = { 99 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const unsigned int pwm27_pins[] = { 100 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const unsigned int pwm28_pins[] = { 101 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const unsigned int pwm29_pins[] = { 102 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned int pwm30_pins[] = { 103 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const unsigned int pwm31_pins[] = { 104 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const unsigned int pwm32_pins[] = { 105 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const unsigned int pwm33_pins[] = { 106 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const unsigned int pwm34_pins[] = { 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const unsigned int pwm35_pins[] = { 108 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const unsigned int pwm36_pins[] = { 109 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned int pwm37_pins[] = { 110 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const unsigned int i2c0_pins[] = { 63, 64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const unsigned int i2c1_pins[] = { 65, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned int i2c2_pins[] = { 67, 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const unsigned int i2c3_pins[] = { 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned int i2c4_pins[] = { 71, 72 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const unsigned int uart0_pins[] = { 73, 74 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const unsigned int uart1_pins[] = { 75, 76 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int uart2_pins[] = { 77, 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int uart3_pins[] = { 79, 80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned int uart4_pins[] = { 81, 82 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const unsigned int uart5_pins[] = { 83, 84 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned int uart6_pins[] = { 85, 86 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const unsigned int uart7_pins[] = { 87, 88 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned int uart8_pins[] = { 89, 90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const unsigned int uart9_pins[] = { 91, 92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const unsigned int uart10_pins[] = { 93, 94 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned int uart11_pins[] = { 95, 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const unsigned int gpio0_pins[] = { 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned int gpio1_pins[] = { 98 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const unsigned int gpio2_pins[] = { 99 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const unsigned int gpio3_pins[] = { 100 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const unsigned int gpio4_pins[] = { 101 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const unsigned int gpio5_pins[] = { 102 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const unsigned int gpio6_pins[] = { 103 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned int gpio7_pins[] = { 104 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const unsigned int gpio8_pins[] = { 105 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const unsigned int gpio9_pins[] = { 106 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const unsigned int gpio10_pins[] = { 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned int gpio11_pins[] = { 108 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const unsigned int gpio12_pins[] = { 109 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const unsigned int gpio13_pins[] = { 110 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int gpio14_pins[] = { 43 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const unsigned int gpio15_pins[] = { 44 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const unsigned int gpio16_pins[] = { 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned int gpio17_pins[] = { 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int gpio18_pins[] = { 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const unsigned int gpio19_pins[] = { 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const unsigned int gpio20_pins[] = { 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const unsigned int gpio21_pins[] = { 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const unsigned int gpio22_pins[] = { 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const unsigned int gpio23_pins[] = { 52 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const unsigned int gpio24_pins[] = { 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const unsigned int gpio25_pins[] = { 54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const unsigned int gpio26_pins[] = { 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned int gpio27_pins[] = { 56 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const unsigned int gpio28_pins[] = { 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const unsigned int gpio29_pins[] = { 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int gpio30_pins[] = { 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const unsigned int gpio31_pins[] = { 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int gpio32_pins[] = { 61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int gpio33_pins[] = { 62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int gpio34_pins[] = { 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int gpio35_pins[] = { 64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int gpio36_pins[] = { 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int gpio37_pins[] = { 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int gpio38_pins[] = { 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const unsigned int gpio39_pins[] = { 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int gpio40_pins[] = { 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int gpio41_pins[] = { 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int gpio42_pins[] = { 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const unsigned int gpio43_pins[] = { 72 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const unsigned int gpio44_pins[] = { 73 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const unsigned int gpio45_pins[] = { 74 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned int gpio46_pins[] = { 75 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const unsigned int gpio47_pins[] = { 76 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const unsigned int gpio48_pins[] = { 77 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const unsigned int gpio49_pins[] = { 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const unsigned int gpio50_pins[] = { 79 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const unsigned int gpio51_pins[] = { 80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const unsigned int gpio52_pins[] = { 81 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const unsigned int gpio53_pins[] = { 82 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int gpio54_pins[] = { 83 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int gpio55_pins[] = { 84 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int gpio56_pins[] = { 85 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const unsigned int gpio57_pins[] = { 86 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int gpio58_pins[] = { 87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int gpio59_pins[] = { 88 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int gpio60_pins[] = { 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int gpio61_pins[] = { 90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int gpio62_pins[] = { 91 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int gpio63_pins[] = { 92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int gpio64_pins[] = { 93 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned int gpio65_pins[] = { 94 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int gpio66_pins[] = { 95 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int gpio67_pins[] = { 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 52, 53, 54, 55, 56, 57, 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned int i2s0_mclkin_pins[] = { 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned int i2s1_mclkin_pins[] = { 98 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define BM1880_PINCTRL_GRP(nm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = #nm "_grp", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .pins = nm ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .npins = ARRAY_SIZE(nm ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) BM1880_PINCTRL_GRP(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) BM1880_PINCTRL_GRP(spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) BM1880_PINCTRL_GRP(emmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) BM1880_PINCTRL_GRP(sdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BM1880_PINCTRL_GRP(eth0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BM1880_PINCTRL_GRP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) BM1880_PINCTRL_GRP(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) BM1880_PINCTRL_GRP(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BM1880_PINCTRL_GRP(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) BM1880_PINCTRL_GRP(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) BM1880_PINCTRL_GRP(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) BM1880_PINCTRL_GRP(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) BM1880_PINCTRL_GRP(pwm7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) BM1880_PINCTRL_GRP(pwm8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) BM1880_PINCTRL_GRP(pwm9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) BM1880_PINCTRL_GRP(pwm10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BM1880_PINCTRL_GRP(pwm11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BM1880_PINCTRL_GRP(pwm12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BM1880_PINCTRL_GRP(pwm13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BM1880_PINCTRL_GRP(pwm14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) BM1880_PINCTRL_GRP(pwm15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) BM1880_PINCTRL_GRP(pwm16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BM1880_PINCTRL_GRP(pwm17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) BM1880_PINCTRL_GRP(pwm18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) BM1880_PINCTRL_GRP(pwm19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BM1880_PINCTRL_GRP(pwm20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) BM1880_PINCTRL_GRP(pwm21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BM1880_PINCTRL_GRP(pwm22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) BM1880_PINCTRL_GRP(pwm23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) BM1880_PINCTRL_GRP(pwm24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) BM1880_PINCTRL_GRP(pwm25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) BM1880_PINCTRL_GRP(pwm26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BM1880_PINCTRL_GRP(pwm27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) BM1880_PINCTRL_GRP(pwm28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) BM1880_PINCTRL_GRP(pwm29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BM1880_PINCTRL_GRP(pwm30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BM1880_PINCTRL_GRP(pwm31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BM1880_PINCTRL_GRP(pwm32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BM1880_PINCTRL_GRP(pwm33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) BM1880_PINCTRL_GRP(pwm34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) BM1880_PINCTRL_GRP(pwm35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BM1880_PINCTRL_GRP(pwm36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) BM1880_PINCTRL_GRP(pwm37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) BM1880_PINCTRL_GRP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) BM1880_PINCTRL_GRP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) BM1880_PINCTRL_GRP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) BM1880_PINCTRL_GRP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) BM1880_PINCTRL_GRP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) BM1880_PINCTRL_GRP(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) BM1880_PINCTRL_GRP(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BM1880_PINCTRL_GRP(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BM1880_PINCTRL_GRP(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) BM1880_PINCTRL_GRP(uart4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) BM1880_PINCTRL_GRP(uart5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) BM1880_PINCTRL_GRP(uart6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BM1880_PINCTRL_GRP(uart7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BM1880_PINCTRL_GRP(uart8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) BM1880_PINCTRL_GRP(uart9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BM1880_PINCTRL_GRP(uart10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BM1880_PINCTRL_GRP(uart11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BM1880_PINCTRL_GRP(uart12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) BM1880_PINCTRL_GRP(uart13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) BM1880_PINCTRL_GRP(uart14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) BM1880_PINCTRL_GRP(uart15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BM1880_PINCTRL_GRP(gpio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) BM1880_PINCTRL_GRP(gpio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BM1880_PINCTRL_GRP(gpio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BM1880_PINCTRL_GRP(gpio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BM1880_PINCTRL_GRP(gpio4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BM1880_PINCTRL_GRP(gpio5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BM1880_PINCTRL_GRP(gpio6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BM1880_PINCTRL_GRP(gpio7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BM1880_PINCTRL_GRP(gpio8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BM1880_PINCTRL_GRP(gpio9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BM1880_PINCTRL_GRP(gpio10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BM1880_PINCTRL_GRP(gpio11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BM1880_PINCTRL_GRP(gpio12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BM1880_PINCTRL_GRP(gpio13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BM1880_PINCTRL_GRP(gpio14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) BM1880_PINCTRL_GRP(gpio15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) BM1880_PINCTRL_GRP(gpio16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BM1880_PINCTRL_GRP(gpio17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) BM1880_PINCTRL_GRP(gpio18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) BM1880_PINCTRL_GRP(gpio19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BM1880_PINCTRL_GRP(gpio20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) BM1880_PINCTRL_GRP(gpio21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BM1880_PINCTRL_GRP(gpio22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BM1880_PINCTRL_GRP(gpio23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) BM1880_PINCTRL_GRP(gpio24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) BM1880_PINCTRL_GRP(gpio25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BM1880_PINCTRL_GRP(gpio26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) BM1880_PINCTRL_GRP(gpio27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BM1880_PINCTRL_GRP(gpio28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) BM1880_PINCTRL_GRP(gpio29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) BM1880_PINCTRL_GRP(gpio30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BM1880_PINCTRL_GRP(gpio31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BM1880_PINCTRL_GRP(gpio32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) BM1880_PINCTRL_GRP(gpio33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BM1880_PINCTRL_GRP(gpio34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BM1880_PINCTRL_GRP(gpio35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) BM1880_PINCTRL_GRP(gpio36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) BM1880_PINCTRL_GRP(gpio37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) BM1880_PINCTRL_GRP(gpio38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) BM1880_PINCTRL_GRP(gpio39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) BM1880_PINCTRL_GRP(gpio40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BM1880_PINCTRL_GRP(gpio41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) BM1880_PINCTRL_GRP(gpio42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) BM1880_PINCTRL_GRP(gpio43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BM1880_PINCTRL_GRP(gpio44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BM1880_PINCTRL_GRP(gpio45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) BM1880_PINCTRL_GRP(gpio46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) BM1880_PINCTRL_GRP(gpio47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) BM1880_PINCTRL_GRP(gpio48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) BM1880_PINCTRL_GRP(gpio49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) BM1880_PINCTRL_GRP(gpio50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) BM1880_PINCTRL_GRP(gpio51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) BM1880_PINCTRL_GRP(gpio52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BM1880_PINCTRL_GRP(gpio53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) BM1880_PINCTRL_GRP(gpio54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) BM1880_PINCTRL_GRP(gpio55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) BM1880_PINCTRL_GRP(gpio56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) BM1880_PINCTRL_GRP(gpio57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) BM1880_PINCTRL_GRP(gpio58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) BM1880_PINCTRL_GRP(gpio59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) BM1880_PINCTRL_GRP(gpio60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) BM1880_PINCTRL_GRP(gpio61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) BM1880_PINCTRL_GRP(gpio62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) BM1880_PINCTRL_GRP(gpio63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) BM1880_PINCTRL_GRP(gpio64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) BM1880_PINCTRL_GRP(gpio65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BM1880_PINCTRL_GRP(gpio66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) BM1880_PINCTRL_GRP(gpio67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) BM1880_PINCTRL_GRP(eth1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) BM1880_PINCTRL_GRP(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) BM1880_PINCTRL_GRP(i2s0_mclkin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) BM1880_PINCTRL_GRP(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) BM1880_PINCTRL_GRP(i2s1_mclkin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) BM1880_PINCTRL_GRP(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const char * const nand_group[] = { "nand_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const char * const spi_group[] = { "spi_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const char * const emmc_group[] = { "emmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const char * const sdio_group[] = { "sdio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const char * const eth0_group[] = { "eth0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const char * const pwm0_group[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const char * const pwm1_group[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const char * const pwm2_group[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const char * const pwm3_group[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const char * const pwm4_group[] = { "pwm4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const char * const pwm5_group[] = { "pwm5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const char * const pwm6_group[] = { "pwm6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const char * const pwm7_group[] = { "pwm7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const char * const pwm8_group[] = { "pwm8_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const char * const pwm9_group[] = { "pwm9_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const char * const pwm10_group[] = { "pwm10_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const char * const pwm11_group[] = { "pwm11_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const char * const pwm12_group[] = { "pwm12_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const char * const pwm13_group[] = { "pwm13_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const char * const pwm14_group[] = { "pwm14_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const char * const pwm15_group[] = { "pwm15_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const char * const pwm16_group[] = { "pwm16_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const char * const pwm17_group[] = { "pwm17_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const char * const pwm18_group[] = { "pwm18_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const char * const pwm19_group[] = { "pwm19_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char * const pwm20_group[] = { "pwm20_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const char * const pwm21_group[] = { "pwm21_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const char * const pwm22_group[] = { "pwm22_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const char * const pwm23_group[] = { "pwm23_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const char * const pwm24_group[] = { "pwm24_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const char * const pwm25_group[] = { "pwm25_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const char * const pwm26_group[] = { "pwm26_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const char * const pwm27_group[] = { "pwm27_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const char * const pwm28_group[] = { "pwm28_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const char * const pwm29_group[] = { "pwm29_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const char * const pwm30_group[] = { "pwm30_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const char * const pwm31_group[] = { "pwm31_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const char * const pwm32_group[] = { "pwm32_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const char * const pwm33_group[] = { "pwm33_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const char * const pwm34_group[] = { "pwm34_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const char * const pwm35_group[] = { "pwm35_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const char * const pwm36_group[] = { "pwm36_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const char * const pwm37_group[] = { "pwm37_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const char * const i2c0_group[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const char * const i2c1_group[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const char * const i2c2_group[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const char * const i2c3_group[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const char * const i2c4_group[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const uart0_group[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const char * const uart1_group[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const char * const uart2_group[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const char * const uart3_group[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const char * const uart4_group[] = { "uart4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const char * const uart5_group[] = { "uart5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const char * const uart6_group[] = { "uart6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const char * const uart7_group[] = { "uart7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const char * const uart8_group[] = { "uart8_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const char * const uart9_group[] = { "uart9_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const char * const uart10_group[] = { "uart10_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const char * const uart11_group[] = { "uart11_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const char * const uart12_group[] = { "uart12_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const char * const uart13_group[] = { "uart13_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const char * const uart14_group[] = { "uart14_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const char * const uart15_group[] = { "uart15_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const char * const gpio0_group[] = { "gpio0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const char * const gpio1_group[] = { "gpio1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const char * const gpio2_group[] = { "gpio2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const char * const gpio3_group[] = { "gpio3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char * const gpio4_group[] = { "gpio4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const char * const gpio5_group[] = { "gpio5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const gpio6_group[] = { "gpio6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const char * const gpio7_group[] = { "gpio7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const char * const gpio8_group[] = { "gpio8_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const char * const gpio9_group[] = { "gpio9_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const char * const gpio10_group[] = { "gpio10_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const char * const gpio11_group[] = { "gpio11_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const char * const gpio12_group[] = { "gpio12_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const gpio13_group[] = { "gpio13_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const char * const gpio14_group[] = { "gpio14_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const char * const gpio15_group[] = { "gpio15_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const char * const gpio16_group[] = { "gpio16_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const char * const gpio17_group[] = { "gpio17_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const gpio18_group[] = { "gpio18_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const char * const gpio19_group[] = { "gpio19_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const char * const gpio20_group[] = { "gpio20_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const char * const gpio21_group[] = { "gpio21_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const char * const gpio22_group[] = { "gpio22_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const char * const gpio23_group[] = { "gpio23_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const char * const gpio24_group[] = { "gpio24_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const char * const gpio25_group[] = { "gpio25_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const char * const gpio26_group[] = { "gpio26_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const char * const gpio27_group[] = { "gpio27_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const char * const gpio28_group[] = { "gpio28_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const char * const gpio29_group[] = { "gpio29_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char * const gpio30_group[] = { "gpio30_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const char * const gpio31_group[] = { "gpio31_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const char * const gpio32_group[] = { "gpio32_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const char * const gpio33_group[] = { "gpio33_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const char * const gpio34_group[] = { "gpio34_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const gpio35_group[] = { "gpio35_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const char * const gpio36_group[] = { "gpio36_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const char * const gpio37_group[] = { "gpio37_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const char * const gpio38_group[] = { "gpio38_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const char * const gpio39_group[] = { "gpio39_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const char * const gpio40_group[] = { "gpio40_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const gpio41_group[] = { "gpio41_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char * const gpio42_group[] = { "gpio42_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const char * const gpio43_group[] = { "gpio43_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char * const gpio44_group[] = { "gpio44_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const char * const gpio45_group[] = { "gpio45_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const char * const gpio46_group[] = { "gpio46_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char * const gpio47_group[] = { "gpio47_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char * const gpio48_group[] = { "gpio48_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char * const gpio49_group[] = { "gpio49_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const gpio50_group[] = { "gpio50_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char * const gpio51_group[] = { "gpio51_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const char * const gpio52_group[] = { "gpio52_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const gpio53_group[] = { "gpio53_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const char * const gpio54_group[] = { "gpio54_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const gpio55_group[] = { "gpio55_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char * const gpio56_group[] = { "gpio56_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const gpio57_group[] = { "gpio57_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const char * const gpio58_group[] = { "gpio58_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const gpio59_group[] = { "gpio59_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char * const gpio60_group[] = { "gpio60_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const gpio61_group[] = { "gpio61_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char * const gpio62_group[] = { "gpio62_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const gpio63_group[] = { "gpio63_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char * const gpio64_group[] = { "gpio64_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const char * const gpio65_group[] = { "gpio65_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const gpio66_group[] = { "gpio66_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const char * const gpio67_group[] = { "gpio67_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char * const eth1_group[] = { "eth1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const char * const i2s0_group[] = { "i2s0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const i2s1_group[] = { "i2s1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const char * const spi0_group[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define BM1880_PINMUX_FUNCTION(fname, mval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [F_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .groups = fname##_group, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .ngroups = ARRAY_SIZE(fname##_group), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .mux_val = mval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) BM1880_PINMUX_FUNCTION(nand, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) BM1880_PINMUX_FUNCTION(spi, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) BM1880_PINMUX_FUNCTION(emmc, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) BM1880_PINMUX_FUNCTION(sdio, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) BM1880_PINMUX_FUNCTION(eth0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) BM1880_PINMUX_FUNCTION(pwm0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) BM1880_PINMUX_FUNCTION(pwm1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) BM1880_PINMUX_FUNCTION(pwm2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) BM1880_PINMUX_FUNCTION(pwm3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) BM1880_PINMUX_FUNCTION(pwm4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) BM1880_PINMUX_FUNCTION(pwm5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) BM1880_PINMUX_FUNCTION(pwm6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) BM1880_PINMUX_FUNCTION(pwm7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) BM1880_PINMUX_FUNCTION(pwm8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) BM1880_PINMUX_FUNCTION(pwm9, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) BM1880_PINMUX_FUNCTION(pwm10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) BM1880_PINMUX_FUNCTION(pwm11, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) BM1880_PINMUX_FUNCTION(pwm12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) BM1880_PINMUX_FUNCTION(pwm13, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) BM1880_PINMUX_FUNCTION(pwm14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) BM1880_PINMUX_FUNCTION(pwm15, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) BM1880_PINMUX_FUNCTION(pwm16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) BM1880_PINMUX_FUNCTION(pwm17, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) BM1880_PINMUX_FUNCTION(pwm18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) BM1880_PINMUX_FUNCTION(pwm19, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) BM1880_PINMUX_FUNCTION(pwm20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) BM1880_PINMUX_FUNCTION(pwm21, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) BM1880_PINMUX_FUNCTION(pwm22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) BM1880_PINMUX_FUNCTION(pwm23, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) BM1880_PINMUX_FUNCTION(pwm24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) BM1880_PINMUX_FUNCTION(pwm25, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) BM1880_PINMUX_FUNCTION(pwm26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) BM1880_PINMUX_FUNCTION(pwm27, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) BM1880_PINMUX_FUNCTION(pwm28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) BM1880_PINMUX_FUNCTION(pwm29, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) BM1880_PINMUX_FUNCTION(pwm30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) BM1880_PINMUX_FUNCTION(pwm31, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) BM1880_PINMUX_FUNCTION(pwm32, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) BM1880_PINMUX_FUNCTION(pwm33, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) BM1880_PINMUX_FUNCTION(pwm34, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) BM1880_PINMUX_FUNCTION(pwm35, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) BM1880_PINMUX_FUNCTION(pwm36, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) BM1880_PINMUX_FUNCTION(pwm37, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) BM1880_PINMUX_FUNCTION(i2c0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) BM1880_PINMUX_FUNCTION(i2c1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) BM1880_PINMUX_FUNCTION(i2c2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) BM1880_PINMUX_FUNCTION(i2c3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) BM1880_PINMUX_FUNCTION(i2c4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) BM1880_PINMUX_FUNCTION(uart0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) BM1880_PINMUX_FUNCTION(uart1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) BM1880_PINMUX_FUNCTION(uart2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) BM1880_PINMUX_FUNCTION(uart3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) BM1880_PINMUX_FUNCTION(uart4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) BM1880_PINMUX_FUNCTION(uart5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) BM1880_PINMUX_FUNCTION(uart6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) BM1880_PINMUX_FUNCTION(uart7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) BM1880_PINMUX_FUNCTION(uart8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) BM1880_PINMUX_FUNCTION(uart9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) BM1880_PINMUX_FUNCTION(uart10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) BM1880_PINMUX_FUNCTION(uart11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) BM1880_PINMUX_FUNCTION(uart12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) BM1880_PINMUX_FUNCTION(uart13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) BM1880_PINMUX_FUNCTION(uart14, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) BM1880_PINMUX_FUNCTION(uart15, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) BM1880_PINMUX_FUNCTION(gpio0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BM1880_PINMUX_FUNCTION(gpio1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BM1880_PINMUX_FUNCTION(gpio2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BM1880_PINMUX_FUNCTION(gpio3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BM1880_PINMUX_FUNCTION(gpio4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) BM1880_PINMUX_FUNCTION(gpio5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) BM1880_PINMUX_FUNCTION(gpio6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) BM1880_PINMUX_FUNCTION(gpio7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) BM1880_PINMUX_FUNCTION(gpio8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) BM1880_PINMUX_FUNCTION(gpio9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) BM1880_PINMUX_FUNCTION(gpio10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) BM1880_PINMUX_FUNCTION(gpio11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) BM1880_PINMUX_FUNCTION(gpio12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) BM1880_PINMUX_FUNCTION(gpio13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) BM1880_PINMUX_FUNCTION(gpio14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) BM1880_PINMUX_FUNCTION(gpio15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) BM1880_PINMUX_FUNCTION(gpio16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) BM1880_PINMUX_FUNCTION(gpio17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) BM1880_PINMUX_FUNCTION(gpio18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) BM1880_PINMUX_FUNCTION(gpio19, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) BM1880_PINMUX_FUNCTION(gpio20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) BM1880_PINMUX_FUNCTION(gpio21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) BM1880_PINMUX_FUNCTION(gpio22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) BM1880_PINMUX_FUNCTION(gpio23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) BM1880_PINMUX_FUNCTION(gpio24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) BM1880_PINMUX_FUNCTION(gpio25, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) BM1880_PINMUX_FUNCTION(gpio26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) BM1880_PINMUX_FUNCTION(gpio27, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) BM1880_PINMUX_FUNCTION(gpio28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) BM1880_PINMUX_FUNCTION(gpio29, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) BM1880_PINMUX_FUNCTION(gpio30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) BM1880_PINMUX_FUNCTION(gpio31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) BM1880_PINMUX_FUNCTION(gpio32, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) BM1880_PINMUX_FUNCTION(gpio33, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) BM1880_PINMUX_FUNCTION(gpio34, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) BM1880_PINMUX_FUNCTION(gpio35, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) BM1880_PINMUX_FUNCTION(gpio36, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) BM1880_PINMUX_FUNCTION(gpio37, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) BM1880_PINMUX_FUNCTION(gpio38, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) BM1880_PINMUX_FUNCTION(gpio39, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) BM1880_PINMUX_FUNCTION(gpio40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) BM1880_PINMUX_FUNCTION(gpio41, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) BM1880_PINMUX_FUNCTION(gpio42, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) BM1880_PINMUX_FUNCTION(gpio43, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) BM1880_PINMUX_FUNCTION(gpio44, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) BM1880_PINMUX_FUNCTION(gpio45, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) BM1880_PINMUX_FUNCTION(gpio46, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) BM1880_PINMUX_FUNCTION(gpio47, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) BM1880_PINMUX_FUNCTION(gpio48, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) BM1880_PINMUX_FUNCTION(gpio49, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) BM1880_PINMUX_FUNCTION(gpio50, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BM1880_PINMUX_FUNCTION(gpio51, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) BM1880_PINMUX_FUNCTION(gpio52, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) BM1880_PINMUX_FUNCTION(gpio53, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) BM1880_PINMUX_FUNCTION(gpio54, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) BM1880_PINMUX_FUNCTION(gpio55, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) BM1880_PINMUX_FUNCTION(gpio56, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) BM1880_PINMUX_FUNCTION(gpio57, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) BM1880_PINMUX_FUNCTION(gpio58, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) BM1880_PINMUX_FUNCTION(gpio59, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BM1880_PINMUX_FUNCTION(gpio60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) BM1880_PINMUX_FUNCTION(gpio61, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) BM1880_PINMUX_FUNCTION(gpio62, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) BM1880_PINMUX_FUNCTION(gpio63, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) BM1880_PINMUX_FUNCTION(gpio64, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) BM1880_PINMUX_FUNCTION(gpio65, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) BM1880_PINMUX_FUNCTION(gpio66, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) BM1880_PINMUX_FUNCTION(gpio67, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) BM1880_PINMUX_FUNCTION(eth1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) BM1880_PINMUX_FUNCTION(i2s0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) BM1880_PINMUX_FUNCTION(i2s1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) BM1880_PINMUX_FUNCTION(spi0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define BM1880_PINCONF_DAT(_width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .drv_bits = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct bm1880_pinconf_data bm1880_pinconf[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) BM1880_PINCONF_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) BM1880_PINCONF_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return pctrl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return pctrl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) *pins = pctrl->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) *num_pins = pctrl->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const struct pinctrl_ops bm1880_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .get_groups_count = bm1880_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .get_group_name = bm1880_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .get_group_pins = bm1880_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return pctrl->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return pctrl->funcs[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *groups = pctrl->funcs[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *num_groups = pctrl->funcs[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) for (i = 0; i < pgrp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned int pin = pgrp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 offset = (pin >> 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) regval &= ~(0x03 << mux_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) regval |= func->mux_val << mux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u32 *regval, u32 bit_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 _regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) _regval = *regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * There are two sets of drive strength bit width exposed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * SoC at 4mA step, hence we need to handle them separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (width == 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) switch (mA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) _regval |= (0 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) _regval |= (1 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) _regval |= (2 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) _regval |= (3 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) _regval |= (4 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) _regval |= (5 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case 28:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) _regval |= (6 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) _regval |= (7 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) switch (mA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) _regval |= (0 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) _regval |= (1 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) _regval |= (2 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) _regval &= ~(width << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) _regval |= (3 << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *regval = _regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int bm1880_pinconf_drv_get(u32 width, u32 drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * There are two sets of drive strength bit width exposed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * SoC at 4mA step, hence we need to handle them separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (width == 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) switch (drv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) switch (drv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) unsigned int arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u32 regval, offset, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) offset = (pin >> 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) bit_offset = BM1880_PINCONF_PULLUP(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) arg = !!(regval & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) bit_offset = BM1880_PINCONF_PULLDOWN(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) arg = !!(regval & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) bit_offset = BM1880_PINCONF_PULLCTRL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) arg = !!(regval & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) bit_offset = BM1880_PINCONF_SCHMITT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) arg = !!(regval & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) bit_offset = BM1880_PINCONF_SLEW(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) arg = !!(regval & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) bit_offset = BM1880_PINCONF_DRV(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) !!(regval & BIT(bit_offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) arg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u32 regval, offset, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) offset = (pin >> 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) unsigned int param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) unsigned int arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) bit_offset = BM1880_PINCONF_PULLUP(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) regval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bit_offset = BM1880_PINCONF_PULLDOWN(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) regval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) bit_offset = BM1880_PINCONF_PULLCTRL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) regval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) bit_offset = BM1880_PINCONF_SCHMITT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) regval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) regval &= ~BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) bit_offset = BM1880_PINCONF_SLEW(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) regval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) regval &= ~BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bit_offset = BM1880_PINCONF_DRV(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = bm1880_pinconf_drv_set(arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pctrl->pinconf[pin].drv_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ®val, bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_warn(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) "unsupported configuration parameter '%u'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) for (i = 0; i < pgrp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct pinconf_ops bm1880_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .pin_config_get = bm1880_pinconf_cfg_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .pin_config_set = bm1880_pinconf_cfg_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .pin_config_group_set = bm1880_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static const struct pinmux_ops bm1880_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .get_functions_count = bm1880_pmux_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .get_function_name = bm1880_pmux_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .get_function_groups = bm1880_pmux_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .set_mux = bm1880_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static struct pinctrl_desc bm1880_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .name = "bm1880_pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .pins = bm1880_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .npins = ARRAY_SIZE(bm1880_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .pctlops = &bm1880_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .pmxops = &bm1880_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .confops = &bm1880_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int bm1880_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct bm1880_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) pctrl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (IS_ERR(pctrl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return PTR_ERR(pctrl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pctrl->groups = bm1880_pctrl_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pctrl->funcs = bm1880_pmux_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pctrl->pinconf = bm1880_pinconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(pctrl->pctrldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return PTR_ERR(pctrl->pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) platform_set_drvdata(pdev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const struct of_device_id bm1880_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { .compatible = "bitmain,bm1880-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static struct platform_driver bm1880_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .name = "pinctrl-bm1880",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .probe = bm1880_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int __init bm1880_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return platform_driver_register(&bm1880_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) arch_initcall(bm1880_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags