^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005 Ivan Kokshaysky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Parallel I/O Controller (PIO) - System peripherals registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __PINCTRL_AT91_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __PINCTRL_AT91_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PIO_PER 0x00 /* Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PIO_PDR 0x04 /* Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PIO_PSR 0x08 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIO_OER 0x10 /* Output Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PIO_ODR 0x14 /* Output Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PIO_OSR 0x18 /* Output Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIO_SODR 0x30 /* Set Output Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PIO_CODR 0x34 /* Clear Output Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PIO_ODSR 0x38 /* Output Data Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIO_PDSR 0x3c /* Pin Data Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIO_IER 0x40 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PIO_IDR 0x44 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIO_IMR 0x48 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIO_ISR 0x4c /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PIO_MDER 0x50 /* Multi-driver Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PIO_MDSR 0x58 /* Multi-driver Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIO_PUDR 0x60 /* Pull-up Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PIO_PUER 0x64 /* Pull-up Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PIO_PUSR 0x68 /* Pull-up Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PIO_ASR 0x70 /* Peripheral A Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PIO_BSR 0x74 /* Peripheral B Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIO_ABSR 0x78 /* AB Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIO_OWER 0xa0 /* Output Write Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIO_OWDR 0xa4 /* Output Write Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIO_OWSR 0xa8 /* Output Write Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PIO_ESR 0xc0 /* Edge Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PIO_LSR 0xc4 /* Level Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PIO_ELSR 0xc8 /* Edge/Level Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SAM9X60_PIO_SLEWR 0x110 /* PIO Slew Rate Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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