^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at91 pinctrl driver based on at91 pinmux core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Since we request GPIOs from ourself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinctrl-at91.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_GPIO_BANKS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_NB_GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct at91_pinctrl_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct at91_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pinctrl_gpio_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct at91_gpio_chip *next; /* Bank sharing same clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int pioc_virq; /* PIO bank Linux virtual interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int pioc_idx; /* PIO bank index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *regbase; /* PIO bank virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *clock; /* associated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct at91_pinctrl_mux_ops *ops; /* ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PULL_UP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MULTI_DRIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DEGLITCH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PULL_DOWN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DIS_SCHMIT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRIVE_STRENGTH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRIVE_STRENGTH_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OUTPUT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OUTPUT_VAL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLEWRATE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLEWRATE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEBOUNCE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEBOUNCE_VAL_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * These defines will translated the dt binding settings to our internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * settings. They are not necessarily the same value as the register setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * The actual drive strength current of low, medium and high must be looked up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * from the corresponding device datasheet. This value is different for pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * that are even in the same banks. It is also dependent on VCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * strength when there is no dt config for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum drive_strength_bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DRIVE_STRENGTH_BIT_DEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DRIVE_STRENGTH_BIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DRIVE_STRENGTH_BIT_MED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DRIVE_STRENGTH_BIT_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DRIVE_STRENGTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum slewrate_bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SLEWRATE_BIT_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SLEWRATE_BIT_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct at91_pmx_func - describes AT91 pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @name: the name of this specific function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @groups: corresponding pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @ngroups: the number of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct at91_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum at91_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AT91_MUX_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AT91_MUX_PERIPH_A = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AT91_MUX_PERIPH_B = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AT91_MUX_PERIPH_C = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AT91_MUX_PERIPH_D = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * struct at91_pmx_pin - describes an At91 pin mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @bank: the bank of the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @pin: the pin number in the @bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct at91_pmx_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint32_t bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint32_t pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum at91_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * struct at91_pin_group - describes an At91 pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @pins_conf: the mux mode for each pin in this group. The size of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * array is the same as pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @pins: an array of discrete physical pins used in this group, taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * from the driver-local pin enumeration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @npins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct at91_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct at91_pmx_pin *pins_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * on new IP with support for periph C and D the way to mux in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * periph A and B has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * So provide the right call back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * if not present means the IP does not support it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @get_periph: return the periph mode configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @mux_A_periph: mux as periph A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @mux_B_periph: mux as periph B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @mux_C_periph: mux as periph C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @mux_D_periph: mux as periph D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @get_deglitch: get deglitch status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @set_deglitch: enable/disable deglitch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @get_debounce: get debounce status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @set_debounce: enable/disable debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @get_pulldown: get pulldown status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @set_pulldown: enable/disable pulldown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @get_schmitt_trig: get schmitt trigger status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @disable_schmitt_trig: disable schmitt trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @get_drivestrength: get driver strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @set_drivestrength: set driver strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @get_slewrate: get slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @set_slewrate: set slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @irq_type: return irq type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct at91_pinctrl_mux_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void (*mux_A_periph)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void (*mux_B_periph)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void (*mux_C_periph)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void (*mux_D_periph)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool (*get_deglitch)(void __iomem *pio, unsigned pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool (*get_pulldown)(void __iomem *pio, unsigned pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void (*set_drivestrength)(void __iomem *pio, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int (*irq_type)(struct irq_data *d, unsigned type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int gpio_irq_type(struct irq_data *d, unsigned type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct at91_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int nactive_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint32_t *mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int nmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct at91_pmx_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct at91_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct at91_pinctrl_mux_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const struct at91_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct at91_pin_group *grp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < info->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (strcmp(info->groups[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) grp = &info->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int at91_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return info->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *pins = info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *npins = info->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) seq_printf(s, "%s", dev_name(pctldev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const struct at91_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct pinctrl_map *new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int map_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * first find the group of this node and check if we need to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * config maps for pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) grp = at91_pinctrl_find_group_by_name(info, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(info->dev, "unable to find group for node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) map_num += grp->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!new_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *map = new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *num_maps = map_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* create mux map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) parent = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) devm_kfree(pctldev->dev, new_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) new_map[0].data.mux.function = parent->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) new_map[0].data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* create config map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) new_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) new_map[i].data.configs.group_or_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pin_get_name(pctldev, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) new_map[i].data.configs.num_configs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (*map)->data.mux.function, (*map)->data.mux.group, map_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void at91_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct pinctrl_ops at91_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .get_groups_count = at91_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .get_group_name = at91_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .get_group_pins = at91_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .pin_dbg_show = at91_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .dt_node_to_map = at91_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .dt_free_map = at91_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __iomem *pin_to_controller(struct at91_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!gpio_chips[bank])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return gpio_chips[bank]->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline int pin_to_bank(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return pin /= MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static unsigned pin_to_mask(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 1 << pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* return the shift value for a pin for "two bit" per pin registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * i.e. drive strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static unsigned sama5d3_get_drive_register(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* drive strength is split between two registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * with two bits per pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return (pin >= MAX_NB_GPIO_PER_BANK/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static unsigned at91sam9x5_get_drive_register(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* drive strength is split between two registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * with two bits per pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return (pin >= MAX_NB_GPIO_PER_BANK/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel_relaxed(mask, pio + PIO_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel_relaxed(mask, pio + PIO_PPDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bool is_on, bool val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writel_relaxed(mask, pio + PIO_ASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writel_relaxed(mask, pio + PIO_BSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pio + PIO_ABCDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pio + PIO_ABCDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pio + PIO_ABCDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pio + PIO_ABCDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (readl_relaxed(pio + PIO_PSR) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return AT91_MUX_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return select + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (readl_relaxed(pio + PIO_PSR) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return AT91_MUX_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) select = readl_relaxed(pio + PIO_ABSR) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return select + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel_relaxed(mask, pio + PIO_IFSCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) at91_mux_set_deglitch(pio, mask, is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *div = readl_relaxed(pio + PIO_SCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bool is_on, u32 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel_relaxed(mask, pio + PIO_IFSCER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel_relaxed(mask, pio + PIO_IFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel_relaxed(mask, pio + PIO_IFSCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel_relaxed(mask, pio + PIO_PUDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned tmp = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tmp = tmp >> two_bit_pin_value_shift_amount(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return tmp & DRIVE_STRENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned tmp = read_drive_strength(pio +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sama5d3_get_drive_register(pin), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* SAMA5 strength is 1:1 with our defines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * except 0 is equivalent to low per datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned tmp = read_drive_strength(pio +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) at91sam9x5_get_drive_register(pin), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* strength is inverse in SAM9x5s hardware with the pinctrl defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (tmp & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return DRIVE_STRENGTH_BIT_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return DRIVE_STRENGTH_BIT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if ((tmp & BIT(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return SLEWRATE_BIT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return SLEWRATE_BIT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned tmp = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned shift = two_bit_pin_value_shift_amount(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tmp &= ~(DRIVE_STRENGTH_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tmp |= strength << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) writel_relaxed(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* do nothing if setting is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* strength is 1 to 1 with setting for SAMA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* do nothing if setting is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* strength is inverse on SAM9x5s with our defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (setting <= DRIVE_STRENGTH_BIT_DEF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) setting == DRIVE_STRENGTH_BIT_MED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) setting > DRIVE_STRENGTH_BIT_HI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Strength is 0: low, 1: hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (setting == DRIVE_STRENGTH_BIT_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) tmp &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) tmp |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (setting == SLEWRATE_BIT_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tmp &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) tmp |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static struct at91_pinctrl_mux_ops at91rm9200_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .get_periph = at91_mux_get_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .mux_A_periph = at91_mux_set_A_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .mux_B_periph = at91_mux_set_B_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .get_deglitch = at91_mux_get_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .set_deglitch = at91_mux_set_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .irq_type = gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .get_periph = at91_mux_pio3_get_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .mux_A_periph = at91_mux_pio3_set_A_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .mux_B_periph = at91_mux_pio3_set_B_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .mux_C_periph = at91_mux_pio3_set_C_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .mux_D_periph = at91_mux_pio3_set_D_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .get_deglitch = at91_mux_pio3_get_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .set_deglitch = at91_mux_pio3_set_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .get_debounce = at91_mux_pio3_get_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .set_debounce = at91_mux_pio3_set_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .get_pulldown = at91_mux_pio3_get_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .set_pulldown = at91_mux_pio3_set_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .irq_type = alt_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct at91_pinctrl_mux_ops sam9x60_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .get_periph = at91_mux_pio3_get_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .mux_A_periph = at91_mux_pio3_set_A_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .mux_B_periph = at91_mux_pio3_set_B_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .mux_C_periph = at91_mux_pio3_set_C_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .mux_D_periph = at91_mux_pio3_set_D_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .get_deglitch = at91_mux_pio3_get_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .set_deglitch = at91_mux_pio3_set_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .get_debounce = at91_mux_pio3_get_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .set_debounce = at91_mux_pio3_set_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .get_pulldown = at91_mux_pio3_get_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .set_pulldown = at91_mux_pio3_set_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .get_slewrate = at91_mux_sam9x60_get_slewrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .set_slewrate = at91_mux_sam9x60_set_slewrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .irq_type = alt_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static struct at91_pinctrl_mux_ops sama5d3_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .get_periph = at91_mux_pio3_get_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .mux_A_periph = at91_mux_pio3_set_A_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .mux_B_periph = at91_mux_pio3_set_B_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .mux_C_periph = at91_mux_pio3_set_C_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .mux_D_periph = at91_mux_pio3_set_D_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .get_deglitch = at91_mux_pio3_get_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .set_deglitch = at91_mux_pio3_set_deglitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .get_debounce = at91_mux_pio3_get_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .set_debounce = at91_mux_pio3_set_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .get_pulldown = at91_mux_pio3_get_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .set_pulldown = at91_mux_pio3_set_pulldown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .irq_type = alt_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (pin->mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pin->bank + 'A', pin->pin, pin->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int pin_check_config(struct at91_pinctrl *info, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int index, const struct at91_pmx_pin *pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* check if it's a valid config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (pin->bank >= gpio_banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) name, index, pin->bank, gpio_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!gpio_chips[pin->bank]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) name, index, pin->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!pin->mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mux = pin->mux - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (mux >= info->nmux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) name, index, mux, info->nmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) name, index, mux, pin->bank + 'A', pin->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) writel_relaxed(mask, pio + PIO_PDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) writel_relaxed(mask, pio + PIO_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) const struct at91_pmx_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uint32_t npins = info->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_dbg(info->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) info->functions[selector].name, info->groups[group].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* first check that all the pins of the group are valid with a valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pin = &pins_conf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = pin_check_config(info, info->groups[group].name, i, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pin = &pins_conf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) at91_pin_dbg(info->dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pio = pin_to_controller(info, pin->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mask = pin_to_mask(pin->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) at91_mux_disable_interrupt(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) switch (pin->mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case AT91_MUX_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) at91_mux_gpio_enable(pio, mask, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case AT91_MUX_PERIPH_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) info->ops->mux_A_periph(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case AT91_MUX_PERIPH_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) info->ops->mux_B_periph(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case AT91_MUX_PERIPH_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!info->ops->mux_C_periph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) info->ops->mux_C_periph(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case AT91_MUX_PERIPH_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!info->ops->mux_D_periph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) info->ops->mux_D_periph(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (pin->mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) at91_mux_gpio_disable(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return info->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return info->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *groups = info->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *num_groups = info->functions[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct at91_gpio_chip *at91_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_err(npct->dev, "invalid range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!range->gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_err(npct->dev, "missing GPIO chip in range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) chip = range->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) at91_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mask = 1 << (offset - chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) offset, 'A' + range->id, offset - chip->base, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) writel_relaxed(mask, at91_chip->regbase + PIO_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Set the pin to some default state, GPIO is usually default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const struct pinmux_ops at91_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .get_functions_count = at91_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .get_function_name = at91_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .get_function_groups = at91_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .set_mux = at91_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .gpio_request_enable = at91_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .gpio_disable_free = at91_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int at91_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned pin_id, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) bool out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pio = pin_to_controller(info, pin_to_bank(pin_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) pin = pin_id % MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (at91_mux_get_multidrive(pio, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) *config |= MULTI_DRIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (at91_mux_get_pullup(pio, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *config |= PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) *config |= DEGLITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *config |= PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) *config |= DIS_SCHMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (info->ops->get_drivestrength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) *config |= (info->ops->get_drivestrength(pio, pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) << DRIVE_STRENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (info->ops->get_slewrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (at91_mux_get_output(pio, pin, &out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int at91_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned pin_id, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) config = configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_dbg(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "%s:%d, pin_id=%d, config=0x%lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __func__, __LINE__, pin_id, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pio = pin_to_controller(info, pin_to_bank(pin_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pin = pin_id % MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mask = pin_to_mask(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (config & PULL_UP && config & PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) at91_mux_set_output(pio, mask, config & OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) at91_mux_set_pullup(pio, mask, config & PULL_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (info->ops->set_deglitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) info->ops->set_deglitch(pio, mask, config & DEGLITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (info->ops->set_debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) info->ops->set_debounce(pio, mask, config & DEBOUNCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (info->ops->set_pulldown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) info->ops->disable_schmitt_trig(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (info->ops->set_drivestrength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) info->ops->set_drivestrength(pio, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) (config & DRIVE_STRENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) >> DRIVE_STRENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (info->ops->set_slewrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) info->ops->set_slewrate(pio, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) (config & SLEWRATE) >> SLEWRATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define DBG_SHOW_FLAG(flag) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (config & flag) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (num_conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) seq_puts(s, "|"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) seq_puts(s, #flag); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) num_conf++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if ((config & mask) == flag) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (num_conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) seq_puts(s, "|"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) seq_puts(s, #name); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) num_conf++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct seq_file *s, unsigned pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int val, num_conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) at91_pinconf_get(pctldev, pin_id, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) DBG_SHOW_FLAG(MULTI_DRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) DBG_SHOW_FLAG(PULL_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) DBG_SHOW_FLAG(PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) DBG_SHOW_FLAG(DIS_SCHMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) DBG_SHOW_FLAG(DEGLITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) DRIVE_STRENGTH_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) DRIVE_STRENGTH_MED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) DRIVE_STRENGTH_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DBG_SHOW_FLAG(SLEWRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) DBG_SHOW_FLAG(DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (config & DEBOUNCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val = config >> DEBOUNCE_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) seq_printf(s, "(%d)", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct seq_file *s, unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static const struct pinconf_ops at91_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .pin_config_get = at91_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .pin_config_set = at91_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .pin_config_dbg_show = at91_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static struct pinctrl_desc at91_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .pctlops = &at91_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .pmxops = &at91_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .confops = &at91_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const char *gpio_compat = "atmel,at91rm9200-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static void at91_pinctrl_child_count(struct at91_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (of_device_is_compatible(child, gpio_compat)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (of_device_is_available(child))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) info->nactive_banks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) info->nfunctions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) info->ngroups += of_get_child_count(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) list = of_get_property(np, "atmel,mux-mask", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(info->dev, "can not read the mux-mask of %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) size /= sizeof(*list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (!size || size % gpio_banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) info->nmux = size / gpio_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!info->mux_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = of_property_read_u32_array(np, "atmel,mux-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) info->mux_mask, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_err(info->dev, "can not read the mux-mask of %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int at91_pinctrl_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct at91_pin_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct at91_pinctrl *info, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct at91_pmx_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Initialise group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * do sanity check and calculate pins number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) list = of_get_property(np, "atmel,pins", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* we do not check return since it's safe node passed down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) size /= sizeof(*list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!size || size % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) grp->npins = size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pin = grp->pins_conf = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) grp->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) sizeof(struct at91_pmx_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!grp->pins_conf || !grp->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) for (i = 0, j = 0; i < size; i += 4, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pin->bank = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pin->pin = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) pin->mux = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) pin->conf = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) at91_pin_dbg(info->dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int at91_pinctrl_parse_functions(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct at91_pinctrl *info, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct at91_pmx_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct at91_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static u32 grp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) func = &info->functions[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Initialise function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) func->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) func->ngroups = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (func->ngroups == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_err(info->dev, "no groups defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) func->groups = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) func->ngroups, sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) func->groups[i] = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) grp = &info->groups[grp_index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = at91_pinctrl_parse_groups(child, grp, info, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct of_device_id at91_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int at91_pinctrl_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct at91_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) uint32_t *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) info->ops = (struct at91_pinctrl_mux_ops *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) at91_pinctrl_child_count(info, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (gpio_banks < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = at91_pinctrl_mux_mask(info, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_dbg(&pdev->dev, "mux-mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) tmp = info->mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) for (i = 0; i < gpio_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) for (j = 0; j < info->nmux; j++, tmp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) info->functions = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) info->nfunctions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sizeof(struct at91_pmx_func),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!info->functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) info->groups = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) info->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) sizeof(struct at91_pin_group),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!info->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (of_device_is_compatible(child, gpio_compat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret = at91_pinctrl_parse_functions(child, info, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) dev_err(&pdev->dev, "failed to parse function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static int at91_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct at91_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct pinctrl_pin_desc *pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int ret, i, j, k, ngpio_chips_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = at91_pinctrl_probe_dt(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * We need all the GPIO drivers to probe FIRST, or we will not be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * to obtain references to the struct gpio_chip * for them, and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * need this to proceed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) for (i = 0; i < gpio_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (gpio_chips[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ngpio_chips_enabled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ngpio_chips_enabled < info->nactive_banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) "All GPIO chips are not registered yet (%d/%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ngpio_chips_enabled, info->nactive_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) devm_kfree(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) at91_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) at91_pinctrl_desc.pins = pdesc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) at91_pinctrl_desc.npins, sizeof(*pdesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!at91_pinctrl_desc.pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) for (i = 0, k = 0; i < gpio_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pdesc->number = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) pdesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (IS_ERR(info->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return PTR_ERR(info->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* We will handle a range of GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) for (i = 0; i < gpio_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (gpio_chips[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) unsigned mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u32 osr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) osr = readl_relaxed(pio + PIO_OSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (osr & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) unsigned mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) writel_relaxed(mask, pio + PIO_ODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) unsigned mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 pdsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) pdsr = readl_relaxed(pio + PIO_PDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return (pdsr & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) unsigned mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static void at91_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) writel_relaxed(set_mask, pio + PIO_SODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) writel_relaxed(clear_mask, pio + PIO_CODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) unsigned mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) writel_relaxed(mask, pio + PIO_OER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) enum at91_mux mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) const char *gpio_label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) for_each_requested_gpio(chip, i, gpio_label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) unsigned mask = pin_to_mask(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mode = at91_gpio->ops->get_periph(pio, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) seq_printf(s, "[%s] GPIO%s%d: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) gpio_label, chip->label, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (mode == AT91_MUX_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) seq_printf(s, "[gpio] ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) seq_printf(s, "%s ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) readl_relaxed(pio + PIO_OSR) & mask ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) "output" : "input");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) seq_printf(s, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) readl_relaxed(pio + PIO_PDSR) & mask ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) "set" : "clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) seq_printf(s, "[periph %c]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) mode + 'A' - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define at91_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* Several AIC controller irqs are dispatched through this GPIO handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * To use any AT91_PIN_* as an externally triggered IRQ, first call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * at91_set_gpio_input() then maybe enable its glitch filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * Then just request_irq() with the pin ID; it works like any ARM IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * First implementation always triggers on rising and falling edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * whereas the newer PIO3 can be additionally configured to trigger on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * level, edge with any polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * configuring them with at91_set_a_periph() or at91_set_b_periph().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static void gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) unsigned mask = 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) writel_relaxed(mask, pio + PIO_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) unsigned mask = 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) writel_relaxed(mask, pio + PIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int gpio_irq_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Alternate irq type for PIO3 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) unsigned mask = 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) irq_set_handler_locked(d, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) writel_relaxed(mask, pio + PIO_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) writel_relaxed(mask, pio + PIO_REHLSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) irq_set_handler_locked(d, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) writel_relaxed(mask, pio + PIO_ESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) writel_relaxed(mask, pio + PIO_FELLSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) writel_relaxed(mask, pio + PIO_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) writel_relaxed(mask, pio + PIO_FELLSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) writel_relaxed(mask, pio + PIO_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) writel_relaxed(mask, pio + PIO_REHLSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * disable additional interrupt modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * fall back to default behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) irq_set_handler_locked(d, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) writel_relaxed(mask, pio + PIO_AIMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* enable additional interrupt modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) writel_relaxed(mask, pio + PIO_AIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static void gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* the interrupt is already cleared before by reading ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static u32 wakeups[MAX_GPIO_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static u32 backups[MAX_GPIO_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) unsigned bank = at91_gpio->pioc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) unsigned mask = 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (unlikely(bank >= MAX_GPIO_BANKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) wakeups[bank] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) wakeups[bank] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) irq_set_irq_wake(at91_gpio->pioc_virq, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) void at91_pinctrl_gpio_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) for (i = 0; i < gpio_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (!gpio_chips[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) pio = gpio_chips[i]->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) backups[i] = readl_relaxed(pio + PIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) writel_relaxed(backups[i], pio + PIO_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) writel_relaxed(wakeups[i], pio + PIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (!wakeups[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) clk_disable_unprepare(gpio_chips[i]->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) 'A'+i, wakeups[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) void at91_pinctrl_gpio_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) for (i = 0; i < gpio_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!gpio_chips[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) pio = gpio_chips[i]->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (!wakeups[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) clk_prepare_enable(gpio_chips[i]->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) writel_relaxed(wakeups[i], pio + PIO_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) writel_relaxed(backups[i], pio + PIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define gpio_irq_set_wake NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static void gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) void __iomem *pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) unsigned long isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* Reading ISR acks pending (edge triggered) GPIO interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * When there are none pending, we're finished unless we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * to process multiple banks (like ID_PIOCDE on sam9263).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (!isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (!at91_gpio->next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) at91_gpio = at91_gpio->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) pio = at91_gpio->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) gpio_chip = &at91_gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) for_each_set_bit(n, &isr, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) generic_handle_irq(irq_find_mapping(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) gpio_chip->irq.domain, n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* now it may re-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int at91_gpio_of_irq_setup(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct at91_gpio_chip *at91_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct gpio_chip *gpiochip_prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct at91_gpio_chip *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct irq_chip *gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (!gpio_irqchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) gpio_irqchip->name = "GPIO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) gpio_irqchip->irq_ack = gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) gpio_irqchip->irq_disable = gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) gpio_irqchip->irq_mask = gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) gpio_irqchip->irq_unmask = gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* Disable irqs of this PIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Let the generic code handle this edge IRQ, the the chained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * handler will perform the actual work of handling the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) girq = &at91_gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) girq->chip = gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * The top level handler handles one bank of GPIOs, except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * on some SoC it can handle up to three...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * We only set up the handler for the first of the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (!gpiochip_prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) girq->parent_handler = gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) girq->parents[0] = at91_gpio->pioc_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) prev = gpiochip_get_data(gpiochip_prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* we can only have 2 banks before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (prev->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) prev = prev->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) prev->next = at91_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* This structure is replicated for each GPIO block allocated at probe time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const struct gpio_chip at91_gpio_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .get_direction = at91_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .direction_input = at91_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .get = at91_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .direction_output = at91_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .set = at91_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .set_multiple = at91_gpio_set_multiple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .dbg_show = at91_gpio_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .can_sleep = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .ngpio = MAX_NB_GPIO_PER_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static const struct of_device_id at91_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static int at91_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct at91_gpio_chip *at91_chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) int irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) int alias_idx = of_alias_get_id(np, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) uint32_t ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) char **names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (gpio_chips[alias_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (!at91_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (IS_ERR(at91_chip->regbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ret = PTR_ERR(at91_chip->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) at91_chip->ops = (struct at91_pinctrl_mux_ops *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) of_match_device(at91_gpio_of_match, &pdev->dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) at91_chip->pioc_virq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) at91_chip->pioc_idx = alias_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (IS_ERR(at91_chip->clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ret = PTR_ERR(at91_chip->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ret = clk_prepare_enable(at91_chip->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) goto clk_enable_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) at91_chip->chip = at91_gpio_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) chip = &at91_chip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) chip->label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) chip->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (ngpio >= MAX_NB_GPIO_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) chip->ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (!names) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) goto clk_enable_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) for (i = 0; i < chip->ngpio; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) chip->names = (const char *const *)names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) range = &at91_chip->range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) range->name = chip->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) range->id = alias_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) range->npins = chip->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) range->gc = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ret = at91_gpio_of_irq_setup(pdev, at91_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) goto gpiochip_add_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ret = gpiochip_add_data(chip, at91_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) goto gpiochip_add_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) gpio_chips[alias_idx] = at91_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) gpio_banks = max(gpio_banks, alias_idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) gpiochip_add_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) clk_enable_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) clk_disable_unprepare(at91_chip->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static struct platform_driver at91_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .name = "gpio-at91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .of_match_table = at91_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .probe = at91_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static struct platform_driver at91_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .name = "pinctrl-at91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .of_match_table = at91_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .probe = at91_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) &at91_gpio_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) &at91_pinctrl_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static int __init at91_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) arch_initcall(at91_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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