^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Atmel PIO4 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Atmel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/pinctrl/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Warning:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * In order to not introduce confusion between Atmel PIO groups and pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * framework groups, Atmel PIO groups will be called banks, line is kept to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * designed the pin id into this bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATMEL_PIO_MSKR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ATMEL_PIO_CFGR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ATMEL_PIO_DIR_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ATMEL_PIO_PUEN_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ATMEL_PIO_PDEN_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ATMEL_PIO_IFEN_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ATMEL_PIO_IFSCEN_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ATMEL_PIO_OPD_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ATMEL_PIO_SCHMITT_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ATMEL_PIO_DRVSTR_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ATMEL_PIO_PDSR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ATMEL_PIO_LOCKSR 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ATMEL_PIO_SODR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ATMEL_PIO_CODR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ATMEL_PIO_ODSR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ATMEL_PIO_IER 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ATMEL_PIO_IDR 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATMEL_PIO_IMR 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATMEL_PIO_ISR 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATMEL_PIO_IOFR 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATMEL_PIO_NPINS_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ATMEL_PIO_BANK_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Custom pinconf parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct atmel_pioctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct atmel_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct atmel_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned ioset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @reg_base: base address of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @clk: clock of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @nbanks: number of PIO groups, it can vary depending on the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @pinctrl_dev: pinctrl device registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @groups: groups table to provide group name and pin in the group to pinctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @group_names: group names table to provide all the group/pin names to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * pinctrl or gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * fields are set at probe time. Other ones are set when parsing dt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * pinctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @npins: number of pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @gpio_chip: gpio chip registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @irq_domain: irq domain for the gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @irqs: table containing the hw irq number of the bank. The index of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * table is the bank id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @pm_wakeup_sources: bitmap of wakeup sources (lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @pm_suspend_backup: backup/restore register values on suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @dev: device entry for the Atmel PIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @node: node of the Atmel PIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct atmel_pioctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pinctrl_dev *pinctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct atmel_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const char * const *group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct atmel_pin **pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gpio_chip *gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned *pm_wakeup_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 odsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } *pm_suspend_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const char * const atmel_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "GPIO", "A", "B", "C", "D", "E", "F", "G"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct pinconf_generic_params atmel_custom_bindings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* --- GPIO --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int bank, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return readl_relaxed(atmel_pioctrl->reg_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) + ATMEL_PIO_BANK_OFFSET * bank + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int bank, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(val, atmel_pioctrl->reg_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) + ATMEL_PIO_BANK_OFFSET * bank + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void atmel_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Nothing to do, interrupt is cleared when reading the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void atmel_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void atmel_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int bank = ATMEL_PIO_BANK(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int line = ATMEL_PIO_LINE(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* The gpio controller has one interrupt line per bank. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define atmel_gpio_irq_set_wake NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct irq_chip atmel_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .irq_ack = atmel_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .irq_mask = atmel_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .irq_unmask = atmel_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .irq_set_type = atmel_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .irq_set_wake = atmel_gpio_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void atmel_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int n, bank = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Find from which bank is the irq received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (n = 0; n < atmel_pioctrl->nbanks; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (atmel_pioctrl->irqs[n] == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bank = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (bank < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(atmel_pioctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "no bank associated to irq %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ATMEL_PIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ATMEL_PIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for_each_set_bit(n, &isr, BITS_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) generic_handle_irq(atmel_gpio_to_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) atmel_pioctrl->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bank * ATMEL_PIO_NPINS_PER_BANK + n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct atmel_pin *pin = atmel_pioctrl->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg &= ~ATMEL_PIO_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct atmel_pin *pin = atmel_pioctrl->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return !!(reg & BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bitmap_zero(bits, atmel_pioctrl->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int word = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!mask[word])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bits[word] |= mask[word] & (reg << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct atmel_pin *pin = atmel_pioctrl->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) atmel_gpio_write(atmel_pioctrl, pin->bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reg |= ATMEL_PIO_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct atmel_pin *pin = atmel_pioctrl->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) atmel_gpio_write(atmel_pioctrl, pin->bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BIT(pin->line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int word = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * two 32bit words to handle the whole bitmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!mask[word])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bitmask = mask[word] & bits[word];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bitmask = mask[word] & ~bits[word];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct gpio_chip atmel_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .direction_input = atmel_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .get = atmel_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .get_multiple = atmel_gpio_get_multiple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .direction_output = atmel_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .set = atmel_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .set_multiple = atmel_gpio_set_multiple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .to_irq = atmel_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* --- PINCTRL --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned line = atmel_pioctrl->pins[pin_id]->line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void __iomem *addr = atmel_pioctrl->reg_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) + bank * ATMEL_PIO_BANK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Have to set MSKR first, to access the right pin CFGR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return readl_relaxed(addr + ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned pin_id, u32 conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned line = atmel_pioctrl->pins[pin_id]->line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void __iomem *addr = atmel_pioctrl->reg_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) + bank * ATMEL_PIO_BANK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Have to set MSKR first, to access the right pin CFGR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return atmel_pioctrl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return atmel_pioctrl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned selector, const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct atmel_group *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (i = 0; i < atmel_pioctrl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct atmel_group *grp = atmel_pioctrl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (grp->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 pinfunc, const char **grp_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) const char **func_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned pin_id, func_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct atmel_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pin_id = ATMEL_GET_PIN_NO(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) func_id = ATMEL_GET_PIN_FUNC(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (func_id >= ARRAY_SIZE(atmel_functions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *func_name = atmel_functions[func_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *grp_name = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) atmel_pioctrl->pins[pin_id]->mux = func_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Want the device name not the group one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (np->parent == atmel_pioctrl->node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) atmel_pioctrl->pins[pin_id]->device = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) atmel_pioctrl->pins[pin_id]->device = np->parent->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned num_pins, num_configs, reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct property *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 pinfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pins = of_find_property(np, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(pctldev->dev, "%pOF: could not parse node property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) num_pins = pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!num_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Reserve maps, at least there is a mux map and an optional conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * map for each pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) reserve = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) reserve *= num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) const char *group, *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) group, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (num_configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) reserved_maps, num_maps, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) configs, num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * If all the pins of a device have the same configuration (or no one),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * it is useless to add a subnode, so directly parse node referenced by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * phandle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_err(pctldev->dev, "can't create maps for node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) np_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct pinctrl_ops atmel_pctlops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .get_groups_count = atmel_pctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .get_group_name = atmel_pctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .get_group_pins = atmel_pctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .dt_node_to_map = atmel_pctl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ARRAY_SIZE(atmel_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return atmel_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *groups = atmel_pioctrl->group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *num_groups = atmel_pioctrl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_dbg(pctldev->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) atmel_functions[function], atmel_pioctrl->groups[group].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pin = atmel_pioctrl->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) conf = atmel_pin_config_read(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) atmel_pin_config_write(pctldev, pin, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct pinmux_ops atmel_pmxops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .get_functions_count = atmel_pmx_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .get_function_name = atmel_pmx_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .get_function_groups = atmel_pmx_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .set_mux = atmel_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned param = pinconf_to_config_param(*config), arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct atmel_group *grp = atmel_pioctrl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned pin_id = grp->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) res = atmel_pin_config_read(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!(res & ATMEL_PIO_PUEN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if ((res & ATMEL_PIO_PUEN_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (!(res & ATMEL_PIO_PDEN_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if ((res & ATMEL_PIO_PUEN_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ((res & ATMEL_PIO_PDEN_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!(res & ATMEL_PIO_OPD_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!(res & ATMEL_PIO_SCHMITT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!(res & ATMEL_PIO_DRVSTR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct atmel_group *grp = atmel_pioctrl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned bank, pin, pin_id = grp->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 mask, conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) conf = atmel_pin_config_read(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __func__, pin_id, configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) conf &= (~ATMEL_PIO_PUEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) conf &= (~ATMEL_PIO_PDEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) conf |= ATMEL_PIO_PUEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) conf &= (~ATMEL_PIO_PDEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) conf |= ATMEL_PIO_PDEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) conf &= (~ATMEL_PIO_PUEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (arg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) conf &= (~ATMEL_PIO_OPD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) conf |= ATMEL_PIO_OPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (arg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) conf |= ATMEL_PIO_SCHMITT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) conf &= (~ATMEL_PIO_SCHMITT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (arg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) conf &= (~ATMEL_PIO_IFEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) conf &= (~ATMEL_PIO_IFSCEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * We don't care about the debounce value for several reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * - can't have different debounce periods inside a same group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * - the register to configure this period is a secure register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * The debouncing filter can filter a pulse with a duration of less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * than 1/2 slow clock period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) conf |= ATMEL_PIO_IFEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) conf |= ATMEL_PIO_IFSCEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) conf |= ATMEL_PIO_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) bank = ATMEL_PIO_BANK(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) pin = ATMEL_PIO_LINE(pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mask = 1 << pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (arg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) writel_relaxed(mask, atmel_pioctrl->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) bank * ATMEL_PIO_BANK_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ATMEL_PIO_CODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writel_relaxed(mask, atmel_pioctrl->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) bank * ATMEL_PIO_BANK_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ATMEL_PIO_SODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case ATMEL_PIO_DRVSTR_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case ATMEL_PIO_DRVSTR_ME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case ATMEL_PIO_DRVSTR_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) conf &= (~ATMEL_PIO_DRVSTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_warn(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "unsupported configuration parameter: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) atmel_pin_config_write(pctldev, pin_id, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct seq_file *s, unsigned pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!atmel_pioctrl->pins[pin_id]->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (atmel_pioctrl->pins[pin_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) seq_printf(s, " (%s, ioset %u) ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) atmel_pioctrl->pins[pin_id]->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) atmel_pioctrl->pins[pin_id]->ioset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) conf = atmel_pin_config_read(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (conf & ATMEL_PIO_PUEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) seq_printf(s, "%s ", "pull-up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (conf & ATMEL_PIO_PDEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) seq_printf(s, "%s ", "pull-down");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (conf & ATMEL_PIO_IFEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) seq_printf(s, "%s ", "debounce");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (conf & ATMEL_PIO_OPD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) seq_printf(s, "%s ", "open-drain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (conf & ATMEL_PIO_SCHMITT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) seq_printf(s, "%s ", "schmitt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (conf & ATMEL_PIO_DRVSTR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case ATMEL_PIO_DRVSTR_ME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) seq_printf(s, "%s ", "medium-drive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case ATMEL_PIO_DRVSTR_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) seq_printf(s, "%s ", "high-drive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) seq_printf(s, "%s ", "low-drive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct pinconf_ops atmel_confops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .pin_config_group_get = atmel_conf_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .pin_config_group_set = atmel_conf_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static struct pinctrl_desc atmel_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .name = "atmel_pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .confops = &atmel_confops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .pctlops = &atmel_pctlops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .pmxops = &atmel_pmxops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * For each bank, save IMR to restore it later and disable all GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * interrupts excepting the ones marked as wakeup sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for (i = 0; i < atmel_pioctrl->nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) atmel_pioctrl->pm_suspend_backup[i].imr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ~atmel_pioctrl->pm_wakeup_sources[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) atmel_pioctrl->pm_suspend_backup[i].odsr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) atmel_gpio_write(atmel_pioctrl, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ATMEL_PIO_MSKR, BIT(j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) atmel_gpio_read(atmel_pioctrl, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ATMEL_PIO_CFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int __maybe_unused atmel_pctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) for (i = 0; i < atmel_pioctrl->nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) atmel_pioctrl->pm_suspend_backup[i].imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) atmel_pioctrl->pm_suspend_backup[i].odsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) atmel_gpio_write(atmel_pioctrl, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ATMEL_PIO_MSKR, BIT(j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const struct dev_pm_ops atmel_pctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * The number of banks can be different from a SoC to another one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * We can have up to 16 banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .nbanks = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .nbanks = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct of_device_id atmel_pctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .compatible = "atmel,sama5d2-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .data = &atmel_sama5d2_pioctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .compatible = "microchip,sama7g5-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .data = µchip_sama7g5_pioctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int atmel_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct pinctrl_pin_desc *pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) const char **group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct atmel_pioctrl *atmel_pioctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) const struct atmel_pioctrl_data *atmel_pioctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!atmel_pioctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) atmel_pioctrl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) atmel_pioctrl->node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) platform_set_drvdata(pdev, atmel_pioctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) match = of_match_node(atmel_pctrl_of_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dev_err(dev, "unknown compatible string\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) atmel_pioctrl_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (IS_ERR(atmel_pioctrl->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return PTR_ERR(atmel_pioctrl->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) atmel_pioctrl->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (IS_ERR(atmel_pioctrl->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return PTR_ERR(atmel_pioctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) atmel_pioctrl->pins = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) atmel_pioctrl->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) sizeof(*atmel_pioctrl->pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!atmel_pioctrl->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (!pin_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) atmel_pinctrl_desc.pins = pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* One pin is one group since a pin can achieve all functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) group_names = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) atmel_pioctrl->npins, sizeof(*group_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!group_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) atmel_pioctrl->group_names = group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (!atmel_pioctrl->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) for (i = 0 ; i < atmel_pioctrl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct atmel_group *group = atmel_pioctrl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) unsigned bank = ATMEL_PIO_BANK(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned line = ATMEL_PIO_LINE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) atmel_pioctrl->pins[i] = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!atmel_pioctrl->pins[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) atmel_pioctrl->pins[i]->pin_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) atmel_pioctrl->pins[i]->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) atmel_pioctrl->pins[i]->line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pin_desc[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Pin naming convention: P(bank_name)(bank_pin_number). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bank + 'A', line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) group->name = group_names[i] = pin_desc[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) group->pin = pin_desc[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) atmel_pioctrl->gpio_chip->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) atmel_pioctrl->gpio_chip->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) atmel_pioctrl->gpio_chip->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) atmel_pioctrl->nbanks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) sizeof(*atmel_pioctrl->pm_wakeup_sources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!atmel_pioctrl->pm_wakeup_sources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) atmel_pioctrl->nbanks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sizeof(*atmel_pioctrl->pm_suspend_backup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (!atmel_pioctrl->pm_suspend_backup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) atmel_pioctrl->irqs = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) atmel_pioctrl->nbanks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sizeof(*atmel_pioctrl->irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (!atmel_pioctrl->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* There is one controller but each bank has its own irq line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) for (i = 0; i < atmel_pioctrl->nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(dev, "missing irq resource for group %c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) 'A' + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) atmel_pioctrl->irqs[i] = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) irq_set_handler_data(res->start, atmel_pioctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) atmel_pioctrl->gpio_chip->ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!atmel_pioctrl->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_err(dev, "can't add the irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) atmel_pioctrl->irq_domain->name = "atmel gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i = 0; i < atmel_pioctrl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) irq_set_chip_data(irq, atmel_pioctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) i, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = clk_prepare_enable(atmel_pioctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_err(dev, "failed to prepare and enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) goto clk_prepare_enable_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) &atmel_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) atmel_pioctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_err(dev, "pinctrl registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto clk_unprep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_err(dev, "failed to add gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) goto clk_unprep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) 0, 0, atmel_pioctrl->gpio_chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dev_err(dev, "failed to add gpio pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) goto gpiochip_add_pin_range_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dev_info(&pdev->dev, "atmel pinctrl initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) gpiochip_add_pin_range_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) gpiochip_remove(atmel_pioctrl->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) clk_unprep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) clk_disable_unprepare(atmel_pioctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) clk_prepare_enable_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) irq_domain_remove(atmel_pioctrl->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static struct platform_driver atmel_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .name = "pinctrl-at91-pio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .of_match_table = atmel_pctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .pm = &atmel_pctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .probe = atmel_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) builtin_platform_driver(atmel_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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