^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ams AS3722 pin control and GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/as3722.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AS3722_PIN_GPIO0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AS3722_PIN_GPIO1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AS3722_PIN_GPIO2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AS3722_PIN_GPIO3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AS3722_PIN_GPIO4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AS3722_PIN_GPIO5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AS3722_PIN_GPIO6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AS3722_PIN_GPIO7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct as3722_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int mux_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct as3722_gpio_pin_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned mode_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int io_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct as3722_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const unsigned pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct as3722_pctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct as3722 *as3722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int pins_current_opt[AS3722_PIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct as3722_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct as3722_pingroup *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct pinctrl_pin_desc as3722_pins_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum as3722_pinmux_option {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) AS3722_PINMUX_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AS3722_PINMUX_INTERRUPT_OUT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AS3722_PINMUX_GPIO_INTERRUPT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AS3722_PINMUX_PWM_INPUT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AS3722_PINMUX_OC_PG_SD0 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AS3722_PINMUX_PG_OUT = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AS3722_PINMUX_CLK32K_OUT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AS3722_PINMUX_WATCHDOG_INPUT = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AS3722_PINMUX_SOFT_RESET_IN = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AS3722_PINMUX_PWM_OUTPUT = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AS3722_PINMUX_OC_PG_SD6 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FUNCTION_GROUP(fname, mux) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .groups = gpio_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .ngroups = ARRAY_SIZE(gpio_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mux_option = AS3722_PINMUX_##mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct as3722_pin_function as3722_pin_function[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FUNCTION_GROUP(gpio, GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FUNCTION_GROUP(powergood-out, PG_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FUNCTION_GROUP(pwm-in, PWM_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AS3722_PINGROUP(pg_name, pin_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .pins = {AS3722_PIN_##pin_id}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .npins = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct as3722_pingroup as3722_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) AS3722_PINGROUP(gpio0, GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) AS3722_PINGROUP(gpio1, GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) AS3722_PINGROUP(gpio2, GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AS3722_PINGROUP(gpio3, GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) AS3722_PINGROUP(gpio4, GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) AS3722_PINGROUP(gpio5, GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) AS3722_PINGROUP(gpio6, GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) AS3722_PINGROUP(gpio7, GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return as_pci->num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return as_pci->pin_groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned group, const unsigned **pins, unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *pins = as_pci->pin_groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *num_pins = as_pci->pin_groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct pinctrl_ops as3722_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .get_groups_count = as3722_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .get_group_name = as3722_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .get_group_pins = as3722_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return as_pci->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return as_pci->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned function, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *groups = as_pci->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *num_groups = as_pci->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __func__, group, function, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AS3722_GPIO_IOSF_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) group, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) as_pci->gpio_control[group].io_function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case AS3722_GPIO_IOSF_SD0_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case AS3722_GPIO_IOSF_Q32K_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case AS3722_GPIO_IOSF_PWM_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) group, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) as_pci->gpio_control[group].mode_prop =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AS3722_GPIO_MODE_OUTPUT_VDDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return AS3722_GPIO_MODE_INPUT_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return AS3722_GPIO_MODE_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return AS3722_GPIO_MODE_OUTPUT_VDDL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return AS3722_GPIO_MODE_OUTPUT_VDDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct pinctrl_gpio_range *range, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (as_pci->gpio_control[offset].io_function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct pinctrl_gpio_range *range, unsigned offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct as3722 *as3722 = as_pci->as3722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mode = as3722_pinctrl_gpio_get_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) as_pci->gpio_control[offset].mode_prop, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (mode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (input) ? "Input" : "Output", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) AS3722_GPIO_MODE_MASK, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct pinmux_ops as3722_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .get_functions_count = as3722_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .get_function_name = as3722_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .get_function_groups = as3722_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .set_mux = as3722_pinctrl_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u16 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) prop = AS3722_GPIO_MODE_PULL_UP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) AS3722_GPIO_MODE_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!(as_pci->gpio_control[pin].mode_prop & prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) prop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) prop = AS3722_GPIO_MODE_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) prop = AS3722_GPIO_MODE_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) prop = AS3722_GPIO_MODE_OPEN_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) prop = AS3722_GPIO_MODE_HIGH_IMPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(as_pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (as_pci->gpio_control[pin].mode_prop & prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *config = pinconf_to_config_packed(param, (u16)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int mode_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mode_prop = as_pci->gpio_control[pin].mode_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) AS3722_GPIO_MODE_PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mode_prop |= AS3722_GPIO_MODE_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(as_pci->dev, "Properties not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) as_pci->gpio_control[pin].mode_prop = mode_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct pinconf_ops as3722_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .pin_config_get = as3722_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pin_config_set = as3722_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct pinctrl_desc as3722_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .pctlops = &as3722_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .pmxops = &as3722_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .confops = &as3722_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct as3722 *as3722 = as_pci->as3722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int invert_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(as_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) invert_enable = !!(control & AS3722_GPIO_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mode = control & AS3722_GPIO_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case AS3722_GPIO_MODE_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case AS3722_GPIO_MODE_INPUT_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) reg = AS3722_GPIO_SIGNAL_IN_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case AS3722_GPIO_MODE_OUTPUT_VDDH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case AS3722_GPIO_MODE_OUTPUT_VDDL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reg = AS3722_GPIO_SIGNAL_OUT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = as3722_read(as3722, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(as_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val = !!(val & AS3722_GPIOn_SIGNAL(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return (invert_enable) ? !val : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct as3722 *as3722 = as_pci->as3722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int en_invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(as_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) en_invert = !!(val & AS3722_GPIO_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) AS3722_GPIOn_SIGNAL(offset), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(as_pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int as3722_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) as3722_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return as3722_irq_get_virq(as_pci->as3722, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct gpio_chip as3722_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .label = "as3722-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .get = as3722_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .set = as3722_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .direction_input = as3722_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .direction_output = as3722_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .to_irq = as3722_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ngpio = AS3722_PIN_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int as3722_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct as3722_pctrl_info *as_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!as_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) as_pci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) as_pci->dev->of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) platform_set_drvdata(pdev, as_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) as_pci->pins = as3722_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) as_pci->functions = as3722_pin_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) as_pci->pin_groups = as3722_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) as3722_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) as3722_pinctrl_desc.pins = as3722_pins_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) as_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(as_pci->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR(as_pci->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) as_pci->gpio_chip = as3722_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) as_pci->gpio_chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0, 0, AS3722_PIN_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) goto fail_range_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) fail_range_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gpiochip_remove(&as_pci->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int as3722_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) gpiochip_remove(&as_pci->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct of_device_id as3722_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { .compatible = "ams,as3722-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct platform_driver as3722_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "as3722-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .of_match_table = as3722_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .probe = as3722_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .remove = as3722_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) module_platform_driver(as3722_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_ALIAS("platform:as3722-pinctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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