^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the Axis ARTPEC-6 pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chris Paterson <chris.paterson@linux.pieboy.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Pinmux control register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARTPEC6_PINMUX_UDC0_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ARTPEC6_PINMUX_UDC0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARTPEC6_PINMUX_UDC1_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARTPEC6_PINMUX_UDC1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARTPEC6_PINMUX_DRV_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARTPEC6_PINMUX_DRV_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARTPEC6_PINMUX_SEL_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARTPEC6_PINMUX_SEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Pinmux configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ARTPEC6_CONFIG_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ARTPEC6_CONFIG_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ARTPEC6_CONFIG_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ARTPEC6_CONFIG_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Pin drive strength options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ARTPEC6_DRIVE_4mA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ARTPEC6_DRIVE_4mA_SET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARTPEC6_DRIVE_6mA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ARTPEC6_DRIVE_6mA_SET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ARTPEC6_DRIVE_8mA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ARTPEC6_DRIVE_8mA_SET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARTPEC6_DRIVE_9mA 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARTPEC6_DRIVE_9mA_SET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct artpec6_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct artpec6_pin_group *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int num_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const struct artpec6_pmx_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct artpec6_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned char config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct artpec6_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct pinctrl_pin_desc artpec6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(0, "GPIO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(1, "GPIO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(2, "GPIO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(3, "GPIO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(4, "GPIO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(5, "GPIO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(6, "GPIO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(7, "GPIO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(8, "GPIO8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(9, "GPIO9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(10, "GPIO10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(11, "GPIO11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(12, "GPIO12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(13, "GPIO13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(14, "GPIO14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(15, "GPIO15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(16, "GPIO16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(17, "GPIO17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(18, "GPIO18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(19, "GPIO19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(20, "GPIO20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(21, "GPIO21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(22, "GPIO22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(23, "GPIO23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(24, "GPIO24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(25, "GPIO25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(26, "GPIO26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(27, "GPIO27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(28, "GPIO28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(29, "GPIO29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(30, "GPIO30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(31, "GPIO31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(32, "UART3_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(33, "UART3_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(34, "UART3_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(35, "UART3_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(36, "NF_ALE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(37, "NF_CE0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(38, "NF_CE1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(39, "NF_CLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(40, "NF_RE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(41, "NF_WE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(42, "NF_WP0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(43, "NF_WP1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(44, "NF_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(45, "NF_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(46, "NF_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(47, "NF_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(48, "NF_IO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(49, "NF_IO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(50, "NF_IO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(51, "NF_IO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(52, "NF_RB0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(53, "SDIO0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(54, "SDIO0_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(55, "SDIO0_DAT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(56, "SDIO0_DAT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(57, "SDIO0_DAT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(58, "SDIO0_DAT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(59, "SDI0_CD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(60, "SDI0_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(61, "SDIO1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(62, "SDIO1_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(63, "SDIO1_DAT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(64, "SDIO1_DAT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(65, "SDIO1_DAT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(66, "SDIO1_DAT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(67, "SDIO1_CD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(68, "SDIO1_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(69, "GBE_REFCLk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(70, "GBE_GTX_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(71, "GBE_TX_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(72, "GBE_TX_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(73, "GBE_TX_ER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(74, "GBE_TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(75, "GBE_TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(76, "GBE_TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(77, "GBE_TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(78, "GBE_TXD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(79, "GBE_TXD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(80, "GBE_TXD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(81, "GBE_TXD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(82, "GBE_RX_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(83, "GBE_RX_DV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(84, "GBE_RX_ER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(85, "GBE_RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(86, "GBE_RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(87, "GBE_RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(88, "GBE_RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(89, "GBE_RXD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(90, "GBE_RXD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(91, "GBE_RXD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(92, "GBE_RXD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(93, "GBE_CRS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(94, "GBE_COL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(95, "GBE_MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(96, "GBE_MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const unsigned int cpuclkout_pins0[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned int udlclkout_pins0[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int i2c1_pins0[] = { 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned int i2c2_pins0[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned int i2c3_pins0[] = { 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int i2s1_pins0[] = { 12, 13, 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned int i2srefclk_pins0[] = { 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const unsigned int spi0_pins0[] = { 12, 13, 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned int spi1_pins0[] = { 16, 17, 18, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int pciedebug_pins0[] = { 12, 13, 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned int uart0_pins0[] = { 16, 17, 18, 19, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 21, 22, 23, 24, 25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const unsigned int uart0_pins1[] = { 20, 21, 22, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned int uart1_pins0[] = { 24, 25, 26, 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const unsigned int uart2_pins0[] = { 26, 27, 28, 29, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 31, 32, 33, 34, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const unsigned int uart2_pins1[] = { 28, 29, 30, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned int uart3_pins0[] = { 32, 33, 34, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const unsigned int uart4_pins0[] = { 20, 21, 22, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned int uart5_pins0[] = { 28, 29, 30, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const unsigned int nand_pins0[] = { 36, 37, 38, 39, 40, 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 42, 43, 44, 45, 46, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 48, 49, 50, 51, 52 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const unsigned int sdio0_pins0[] = { 53, 54, 55, 56, 57, 58, 59, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int sdio1_pins0[] = { 61, 62, 63, 64, 65, 66, 67, 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned int ethernet_pins0[] = { 69, 70, 71, 72, 73, 74, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 76, 77, 78, 79, 80, 81, 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 83, 84, 85, 86, 87, 88, 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 90, 91, 92, 93, 94, 95, 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct artpec6_pin_group artpec6_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "cpuclkoutgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pins = cpuclkout_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .num_pins = ARRAY_SIZE(cpuclkout_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "udlclkoutgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .pins = udlclkout_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .num_pins = ARRAY_SIZE(udlclkout_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "i2c1grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .pins = i2c1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_pins = ARRAY_SIZE(i2c1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "i2c2grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pins = i2c2_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_pins = ARRAY_SIZE(i2c2_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "i2c3grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .pins = i2c3_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .num_pins = ARRAY_SIZE(i2c3_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "i2s0grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .pins = i2s0_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .num_pins = ARRAY_SIZE(i2s0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "i2s1grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .pins = i2s1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .num_pins = ARRAY_SIZE(i2s1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "i2srefclkgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .pins = i2srefclk_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .num_pins = ARRAY_SIZE(i2srefclk_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .config = ARTPEC6_CONFIG_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "spi0grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .pins = spi0_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .num_pins = ARRAY_SIZE(spi0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "spi1grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .pins = spi1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_pins = ARRAY_SIZE(spi1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "pciedebuggrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .pins = pciedebug_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .num_pins = ARRAY_SIZE(pciedebug_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .config = ARTPEC6_CONFIG_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .name = "uart0grp0", /* All pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pins = uart0_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_pins = ARRAY_SIZE(uart0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "uart0grp1", /* RX/TX and RTS/CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .pins = uart0_pins1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_pins = ARRAY_SIZE(uart0_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "uart0grp2", /* Only RX/TX pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .pins = uart0_pins1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "uart1grp0", /* RX/TX and RTS/CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pins = uart1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .num_pins = ARRAY_SIZE(uart1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "uart1grp1", /* Only RX/TX pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .pins = uart1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .num_pins = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "uart2grp0", /* Full pinout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .pins = uart2_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_pins = ARRAY_SIZE(uart2_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "uart2grp1", /* RX/TX and RTS/CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pins = uart2_pins1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .num_pins = ARRAY_SIZE(uart2_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "uart2grp2", /* Only RX/TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .pins = uart2_pins1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_pins = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .config = ARTPEC6_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "uart3grp0", /* RX/TX and CTS/RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .pins = uart3_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_pins = ARRAY_SIZE(uart3_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "uart3grp1", /* Only RX/TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .pins = uart3_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_pins = ARRAY_SIZE(uart3_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "uart4grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .pins = uart4_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_pins = ARRAY_SIZE(uart4_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "uart5grp0", /* TX/RX and RTS/CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .pins = uart5_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .num_pins = ARRAY_SIZE(uart5_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "uart5grp1", /* Only TX/RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pins = uart5_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .num_pins = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "uart5nocts", /* TX/RX/RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .pins = uart5_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .config = ARTPEC6_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "nandgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .pins = nand_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_pins = ARRAY_SIZE(nand_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "sdio0grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .pins = sdio0_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .num_pins = ARRAY_SIZE(sdio0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "sdio1grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .pins = sdio1_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .num_pins = ARRAY_SIZE(sdio1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "ethernetgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .pins = ethernet_pins0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_pins = ARRAY_SIZE(ethernet_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .config = ARTPEC6_CONFIG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct pin_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * The register map has two holes where the pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * no longer fits directly with the register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * This table allows us to map this easily.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct pin_register pin_register[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0, 35, 0x0 }, /* 0x0 - 0x8c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 36, 52, 0x100 }, /* 0x100 - 0x140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 53, 96, 0x180 }, /* 0x180 - 0x22c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static unsigned int artpec6_pmx_reg_offset(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < ARRAY_SIZE(pin_register); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (pin <= pin_register[i].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return (pin - pin_register[i].start) * 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pin_register[i].reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Anything we return here is wrong, but we can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * get here if pin is outside registered range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pr_err("%s: Impossible pin %d\n", __func__, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int artpec6_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ARRAY_SIZE(artpec6_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const char *artpec6_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return artpec6_pin_groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int artpec6_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *pins = (unsigned int *)artpec6_pin_groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *num_pins = artpec6_pin_groups[group].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int artpec6_pconf_drive_mA_to_field(unsigned int mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (mA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case ARTPEC6_DRIVE_4mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ARTPEC6_DRIVE_4mA_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case ARTPEC6_DRIVE_6mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ARTPEC6_DRIVE_6mA_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case ARTPEC6_DRIVE_8mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ARTPEC6_DRIVE_8mA_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case ARTPEC6_DRIVE_9mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ARTPEC6_DRIVE_9mA_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static unsigned int artpec6_pconf_drive_field_to_mA(int field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case ARTPEC6_DRIVE_4mA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ARTPEC6_DRIVE_4mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case ARTPEC6_DRIVE_6mA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ARTPEC6_DRIVE_6mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case ARTPEC6_DRIVE_8mA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ARTPEC6_DRIVE_8mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case ARTPEC6_DRIVE_9mA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ARTPEC6_DRIVE_9mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct pinctrl_ops artpec6_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .get_group_pins = artpec6_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .get_groups_count = artpec6_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .get_group_name = artpec6_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const char * const gpiogrps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "uart5grp1", "uart5nocts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const char * const i2c1grps[] = { "i2c1grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const char * const i2c2grps[] = { "i2c2grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const char * const i2c3grps[] = { "i2c3grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const char * const i2s0grps[] = { "i2s0grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const char * const i2s1grps[] = { "i2s1grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const char * const spi0grps[] = { "spi0grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const char * const spi1grps[] = { "spi1grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const char * const uart0grps[] = { "uart0grp0", "uart0grp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "uart0grp2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const char * const uart2grps[] = { "uart2grp0", "uart2grp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "uart2grp2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const char * const uart3grps[] = { "uart3grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const char * const uart5grps[] = { "uart5grp0", "uart5grp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "uart5nocts" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const char * const nandgrps[] = { "nandgrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const char * const sdio0grps[] = { "sdio0grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const char * const sdio1grps[] = { "sdio1grp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const char * const ethernetgrps[] = { "ethernetgrp0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct artpec6_pmx_func artpec6_pmx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .groups = gpiogrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .num_groups = ARRAY_SIZE(gpiogrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "cpuclkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .groups = cpuclkoutgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .num_groups = ARRAY_SIZE(cpuclkoutgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "udlclkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .groups = udlclkoutgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_groups = ARRAY_SIZE(udlclkoutgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .groups = i2c1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_groups = ARRAY_SIZE(i2c1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .groups = i2c2grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .num_groups = ARRAY_SIZE(i2c2grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .groups = i2c3grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .num_groups = ARRAY_SIZE(i2c3grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .name = "i2s0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .groups = i2s0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .num_groups = ARRAY_SIZE(i2s0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .groups = i2s1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .num_groups = ARRAY_SIZE(i2s1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "i2srefclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .groups = i2srefclkgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .num_groups = ARRAY_SIZE(i2srefclkgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .groups = spi0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .num_groups = ARRAY_SIZE(spi0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = "spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .groups = spi1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .num_groups = ARRAY_SIZE(spi1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "pciedebug",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .groups = pciedebuggrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .num_groups = ARRAY_SIZE(pciedebuggrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .groups = uart0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .num_groups = ARRAY_SIZE(uart0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .groups = uart1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_groups = ARRAY_SIZE(uart1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .groups = uart2grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .num_groups = ARRAY_SIZE(uart2grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = "uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .groups = uart3grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .num_groups = ARRAY_SIZE(uart3grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .groups = uart4grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_groups = ARRAY_SIZE(uart4grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .groups = uart5grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .num_groups = ARRAY_SIZE(uart5grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .groups = nandgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .num_groups = ARRAY_SIZE(nandgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .name = "sdio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .groups = sdio0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .num_groups = ARRAY_SIZE(sdio0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "sdio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .groups = sdio1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_groups = ARRAY_SIZE(sdio1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .groups = ethernetgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_groups = ARRAY_SIZE(ethernetgrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ARRAY_SIZE(artpec6_pmx_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return artpec6_pmx_functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int artpec6_pmx_get_fgroups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *groups = artpec6_pmx_functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *num_groups = artpec6_pmx_functions[function].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned int function, unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int regval, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) for (i = 0; i < artpec6_pin_groups[group].num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Registers for pins above a ARTPEC6_MAX_MUXABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * do not have a SEL field and are always selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!strcmp(artpec6_pmx_get_fname(pctldev, function), "gpio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* GPIO is always config 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val = artpec6_pin_groups[group].config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) << ARTPEC6_PINMUX_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val = ARTPEC6_CONFIG_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) << ARTPEC6_PINMUX_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) regval = readl(pmx->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regval &= ~ARTPEC6_PINMUX_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) writel(regval, pmx->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_dbg(pmx->dev, "enabling %s function for pin group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) artpec6_pmx_get_fname(pctldev, function),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) artpec6_get_group_name(pctldev, group));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) artpec6_pmx_select_func(pctldev, function, group, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int reg = artpec6_pmx_reg_offset(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (pin >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val = readl_relaxed(pmx->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) val &= ~ARTPEC6_PINMUX_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writel_relaxed(val, pmx->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const struct pinmux_ops artpec6_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .get_functions_count = artpec6_pmx_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .get_function_name = artpec6_pmx_get_fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .get_function_groups = artpec6_pmx_get_fgroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .set_mux = artpec6_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .gpio_request_enable = artpec6_pmx_request_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int artpec6_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Check for valid pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (pin >= pmx->num_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pmx->pins[pin].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_dbg(pmx->dev, "getting configuration for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pmx->pins[pin].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Read pin register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* If valid, get configuration for parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (regval & ARTPEC6_PINMUX_UDC1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) regval = regval & ARTPEC6_PINMUX_UDC0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) (param == PIN_CONFIG_BIAS_PULL_DOWN && regval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) regval = (regval & ARTPEC6_PINMUX_DRV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) >> ARTPEC6_PINMUX_DRV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) regval = artpec6_pconf_drive_field_to_mA(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) *config = pinconf_to_config_packed(param, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Valid combinations of param and arg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * param arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * PIN_CONFIG_BIAS_DISABLE: x (disable bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * PIN_CONFIG_BIAS_PULL_UP: 1 (pull up bias + enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * PIN_CONFIG_DRIVE_STRENGTH: x (4mA, 6mA, 8mA, 9mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * All other args are invalid. All other params are not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Check for valid pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (pin >= pmx->num_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pmx->pins[pin].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(pmx->dev, "setting configuration for pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pmx->pins[pin].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) reg = pmx->base + artpec6_pmx_reg_offset(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* For each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) regval = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) writel(regval, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (arg != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __func__, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) regval = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(regval, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (arg != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __func__, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) regval = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) writel(regval, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) drive = artpec6_pconf_drive_mA_to_field(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (drive < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) __func__, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) regval = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) regval &= ~ARTPEC6_PINMUX_DRV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) writel(regval, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_dbg(pmx->dev, "parameter not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int artpec6_pconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned int group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int num_pins, current_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_dbg(pctldev->dev, "setting group %s configuration\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) artpec6_get_group_name(pctldev, group));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) num_pins = artpec6_pin_groups[group].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for (current_pin = 0; current_pin < num_pins; current_pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = artpec6_pconf_set(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) artpec6_pin_groups[group].pins[current_pin],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const struct pinconf_ops artpec6_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .pin_config_get = artpec6_pconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .pin_config_set = artpec6_pconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .pin_config_group_set = artpec6_pconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static struct pinctrl_desc artpec6_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .name = "artpec6-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .pins = artpec6_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .npins = ARRAY_SIZE(artpec6_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .pctlops = &artpec6_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .pmxops = &artpec6_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .confops = &artpec6_pconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* The reset values say 4mA, but we want 8mA as default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void artpec6_pmx_reset(struct artpec6_pmx *pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) void __iomem *base = pmx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = 0; i < ARTPEC6_LAST_PIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) val = readl_relaxed(base + artpec6_pmx_reg_offset(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) val &= ~ARTPEC6_PINMUX_DRV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int artpec6_pmx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct artpec6_pmx *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pmx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pmx->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (IS_ERR(pmx->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return PTR_ERR(pmx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) artpec6_pmx_reset(pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pmx->pins = artpec6_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pmx->num_pins = ARRAY_SIZE(artpec6_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pmx->functions = artpec6_pmx_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pmx->num_functions = ARRAY_SIZE(artpec6_pmx_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pmx->pin_groups = artpec6_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pmx->pctl = pinctrl_register(&artpec6_desc, &pdev->dev, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (IS_ERR(pmx->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(&pdev->dev, "could not register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return PTR_ERR(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) platform_set_drvdata(pdev, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int artpec6_pmx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) pinctrl_unregister(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const struct of_device_id artpec6_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) { .compatible = "axis,artpec6-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static struct platform_driver artpec6_pmx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .name = "artpec6-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .of_match_table = artpec6_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .probe = artpec6_pmx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .remove = artpec6_pmx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int __init artpec6_pmx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return platform_driver_register(&artpec6_pmx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) arch_initcall(artpec6_pmx_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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