^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014,2015 AMD Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Ken Xue <Ken.Xue@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Wu, Jeff <Jeff.Wu@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "pinctrl-amd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(pin_reg, gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pin_reg |= BIT(OUTPUT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pin_reg |= BIT(OUTPUT_VALUE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(pin_reg, gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return !!(pin_reg & BIT(PIN_STS_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pin_reg |= BIT(OUTPUT_VALUE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(pin_reg, gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pin_reg = readl(gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (debounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pin_reg &= ~DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Debounce Debounce Timer Max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TmrLarge TmrOutUnit Unit Debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0 0 61 usec (2 RtcClk) 976 usec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0 1 244 usec (8 RtcClk) 3.9 msec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1 0 15.6 msec (512 RtcClk) 250 msec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 1 1 62.5 msec (2048 RtcClk) 1 sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (debounce < 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pin_reg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else if (debounce < 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) time = debounce / 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pin_reg |= time & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } else if (debounce < 3900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) time = debounce / 244;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pin_reg |= time & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else if (debounce < 250000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) time = debounce / 15625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pin_reg |= time & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pin_reg |= BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else if (debounce < 1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) time = debounce / 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pin_reg |= time & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pin_reg |= BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pin_reg &= ~DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(pin_reg, gpio_dev->base + offset * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return amd_gpio_set_debounce(gc, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int bank, i, pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) char *level_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char *active_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) char *interrupt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) char *interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) char *wake_cntrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) char *wake_cntrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) char *wake_cntrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) char *pin_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) char *pull_up_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) char *pull_up_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) char *pull_down_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) char *output_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) char *output_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) seq_printf(s, "GPIO bank%d\t", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pin_num = AMD_GPIO_PINS_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) i = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pin_num = AMD_GPIO_PINS_BANK1 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) i = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pin_num = AMD_GPIO_PINS_BANK2 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) i = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pin_num = AMD_GPIO_PINS_BANK3 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Illegal bank number, ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for (; i < pin_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) seq_printf(s, "pin%d\t", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pin_reg = readl(gpio_dev->base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ACTIVE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) interrupt_enable = "interrupt is enabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (level == ACTIVE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) active_level = "Active high|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else if (level == ACTIVE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) active_level = "Active low|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) level == ACTIVE_LEVEL_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) active_level = "Active on both|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) active_level = "Unknown Active level|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (pin_reg & BIT(LEVEL_TRIG_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) level_trig = "Level trigger|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) level_trig = "Edge trigger|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) interrupt_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "interrupt is disabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) active_level = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) level_trig = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (pin_reg & BIT(INTERRUPT_MASK_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) interrupt_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "interrupt is unmasked|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) interrupt_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "interrupt is masked|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wake_cntrl0 = "enable wakeup in S0i3 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) wake_cntrl0 = "disable wakeup in S0i3 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wake_cntrl1 = "enable wakeup in S3 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) wake_cntrl1 = "disable wakeup in S3 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) wake_cntrl2 = "enable wakeup in S4/S5 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) wake_cntrl2 = "disable wakeup in S4/S5 state|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pull_up_enable = "pull-up is enabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (pin_reg & BIT(PULL_UP_SEL_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pull_up_sel = "8k pull-up|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pull_up_sel = "4k pull-up|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pull_up_enable = "pull-up is disabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pull_up_sel = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pull_down_enable = "pull-down is enabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pull_down_enable = "Pull-down is disabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pin_sts = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) output_enable = "output is enabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (pin_reg & BIT(OUTPUT_VALUE_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) output_value = "output is high|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) output_value = "output is low|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) output_enable = "output is disabled|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) output_value = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (pin_reg & BIT(PIN_STS_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pin_sts = "input is high|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pin_sts = "input is low|";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) seq_printf(s, "%s %s %s %s %s %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) " %s %s %s %s %s %s %s 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) level_trig, active_level, interrupt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) interrupt_mask, wake_cntrl0, wake_cntrl1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) wake_cntrl2, pin_sts, pull_up_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pull_up_enable, pull_down_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) output_value, output_enable, pin_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define amd_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void amd_gpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pin_reg |= BIT(INTERRUPT_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void amd_gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void amd_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void amd_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pin_reg |= BIT(INTERRUPT_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void amd_gpio_irq_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) reg |= EOI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 pin_reg, pin_reg_irq_en, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pin_reg &= ~BIT(LEVEL_TRIG_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pin_reg &= ~BIT(LEVEL_TRIG_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pin_reg &= ~BIT(LEVEL_TRIG_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * debounce registers of any GPIO will block wake/interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * generation for *all* GPIOs for a length of time that depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * INTERRUPT_ENABLE bit will read as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * We temporarily enable irq for the GPIO whose configuration is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * changing, and then wait for it to read back as 1 to know when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * debounce has settled and then disable the irq again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * We do this polling with the spinlock held to ensure other GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * access routines do not read an incorrect value for the irq enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * bit of other GPIOs. We keep the GPIO masked while polling to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * spurious irqs, and disable the irq again after polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mask = BIT(INTERRUPT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pin_reg_irq_en = pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pin_reg_irq_en |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void amd_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * based on HW design,there is no need to ack HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * before handle current irq. But this routine is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * necessary for handle_edge_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct irq_chip amd_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .name = "amd_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .irq_ack = amd_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .irq_enable = amd_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .irq_disable = amd_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .irq_mask = amd_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .irq_unmask = amd_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .irq_eoi = amd_gpio_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .irq_set_type = amd_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct amd_gpio *gpio_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct gpio_chip *gc = &gpio_dev->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int i, irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u64 status, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Read the wake status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) status <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Bit 0-45 contain the relevant status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) status &= (1ULL << 46) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) regs = gpio_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(status & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) status &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Each status bit covers four pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regval = readl(regs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!(regval & PIN_IRQ_PENDING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) !(regval & BIT(INTERRUPT_MASK_OFF)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) irq = irq_find_mapping(gc->irq.domain, irqnr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (irq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Clear interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * We must read the pin register again, in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * value was changed while executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * generic_handle_irq() above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * If we didn't find a mapping for the interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * disable it in order to avoid a system hang caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * by an interrupt storm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regval = readl(regs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) regval &= ~BIT(INTERRUPT_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_dbg(&gpio_dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "Disabling spurious GPIO IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) irqnr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) writel(regval, regs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Signal EOI to the GPIO unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) regval |= EOI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int amd_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return gpio_dev->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return gpio_dev->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int amd_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *pins = gpio_dev->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *num_pins = gpio_dev->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const struct pinctrl_ops amd_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .get_groups_count = amd_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .get_group_name = amd_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .get_group_pins = amd_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int amd_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pin_reg = readl(gpio_dev->base + pin*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) arg = pin_reg & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pin_reg = readl(gpio_dev->base + pin*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pin_reg &= ~DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pin_reg |= arg & DB_TMR_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pin_reg &= ~BIT(PULL_UP_SEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pin_reg &= ~(DRV_STRENGTH_SEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) << DRV_STRENGTH_SEL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) << DRV_STRENGTH_SEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(&gpio_dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "Invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel(pin_reg, gpio_dev->base + pin*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = amd_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (amd_pinconf_get(pctldev, pins[0], config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = amd_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct pinconf_ops amd_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .pin_config_get = amd_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .pin_config_set = amd_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .pin_config_group_get = amd_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .pin_config_group_set = amd_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 pin_reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) BIT(WAKE_CNTRL_OFF_S4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) for (i = 0; i < desc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int pin = desc->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pin_reg = readl(gpio_dev->base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pin_reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel(pin_reg, gpio_dev->base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Only restore the pin if it is actually in use by the kernel (or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * by userspace).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (pd->mux_owner || pd->gpio_owner ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) gpiochip_line_is_irq(&gpio_dev->gc, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int amd_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) for (i = 0; i < desc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int pin = desc->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!amd_gpio_should_save(gpio_dev, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int amd_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) for (i = 0; i < desc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int pin = desc->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!amd_gpio_should_save(gpio_dev, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const struct dev_pm_ops amd_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) amd_gpio_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static struct pinctrl_desc amd_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .pins = kerncz_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .npins = ARRAY_SIZE(kerncz_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .pctlops = &amd_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .confops = &amd_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int amd_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct amd_gpio *gpio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) gpio_dev = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) sizeof(struct amd_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!gpio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) raw_spin_lock_init(&gpio_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!gpio_dev->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) irq_base = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (irq_base < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) sizeof(*gpio_dev->saved_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!gpio_dev->saved_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) gpio_dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) gpio_dev->gc.get_direction = amd_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) gpio_dev->gc.direction_input = amd_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) gpio_dev->gc.direction_output = amd_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) gpio_dev->gc.get = amd_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) gpio_dev->gc.set = amd_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) gpio_dev->gc.set_config = amd_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) gpio_dev->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) gpio_dev->gc.label = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) gpio_dev->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) gpio_dev->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) gpio_dev->gc.ngpio = resource_size(res) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #if defined(CONFIG_OF_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) gpio_dev->gc.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) gpio_dev->groups = kerncz_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) amd_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (IS_ERR(gpio_dev->pctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return PTR_ERR(gpio_dev->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Disable and mask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) amd_gpio_irq_init(gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) girq = &gpio_dev->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) girq->chip = &amd_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) 0, 0, gpio_dev->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_err(&pdev->dev, "Failed to add pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) platform_set_drvdata(pdev, gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) gpiochip_remove(&gpio_dev->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int amd_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct amd_gpio *gpio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) gpio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) gpiochip_remove(&gpio_dev->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const struct acpi_device_id amd_gpio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { "AMD0030", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { "AMDI0030", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { "AMDI0031", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static struct platform_driver amd_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "amd_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .pm = &amd_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .probe = amd_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .remove = amd_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) module_platform_driver(amd_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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