^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2016-2018 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2016, Dell Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* GCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NPCM7XX_GCR_PDID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NPCM7XX_GCR_MFSEL1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NPCM7XX_GCR_MFSEL2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NPCM7XX_GCR_MFSEL3 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NPCM7XX_GCR_MFSEL4 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NPCM7XX_GCR_CPCTL 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NPCM7XX_GCR_CP2BST 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NPCM7XX_GCR_B2CPNT 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM7XX_GCR_I2CSEGSEL 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NPCM7XX_GCR_I2CSEGCTL 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NPCM7XX_GCR_SRCNT 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NPCM7XX_GCR_FLOCKR1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM7XX_GCR_DSCNT 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SRCNT_ESPI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM7XX_GP_N_TLOCK1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPCM7XX_GP_N_POL 0x08 /* Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM7XX_GP_N_OTYP 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM7XX_GP_N_MP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPCM7XX_GP_N_OBL0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NPCM7XX_GP_N_OBL1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPCM7XX_GP_N_OBL2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NPCM7XX_GP_N_OBL3 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NPCM7XX_GP_N_SPLCK 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NPCM7XX_GP_N_MPLCK 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NPCM7XX_GP_N_OSRC 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NPCM7XX_GP_N_ODSC 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NPCM7XX_GP_N_TLOCK2 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NPCM7XX_GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NPCM7XX_GPIO_BANK_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NPCM7XX_GCR_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Structure for register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct npcm7xx_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 pinctrl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int (*direction_input)(struct gpio_chip *chip, unsigned offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int (*direction_output)(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*request)(struct gpio_chip *chip, unsigned offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void (*free)(struct gpio_chip *chip, unsigned offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct npcm7xx_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regmap *gcr_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* GPIO handling in the pinctrl driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int pinmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = ioread32(reg) | pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iowrite32(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int pinmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = ioread32(reg) & ~pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) iowrite32(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) seq_printf(s, "-- module %d [gpio%d - %d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bank->gc.base / bank->gc.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bank->gc.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bank->gc.base + bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ioread32(bank->base + NPCM7XX_GP_N_DIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ioread32(bank->base + NPCM7XX_GP_N_DOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ioread32(bank->base + NPCM7XX_GP_N_IEM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ioread32(bank->base + NPCM7XX_GP_N_OE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ioread32(bank->base + NPCM7XX_GP_N_PU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ioread32(bank->base + NPCM7XX_GP_N_PD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ioread32(bank->base + NPCM7XX_GP_N_DBNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ioread32(bank->base + NPCM7XX_GP_N_POL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ioread32(bank->base + NPCM7XX_GP_N_EVBE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ioread32(bank->base + NPCM7XX_GP_N_EVEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ioread32(bank->base + NPCM7XX_GP_N_EVST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ioread32(bank->base + NPCM7XX_GP_N_OTYP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ioread32(bank->base + NPCM7XX_GP_N_OSRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ioread32(bank->base + NPCM7XX_GP_N_ODSC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ioread32(bank->base + NPCM7XX_GP_N_OBL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ioread32(bank->base + NPCM7XX_GP_N_OBL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ioread32(bank->base + NPCM7XX_GP_N_OBL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ioread32(bank->base + NPCM7XX_GP_N_OBL3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = pinctrl_gpio_direction_input(offset + chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return bank->direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Set GPIO to Output with initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int npcmgpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = pinctrl_gpio_direction_output(offset + chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return bank->direction_output(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = pinctrl_gpio_request(offset + chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return bank->request(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pinctrl_gpio_free(offset + chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void npcmgpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct npcm7xx_gpio *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 sts, en, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sts &= en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int gpio = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) d->irq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_dbg(bank->gc.parent, "edge.rising\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_dbg(bank->gc.parent, "edge.falling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(bank->gc.parent, "edge.both\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_dbg(bank->gc.parent, "level.low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_dbg(bank->gc.parent, "level.high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_dbg(bank->gc.parent, "invalid irq type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) | IRQ_TYPE_EDGE_FALLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void npcmgpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Disable GPIO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void npcmgpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Clear events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Enable GPIO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void npcmgpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Enable events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static unsigned int npcmgpio_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* active-high, input, clear interrupt, enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) npcmgpio_direction_input(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) npcmgpio_irq_ack(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) npcmgpio_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct irq_chip npcmgpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "NPCM7XX-GPIO-IRQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .irq_ack = npcmgpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .irq_unmask = npcmgpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .irq_mask = npcmgpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .irq_set_type = npcmgpio_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .irq_startup = npcmgpio_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* pinmux handing in the pinctrl driver*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const int smb0_pins[] = { 115, 114 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const int smb0b_pins[] = { 195, 194 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const int smb0c_pins[] = { 202, 196 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const int smb0d_pins[] = { 198, 199 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const int smb0den_pins[] = { 197 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const int smb1_pins[] = { 117, 116 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const int smb1b_pins[] = { 126, 127 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const int smb1c_pins[] = { 124, 125 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const int smb1d_pins[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const int smb2_pins[] = { 119, 118 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const int smb2b_pins[] = { 122, 123 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const int smb2c_pins[] = { 120, 121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const int smb2d_pins[] = { 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const int smb3_pins[] = { 30, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const int smb3b_pins[] = { 39, 40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const int smb3c_pins[] = { 37, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const int smb3d_pins[] = { 59, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const int smb4_pins[] = { 28, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const int smb4b_pins[] = { 18, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const int smb4c_pins[] = { 20, 21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const int smb4d_pins[] = { 22, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const int smb4den_pins[] = { 17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const int smb5_pins[] = { 26, 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const int smb5b_pins[] = { 13, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const int smb5c_pins[] = { 15, 14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const int smb5d_pins[] = { 94, 93 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const int ga20kbc_pins[] = { 94, 93 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const int smb6_pins[] = { 172, 171 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const int smb7_pins[] = { 174, 173 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const int smb8_pins[] = { 129, 128 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const int smb9_pins[] = { 131, 130 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const int smb10_pins[] = { 133, 132 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const int smb11_pins[] = { 135, 134 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const int smb12_pins[] = { 221, 220 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const int smb13_pins[] = { 223, 222 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const int smb14_pins[] = { 22, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const int smb15_pins[] = { 20, 21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const int fanin0_pins[] = { 64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const int fanin1_pins[] = { 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const int fanin2_pins[] = { 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const int fanin3_pins[] = { 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const int fanin4_pins[] = { 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const int fanin5_pins[] = { 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const int fanin6_pins[] = { 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const int fanin7_pins[] = { 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const int fanin8_pins[] = { 72 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const int fanin9_pins[] = { 73 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const int fanin10_pins[] = { 74 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const int fanin11_pins[] = { 75 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const int fanin12_pins[] = { 76 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const int fanin13_pins[] = { 77 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const int fanin14_pins[] = { 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const int fanin15_pins[] = { 79 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const int faninx_pins[] = { 175, 176, 177, 203 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const int pwm0_pins[] = { 80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const int pwm1_pins[] = { 81 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const int pwm2_pins[] = { 82 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const int pwm3_pins[] = { 83 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const int pwm4_pins[] = { 144 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const int pwm5_pins[] = { 145 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const int pwm6_pins[] = { 146 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const int pwm7_pins[] = { 147 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* RGMII 1 pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 106, 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* RGMII 1 MD interface pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const int rg1mdio_pins[] = { 108, 109 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* RGMII 2 pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 213, 214, 215 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* RGMII 2 MD interface pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const int rg2mdio_pins[] = { 216, 217 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 213, 214, 215, 216, 217 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Serial I/O Expander 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const int iox1_pins[] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Serial I/O Expander 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const int iox2_pins[] = { 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Host Serial I/O Expander 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const int ioxh_pins[] = { 10, 11, 24, 25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const int mmcwp_pins[] = { 153 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const int mmccd_pins[] = { 155 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const int mmcrst_pins[] = { 155 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const int mmc8_pins[] = { 148, 149, 150, 151 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* RMII 1 pin groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const int r1err_pins[] = { 56 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const int r1md_pins[] = { 57, 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* RMII 2 pin groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const int r2err_pins[] = { 90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const int r2md_pins[] = { 91, 92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const int sd1pwr_pins[] = { 143 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const int wdog1_pins[] = { 218 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const int wdog2_pins[] = { 219 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* BMC serial port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const int bmcuart0a_pins[] = { 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const int bmcuart0b_pins[] = { 48, 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* System Control Interrupt and Power Management Event pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const int scipme_pins[] = { 169 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* System Management Interrupt pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const int sci_pins[] = { 170 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Serial Interrupt Line pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const int serirq_pins[] = { 162 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const int clkout_pins[] = { 160 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const int clkreq_pins[] = { 231 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Graphics SPI Clock pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const int gspi_pins[] = { 12, 13, 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const int spixcs1_pins[] = { 228 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const int pspi1_pins[] = { 175, 176, 177 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const int pspi2_pins[] = { 17, 18, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const int spi0cs1_pins[] = { 32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const int spi3_pins[] = { 183, 184, 185, 186 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const int spi3cs1_pins[] = { 187 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const int spi3quad_pins[] = { 188, 189 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const int spi3cs2_pins[] = { 188 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const int spi3cs3_pins[] = { 189 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const int ddc_pins[] = { 204, 205, 206, 207 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const int lpcclk_pins[] = { 168 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const int lkgpo0_pins[] = { 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const int lkgpo1_pins[] = { 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const int lkgpo2_pins[] = { 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const int nprd_smi_pins[] = { 190 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * pin: name, number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * group: name, npins, pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * function: name, ngroups, groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct npcm7xx_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define NPCM7XX_GRPS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) NPCM7XX_GRP(smb0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) NPCM7XX_GRP(smb0b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) NPCM7XX_GRP(smb0c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) NPCM7XX_GRP(smb0d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) NPCM7XX_GRP(smb0den), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) NPCM7XX_GRP(smb1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) NPCM7XX_GRP(smb1b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) NPCM7XX_GRP(smb1c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) NPCM7XX_GRP(smb1d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) NPCM7XX_GRP(smb2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) NPCM7XX_GRP(smb2b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) NPCM7XX_GRP(smb2c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) NPCM7XX_GRP(smb2d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) NPCM7XX_GRP(smb3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) NPCM7XX_GRP(smb3b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) NPCM7XX_GRP(smb3c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) NPCM7XX_GRP(smb3d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) NPCM7XX_GRP(smb4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) NPCM7XX_GRP(smb4b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) NPCM7XX_GRP(smb4c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) NPCM7XX_GRP(smb4d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) NPCM7XX_GRP(smb4den), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) NPCM7XX_GRP(smb5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) NPCM7XX_GRP(smb5b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) NPCM7XX_GRP(smb5c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) NPCM7XX_GRP(smb5d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) NPCM7XX_GRP(ga20kbc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) NPCM7XX_GRP(smb6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) NPCM7XX_GRP(smb7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) NPCM7XX_GRP(smb8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) NPCM7XX_GRP(smb9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) NPCM7XX_GRP(smb10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) NPCM7XX_GRP(smb11), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) NPCM7XX_GRP(smb12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) NPCM7XX_GRP(smb13), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) NPCM7XX_GRP(smb14), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) NPCM7XX_GRP(smb15), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) NPCM7XX_GRP(fanin0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) NPCM7XX_GRP(fanin1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) NPCM7XX_GRP(fanin2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) NPCM7XX_GRP(fanin3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) NPCM7XX_GRP(fanin4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) NPCM7XX_GRP(fanin5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) NPCM7XX_GRP(fanin6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) NPCM7XX_GRP(fanin7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) NPCM7XX_GRP(fanin8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) NPCM7XX_GRP(fanin9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) NPCM7XX_GRP(fanin10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) NPCM7XX_GRP(fanin11), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) NPCM7XX_GRP(fanin12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) NPCM7XX_GRP(fanin13), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) NPCM7XX_GRP(fanin14), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) NPCM7XX_GRP(fanin15), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) NPCM7XX_GRP(faninx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) NPCM7XX_GRP(pwm0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) NPCM7XX_GRP(pwm1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) NPCM7XX_GRP(pwm2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) NPCM7XX_GRP(pwm3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) NPCM7XX_GRP(pwm4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) NPCM7XX_GRP(pwm5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) NPCM7XX_GRP(pwm6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) NPCM7XX_GRP(pwm7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) NPCM7XX_GRP(rg1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) NPCM7XX_GRP(rg1mdio), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) NPCM7XX_GRP(rg2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) NPCM7XX_GRP(rg2mdio), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) NPCM7XX_GRP(ddr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) NPCM7XX_GRP(uart1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) NPCM7XX_GRP(uart2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) NPCM7XX_GRP(bmcuart0a), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) NPCM7XX_GRP(bmcuart0b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) NPCM7XX_GRP(bmcuart1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) NPCM7XX_GRP(iox1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) NPCM7XX_GRP(iox2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) NPCM7XX_GRP(ioxh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) NPCM7XX_GRP(gspi), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) NPCM7XX_GRP(mmc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) NPCM7XX_GRP(mmcwp), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) NPCM7XX_GRP(mmccd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) NPCM7XX_GRP(mmcrst), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) NPCM7XX_GRP(mmc8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) NPCM7XX_GRP(r1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) NPCM7XX_GRP(r1err), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) NPCM7XX_GRP(r1md), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) NPCM7XX_GRP(r2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) NPCM7XX_GRP(r2err), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) NPCM7XX_GRP(r2md), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) NPCM7XX_GRP(sd1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) NPCM7XX_GRP(sd1pwr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) NPCM7XX_GRP(wdog1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) NPCM7XX_GRP(wdog2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) NPCM7XX_GRP(scipme), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) NPCM7XX_GRP(sci), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) NPCM7XX_GRP(serirq), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) NPCM7XX_GRP(jtag2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) NPCM7XX_GRP(spix), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) NPCM7XX_GRP(spixcs1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) NPCM7XX_GRP(pspi1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) NPCM7XX_GRP(pspi2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) NPCM7XX_GRP(ddc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) NPCM7XX_GRP(clkreq), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) NPCM7XX_GRP(clkout), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) NPCM7XX_GRP(spi3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) NPCM7XX_GRP(spi3cs1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) NPCM7XX_GRP(spi3quad), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) NPCM7XX_GRP(spi3cs2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) NPCM7XX_GRP(spi3cs3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) NPCM7XX_GRP(spi0cs1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) NPCM7XX_GRP(lpc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) NPCM7XX_GRP(lpcclk), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) NPCM7XX_GRP(espi), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) NPCM7XX_GRP(lkgpo0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) NPCM7XX_GRP(lkgpo1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) NPCM7XX_GRP(lkgpo2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) NPCM7XX_GRP(nprd_smi), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define NPCM7XX_GRP(x) fn_ ## x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) NPCM7XX_GRPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* add placeholder for none/gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) NPCM7XX_GRP(none),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) NPCM7XX_GRP(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #undef NPCM7XX_GRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct npcm7xx_group npcm7xx_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .npins = ARRAY_SIZE(x ## _pins) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) NPCM7XX_GRPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #undef NPCM7XX_GRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .groups = nm ## _grp }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct npcm7xx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) const char *const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) NPCM7XX_SFUNC(smb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) NPCM7XX_SFUNC(smb0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) NPCM7XX_SFUNC(smb0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) NPCM7XX_SFUNC(smb0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) NPCM7XX_SFUNC(smb0den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) NPCM7XX_SFUNC(smb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) NPCM7XX_SFUNC(smb1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) NPCM7XX_SFUNC(smb1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) NPCM7XX_SFUNC(smb1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) NPCM7XX_SFUNC(smb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) NPCM7XX_SFUNC(smb2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) NPCM7XX_SFUNC(smb2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) NPCM7XX_SFUNC(smb2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) NPCM7XX_SFUNC(smb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) NPCM7XX_SFUNC(smb3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) NPCM7XX_SFUNC(smb3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) NPCM7XX_SFUNC(smb3d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) NPCM7XX_SFUNC(smb4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) NPCM7XX_SFUNC(smb4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) NPCM7XX_SFUNC(smb4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) NPCM7XX_SFUNC(smb4d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) NPCM7XX_SFUNC(smb4den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) NPCM7XX_SFUNC(smb5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) NPCM7XX_SFUNC(smb5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) NPCM7XX_SFUNC(smb5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) NPCM7XX_SFUNC(smb5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) NPCM7XX_SFUNC(ga20kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) NPCM7XX_SFUNC(smb6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) NPCM7XX_SFUNC(smb7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) NPCM7XX_SFUNC(smb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) NPCM7XX_SFUNC(smb9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) NPCM7XX_SFUNC(smb10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) NPCM7XX_SFUNC(smb11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) NPCM7XX_SFUNC(smb12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) NPCM7XX_SFUNC(smb13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) NPCM7XX_SFUNC(smb14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) NPCM7XX_SFUNC(smb15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) NPCM7XX_SFUNC(fanin0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) NPCM7XX_SFUNC(fanin1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) NPCM7XX_SFUNC(fanin2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) NPCM7XX_SFUNC(fanin3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) NPCM7XX_SFUNC(fanin4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) NPCM7XX_SFUNC(fanin5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) NPCM7XX_SFUNC(fanin6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) NPCM7XX_SFUNC(fanin7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) NPCM7XX_SFUNC(fanin8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) NPCM7XX_SFUNC(fanin9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) NPCM7XX_SFUNC(fanin10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) NPCM7XX_SFUNC(fanin11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) NPCM7XX_SFUNC(fanin12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) NPCM7XX_SFUNC(fanin13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) NPCM7XX_SFUNC(fanin14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) NPCM7XX_SFUNC(fanin15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) NPCM7XX_SFUNC(faninx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) NPCM7XX_SFUNC(pwm0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) NPCM7XX_SFUNC(pwm1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) NPCM7XX_SFUNC(pwm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) NPCM7XX_SFUNC(pwm3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) NPCM7XX_SFUNC(pwm4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) NPCM7XX_SFUNC(pwm5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) NPCM7XX_SFUNC(pwm6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) NPCM7XX_SFUNC(pwm7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) NPCM7XX_SFUNC(rg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) NPCM7XX_SFUNC(rg1mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) NPCM7XX_SFUNC(rg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) NPCM7XX_SFUNC(rg2mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) NPCM7XX_SFUNC(ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) NPCM7XX_SFUNC(uart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) NPCM7XX_SFUNC(uart2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) NPCM7XX_SFUNC(bmcuart0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) NPCM7XX_SFUNC(bmcuart0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) NPCM7XX_SFUNC(bmcuart1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) NPCM7XX_SFUNC(iox1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) NPCM7XX_SFUNC(iox2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) NPCM7XX_SFUNC(ioxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) NPCM7XX_SFUNC(gspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) NPCM7XX_SFUNC(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) NPCM7XX_SFUNC(mmcwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) NPCM7XX_SFUNC(mmccd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) NPCM7XX_SFUNC(mmcrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) NPCM7XX_SFUNC(mmc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) NPCM7XX_SFUNC(r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) NPCM7XX_SFUNC(r1err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) NPCM7XX_SFUNC(r1md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) NPCM7XX_SFUNC(r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) NPCM7XX_SFUNC(r2err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) NPCM7XX_SFUNC(r2md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) NPCM7XX_SFUNC(sd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) NPCM7XX_SFUNC(sd1pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) NPCM7XX_SFUNC(wdog1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) NPCM7XX_SFUNC(wdog2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) NPCM7XX_SFUNC(scipme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) NPCM7XX_SFUNC(sci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) NPCM7XX_SFUNC(serirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) NPCM7XX_SFUNC(jtag2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) NPCM7XX_SFUNC(spix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) NPCM7XX_SFUNC(spixcs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) NPCM7XX_SFUNC(pspi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) NPCM7XX_SFUNC(pspi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) NPCM7XX_SFUNC(ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) NPCM7XX_SFUNC(clkreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) NPCM7XX_SFUNC(clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) NPCM7XX_SFUNC(spi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) NPCM7XX_SFUNC(spi3cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) NPCM7XX_SFUNC(spi3quad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) NPCM7XX_SFUNC(spi3cs2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) NPCM7XX_SFUNC(spi3cs3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) NPCM7XX_SFUNC(spi0cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) NPCM7XX_SFUNC(lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) NPCM7XX_SFUNC(lpcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) NPCM7XX_SFUNC(espi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) NPCM7XX_SFUNC(lkgpo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) NPCM7XX_SFUNC(lkgpo1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) NPCM7XX_SFUNC(lkgpo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) NPCM7XX_SFUNC(nprd_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Function names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct npcm7xx_func npcm7xx_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) NPCM7XX_MKFUNC(smb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) NPCM7XX_MKFUNC(smb0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) NPCM7XX_MKFUNC(smb0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) NPCM7XX_MKFUNC(smb0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) NPCM7XX_MKFUNC(smb0den),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) NPCM7XX_MKFUNC(smb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) NPCM7XX_MKFUNC(smb1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) NPCM7XX_MKFUNC(smb1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) NPCM7XX_MKFUNC(smb1d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) NPCM7XX_MKFUNC(smb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) NPCM7XX_MKFUNC(smb2b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) NPCM7XX_MKFUNC(smb2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) NPCM7XX_MKFUNC(smb2d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) NPCM7XX_MKFUNC(smb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) NPCM7XX_MKFUNC(smb3b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) NPCM7XX_MKFUNC(smb3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) NPCM7XX_MKFUNC(smb3d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) NPCM7XX_MKFUNC(smb4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) NPCM7XX_MKFUNC(smb4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) NPCM7XX_MKFUNC(smb4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) NPCM7XX_MKFUNC(smb4d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) NPCM7XX_MKFUNC(smb4den),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) NPCM7XX_MKFUNC(smb5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) NPCM7XX_MKFUNC(smb5b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) NPCM7XX_MKFUNC(smb5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) NPCM7XX_MKFUNC(smb5d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) NPCM7XX_MKFUNC(ga20kbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) NPCM7XX_MKFUNC(smb6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) NPCM7XX_MKFUNC(smb7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) NPCM7XX_MKFUNC(smb8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) NPCM7XX_MKFUNC(smb9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) NPCM7XX_MKFUNC(smb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) NPCM7XX_MKFUNC(smb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) NPCM7XX_MKFUNC(smb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) NPCM7XX_MKFUNC(smb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) NPCM7XX_MKFUNC(smb14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) NPCM7XX_MKFUNC(smb15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) NPCM7XX_MKFUNC(fanin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) NPCM7XX_MKFUNC(fanin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) NPCM7XX_MKFUNC(fanin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) NPCM7XX_MKFUNC(fanin3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) NPCM7XX_MKFUNC(fanin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) NPCM7XX_MKFUNC(fanin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) NPCM7XX_MKFUNC(fanin6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) NPCM7XX_MKFUNC(fanin7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) NPCM7XX_MKFUNC(fanin8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) NPCM7XX_MKFUNC(fanin9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) NPCM7XX_MKFUNC(fanin10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) NPCM7XX_MKFUNC(fanin11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) NPCM7XX_MKFUNC(fanin12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) NPCM7XX_MKFUNC(fanin13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) NPCM7XX_MKFUNC(fanin14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) NPCM7XX_MKFUNC(fanin15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) NPCM7XX_MKFUNC(faninx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) NPCM7XX_MKFUNC(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) NPCM7XX_MKFUNC(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) NPCM7XX_MKFUNC(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) NPCM7XX_MKFUNC(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) NPCM7XX_MKFUNC(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) NPCM7XX_MKFUNC(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) NPCM7XX_MKFUNC(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) NPCM7XX_MKFUNC(pwm7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) NPCM7XX_MKFUNC(rg1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) NPCM7XX_MKFUNC(rg1mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) NPCM7XX_MKFUNC(rg2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) NPCM7XX_MKFUNC(rg2mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) NPCM7XX_MKFUNC(ddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) NPCM7XX_MKFUNC(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) NPCM7XX_MKFUNC(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) NPCM7XX_MKFUNC(bmcuart0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) NPCM7XX_MKFUNC(bmcuart0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) NPCM7XX_MKFUNC(bmcuart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) NPCM7XX_MKFUNC(iox1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) NPCM7XX_MKFUNC(iox2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) NPCM7XX_MKFUNC(ioxh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) NPCM7XX_MKFUNC(gspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) NPCM7XX_MKFUNC(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) NPCM7XX_MKFUNC(mmcwp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) NPCM7XX_MKFUNC(mmccd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) NPCM7XX_MKFUNC(mmcrst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) NPCM7XX_MKFUNC(mmc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) NPCM7XX_MKFUNC(r1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) NPCM7XX_MKFUNC(r1err),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) NPCM7XX_MKFUNC(r1md),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) NPCM7XX_MKFUNC(r2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) NPCM7XX_MKFUNC(r2err),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) NPCM7XX_MKFUNC(r2md),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) NPCM7XX_MKFUNC(sd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) NPCM7XX_MKFUNC(sd1pwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) NPCM7XX_MKFUNC(wdog1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) NPCM7XX_MKFUNC(wdog2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) NPCM7XX_MKFUNC(scipme),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) NPCM7XX_MKFUNC(sci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) NPCM7XX_MKFUNC(serirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) NPCM7XX_MKFUNC(jtag2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) NPCM7XX_MKFUNC(spix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) NPCM7XX_MKFUNC(spixcs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) NPCM7XX_MKFUNC(pspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) NPCM7XX_MKFUNC(pspi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) NPCM7XX_MKFUNC(ddc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) NPCM7XX_MKFUNC(clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) NPCM7XX_MKFUNC(clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) NPCM7XX_MKFUNC(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) NPCM7XX_MKFUNC(spi3cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) NPCM7XX_MKFUNC(spi3quad),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) NPCM7XX_MKFUNC(spi3cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) NPCM7XX_MKFUNC(spi3cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) NPCM7XX_MKFUNC(spi0cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) NPCM7XX_MKFUNC(lpc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) NPCM7XX_MKFUNC(lpcclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) NPCM7XX_MKFUNC(espi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) NPCM7XX_MKFUNC(lkgpo0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) NPCM7XX_MKFUNC(lkgpo1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) NPCM7XX_MKFUNC(lkgpo2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) NPCM7XX_MKFUNC(nprd_smi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .flag = k }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Drive strength controlled by NPCM7XX_GP_N_ODSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define DRIVE_STRENGTH_LO_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define DRIVE_STRENGTH_HI_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define DRIVE_STRENGTH_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ((hi) << DRIVE_STRENGTH_HI_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define GPI 0x1 /* Not GPO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define GPO 0x2 /* Not GPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct npcm7xx_pincfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int fn0, reg0, bit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int fn1, reg1, bit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int fn2, reg2, bit2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct npcm7xx_pincfg pincfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* number, name, drv_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct pinctrl_pin_desc npcm7xx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINCTRL_PIN(0, "GPIO0/IOX1DI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINCTRL_PIN(1, "GPIO1/IOX1LD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINCTRL_PIN(2, "GPIO2/IOX1CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINCTRL_PIN(3, "GPIO3/IOX1D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINCTRL_PIN(8, "GPIO8/LKGPO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINCTRL_PIN(9, "GPIO9/LKGPO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINCTRL_PIN(10, "GPIO10/IOXHLD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINCTRL_PIN(11, "GPIO11/IOXHCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINCTRL_PIN(16, "GPIO16/LKGPO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINCTRL_PIN(24, "GPIO24/IOXHDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINCTRL_PIN(25, "GPIO25/IOXHDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINCTRL_PIN(26, "GPIO26/SMB5SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINCTRL_PIN(27, "GPIO27/SMB5SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINCTRL_PIN(28, "GPIO28/SMB4SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINCTRL_PIN(29, "GPIO29/SMB4SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINCTRL_PIN(30, "GPIO30/SMB3SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINCTRL_PIN(31, "GPIO31/SMB3SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINCTRL_PIN(33, "SPI0D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINCTRL_PIN(34, "SPI0D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINCTRL_PIN(41, "GPIO41/BSPRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINCTRL_PIN(50, "GPIO50/nCTS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINCTRL_PIN(52, "GPIO52/nDCD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINCTRL_PIN(54, "GPIO54/nDSR2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINCTRL_PIN(55, "GPIO55/nRI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINCTRL_PIN(56, "GPIO56/R1RXERR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINCTRL_PIN(57, "GPIO57/R1MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINCTRL_PIN(58, "GPIO58/R1MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINCTRL_PIN(64, "GPIO64/FANIN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINCTRL_PIN(65, "GPIO65/FANIN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINCTRL_PIN(66, "GPIO66/FANIN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINCTRL_PIN(67, "GPIO67/FANIN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINCTRL_PIN(68, "GPIO68/FANIN4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINCTRL_PIN(69, "GPIO69/FANIN5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINCTRL_PIN(70, "GPIO70/FANIN6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINCTRL_PIN(71, "GPIO71/FANIN7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINCTRL_PIN(72, "GPIO72/FANIN8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINCTRL_PIN(73, "GPIO73/FANIN9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINCTRL_PIN(74, "GPIO74/FANIN10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINCTRL_PIN(75, "GPIO75/FANIN11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINCTRL_PIN(76, "GPIO76/FANIN12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINCTRL_PIN(77, "GPIO77/FANIN13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINCTRL_PIN(78, "GPIO78/FANIN14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINCTRL_PIN(79, "GPIO79/FANIN15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINCTRL_PIN(80, "GPIO80/PWM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINCTRL_PIN(81, "GPIO81/PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINCTRL_PIN(82, "GPIO82/PWM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINCTRL_PIN(83, "GPIO83/PWM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINCTRL_PIN(84, "GPIO84/R2TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINCTRL_PIN(85, "GPIO85/R2TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINCTRL_PIN(86, "GPIO86/R2TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINCTRL_PIN(87, "GPIO87/R2RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINCTRL_PIN(88, "GPIO88/R2RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINCTRL_PIN(89, "GPIO89/R2CRSDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINCTRL_PIN(90, "GPIO90/R2RXERR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINCTRL_PIN(91, "GPIO91/R2MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINCTRL_PIN(92, "GPIO92/R2MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINCTRL_PIN(96, "GPIO96/RG1TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINCTRL_PIN(97, "GPIO97/RG1TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINCTRL_PIN(98, "GPIO98/RG1TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINCTRL_PIN(99, "GPIO99/RG1TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINCTRL_PIN(100, "GPIO100/RG1TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINCTRL_PIN(102, "GPIO102/RG1RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINCTRL_PIN(103, "GPIO103/RG1RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINCTRL_PIN(104, "GPIO104/RG1RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINCTRL_PIN(105, "GPIO105/RG1RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINCTRL_PIN(106, "GPIO106/RG1RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINCTRL_PIN(108, "GPIO108/RG1MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINCTRL_PIN(109, "GPIO109/RG1MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINCTRL_PIN(114, "GPIO114/SMB0SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINCTRL_PIN(115, "GPIO115/SMB0SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINCTRL_PIN(116, "GPIO116/SMB1SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINCTRL_PIN(117, "GPIO117/SMB1SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINCTRL_PIN(118, "GPIO118/SMB2SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINCTRL_PIN(119, "GPIO119/SMB2SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINCTRL_PIN(128, "GPIO128/SMB8SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINCTRL_PIN(129, "GPIO129/SMB8SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINCTRL_PIN(130, "GPIO130/SMB9SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINCTRL_PIN(131, "GPIO131/SMB9SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINCTRL_PIN(132, "GPIO132/SMB10SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINCTRL_PIN(133, "GPIO133/SMB10SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINCTRL_PIN(134, "GPIO134/SMB11SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINCTRL_PIN(135, "GPIO135/SMB11SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINCTRL_PIN(136, "GPIO136/SD1DT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINCTRL_PIN(137, "GPIO137/SD1DT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINCTRL_PIN(138, "GPIO138/SD1DT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINCTRL_PIN(139, "GPIO139/SD1DT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINCTRL_PIN(140, "GPIO140/SD1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINCTRL_PIN(141, "GPIO141/SD1WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINCTRL_PIN(142, "GPIO142/SD1CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINCTRL_PIN(144, "GPIO144/PWM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINCTRL_PIN(145, "GPIO145/PWM5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINCTRL_PIN(146, "GPIO146/PWM6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINCTRL_PIN(147, "GPIO147/PWM7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINCTRL_PIN(148, "GPIO148/MMCDT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINCTRL_PIN(149, "GPIO149/MMCDT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINCTRL_PIN(150, "GPIO150/MMCDT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINCTRL_PIN(151, "GPIO151/MMCDT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINCTRL_PIN(152, "GPIO152/MMCCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINCTRL_PIN(153, "GPIO153/MMCWP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINCTRL_PIN(154, "GPIO154/MMCCMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINCTRL_PIN(156, "GPIO156/MMCDT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINCTRL_PIN(157, "GPIO157/MMCDT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINCTRL_PIN(158, "GPIO158/MMCDT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINCTRL_PIN(159, "GPIO159/MMCDT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINCTRL_PIN(162, "GPIO162/SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINCTRL_PIN(169, "GPIO169/nSCIPME"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINCTRL_PIN(170, "GPIO170/nSMI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINCTRL_PIN(171, "GPIO171/SMB6SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINCTRL_PIN(172, "GPIO172/SMB6SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINCTRL_PIN(173, "GPIO173/SMB7SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINCTRL_PIN(174, "GPIO174/SMB7SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINCTRL_PIN(178, "GPIO178/R1TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINCTRL_PIN(179, "GPIO179/R1TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINCTRL_PIN(180, "GPIO180/R1TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINCTRL_PIN(181, "GPIO181/R1RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINCTRL_PIN(182, "GPIO182/R1RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINCTRL_PIN(183, "GPIO183/SPI3CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINCTRL_PIN(191, "GPIO191"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINCTRL_PIN(192, "GPIO192"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINCTRL_PIN(193, "GPIO193/R1CRSDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINCTRL_PIN(197, "GPIO197/SMB0DEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINCTRL_PIN(200, "GPIO200/R2CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINCTRL_PIN(201, "GPIO201/R1CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINCTRL_PIN(203, "GPIO203/FANIN16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINCTRL_PIN(204, "GPIO204/DDC2SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINCTRL_PIN(205, "GPIO205/DDC2SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINCTRL_PIN(206, "GPIO206/HSYNC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINCTRL_PIN(207, "GPIO207/VSYNC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINCTRL_PIN(218, "GPIO218/nWDO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINCTRL_PIN(219, "GPIO219/nWDO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINCTRL_PIN(220, "GPIO220/SMB12SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINCTRL_PIN(221, "GPIO221/SMB12SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINCTRL_PIN(222, "GPIO222/SMB13SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINCTRL_PIN(223, "GPIO223/SMB13SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINCTRL_PIN(224, "GPIO224/SPIXCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINCTRL_PIN(230, "GPIO230/SPIXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINCTRL_PIN(231, "GPIO231/nCLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINCTRL_PIN(255, "GPI255/DACOSEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Enable mode in pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) int pin_number, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) const struct npcm7xx_pincfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) for (i = 0 ; i < pin_number ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) cfg = &pincfg[pin[i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (cfg->reg0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) regmap_update_bits(gcr_regmap, cfg->reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) BIT(cfg->bit0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) !!(cfg->fn0 == mode) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) BIT(cfg->bit0) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (cfg->reg1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) regmap_update_bits(gcr_regmap, cfg->reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) BIT(cfg->bit1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) !!(cfg->fn1 == mode) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) BIT(cfg->bit1) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (cfg->reg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) regmap_update_bits(gcr_regmap, cfg->reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) BIT(cfg->bit2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) !!(cfg->fn2 == mode) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) BIT(cfg->bit2) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Get slew rate of pin (high/low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct regmap *gcr_regmap, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) int gpio = (pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) unsigned long pinmask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (pincfg[pin].flag & SLEW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* LPC Slew rate in SRCNT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (pincfg[pin].flag & SLEWLPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return !!(val & SRCNT_ESPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Set slew rate of pin (high/low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct regmap *gcr_regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int gpio = BIT(pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (pincfg[pin].flag & SLEW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* LPC Slew rate in SRCNT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (pincfg[pin].flag & SLEWLPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SRCNT_ESPI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) SRCNT_ESPI, SRCNT_ESPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Get drive strength for a pin, if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) int gpio = (pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) unsigned long pinmask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) u32 ds = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int flg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) flg = pincfg[pin].flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (flg & DRIVE_STRENGTH_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* Get standard reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ds = val ? DSHI(flg) : DSLO(flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_dbg(bank->gc.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) "pin %d strength %d = %d\n", pin, val, ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Set drive strength for a pin, if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) unsigned int pin, int nval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) int gpio = BIT(pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (!nval || !v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (DSLO(v) == nval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_dbg(bank->gc.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) "setting pin %d to low strength [%d]\n", pin, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } else if (DSHI(v) == nval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev_dbg(bank->gc.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) "setting pin %d to high strength [%d]\n", pin, nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* pinctrl_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct seq_file *s, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) seq_printf(s, "pinctrl_ops.dbg: %d", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return ARRAY_SIZE(npcm7xx_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return npcm7xx_groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) *npins = npcm7xx_groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) *pins = npcm7xx_groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) u32 *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return pinconf_generic_dt_node_to_map(pctldev, np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) map, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) PIN_MAP_TYPE_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct pinctrl_map *map, u32 num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .get_groups_count = npcm7xx_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .get_group_name = npcm7xx_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .get_group_pins = npcm7xx_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .pin_dbg_show = npcm7xx_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .dt_node_to_map = npcm7xx_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .dt_free_map = npcm7xx_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* pinmux_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ARRAY_SIZE(npcm7xx_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return npcm7xx_funcs[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unsigned int * const ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) *ngroups = npcm7xx_funcs[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) *groups = npcm7xx_funcs[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) npcm7xx_groups[group].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) npcm7xx_groups[group].npins, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) dev_err(npcm->dev, "invalid range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (!range->gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dev_err(npcm->dev, "invalid gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Release GPIO back to pinctrl mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) virq = irq_find_mapping(npcm->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) irq_dispose_mapping(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* Set GPIO direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) int gpio = BIT(offset % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const struct pinmux_ops npcm7xx_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .get_functions_count = npcm7xx_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .get_function_name = npcm7xx_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .get_function_groups = npcm7xx_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .set_mux = npcm7xx_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .gpio_request_enable = npcm7xx_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .gpio_disable_free = npcm7xx_gpio_request_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .gpio_set_direction = npcm_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* pinconf_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int gpio = (pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) unsigned long pinmask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) u32 ie, oe, pu, pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (param == PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) rc = (!pu && !pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) else if (param == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) rc = (pu && !pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) rc = (!pu && pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (param == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) rc = (ie && !oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) else if (param == PIN_CONFIG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) rc = (!ie && oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) rc = npcm7xx_get_drive_strength(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) *config = pinconf_to_config_packed(param, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (rc >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) *config = pinconf_to_config_packed(param, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) unsigned int pin, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) enum pin_config_param param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u16 arg = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct npcm7xx_gpio *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) int gpio = BIT(pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return npcm7xx_set_drive_strength(npcm, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* Set multiple configuration settings for a pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) while (num_configs--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) rc = npcm7xx_config_set_one(npcm, pin, *configs++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static const struct pinconf_ops npcm7xx_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .pin_config_get = npcm7xx_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .pin_config_set = npcm7xx_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* pinctrl_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static struct pinctrl_desc npcm7xx_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .name = "npcm7xx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .pins = npcm7xx_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .npins = ARRAY_SIZE(npcm7xx_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .pctlops = &npcm7xx_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .pmxops = &npcm7xx_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .confops = &npcm7xx_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) int ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) int id = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct of_phandle_args pinspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) for_each_available_child_of_node(pctrl->dev->of_node, np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (of_find_property(np, "gpio-controller", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev_err(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) "Resource fail for GPIO bank %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) pctrl->gpio_bank[id].base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_err(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "No IRQ for GPIO bank %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ret = bgpio_init(&pctrl->gpio_bank[id].gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) pctrl->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) pctrl->gpio_bank[id].base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) NPCM7XX_GP_N_DIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) pctrl->gpio_bank[id].base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) NPCM7XX_GP_N_DOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pctrl->gpio_bank[id].base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) NPCM7XX_GP_N_IEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) BGPIOF_READ_OUTPUT_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) dev_err(pctrl->dev, "bgpio_init() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = of_parse_phandle_with_fixed_args(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) "gpio-ranges", 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) 0, &pinspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dev_err(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) "gpio-ranges fail for GPIO bank %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) pctrl->gpio_bank[id].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) pctrl->gpio_bank[id].gc.parent = pctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) pctrl->gpio_bank[id].irqbase =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) id * NPCM7XX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) pctrl->gpio_bank[id].pinctrl_id = pinspec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) pctrl->gpio_bank[id].gc.base = pinspec.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) pctrl->gpio_bank[id].gc.ngpio = pinspec.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) pctrl->gpio_bank[id].gc.label =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (pctrl->gpio_bank[id].gc.label == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) pctrl->gpio_bank[id].direction_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) pctrl->gpio_bank[id].gc.direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) pctrl->gpio_bank[id].gc.direction_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) npcmgpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pctrl->gpio_bank[id].direction_output =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) pctrl->gpio_bank[id].gc.direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) pctrl->gpio_bank[id].gc.direction_output =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) npcmgpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) pctrl->gpio_bank[id].request =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) pctrl->gpio_bank[id].gc.request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) pctrl->gpio_bank[id].gc.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) pctrl->bank_num = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) int ret, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) for (id = 0 ; id < pctrl->bank_num ; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) girq = &pctrl->gpio_bank[id].gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) girq->chip = &pctrl->gpio_bank[id].irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) girq->parent_handler = npcmgpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) girq->parents = devm_kcalloc(pctrl->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) girq->parents[0] = pctrl->gpio_bank[id].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ret = devm_gpiochip_add_data(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) &pctrl->gpio_bank[id].gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) &pctrl->gpio_bank[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) dev_name(pctrl->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pctrl->gpio_bank[id].pinctrl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) pctrl->gpio_bank[id].gc.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) pctrl->gpio_bank[id].gc.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) gpiochip_remove(&pctrl->gpio_bank[id].gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) for (; id > 0; id--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static int npcm7xx_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct npcm7xx_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) pctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dev_set_drvdata(&pdev->dev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) pctrl->gcr_regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (IS_ERR(pctrl->gcr_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return PTR_ERR(pctrl->gcr_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ret = npcm7xx_gpio_of(pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) pctrl->pctldev = devm_pinctrl_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) &npcm7xx_pinctrl_desc, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (IS_ERR(pctrl->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) dev_err(&pdev->dev, "Failed to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) return PTR_ERR(pctrl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ret = npcm7xx_gpio_register(pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) pr_info("NPCM7xx Pinctrl driver probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const struct of_device_id npcm7xx_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) { .compatible = "nuvoton,npcm750-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct platform_driver npcm7xx_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .probe = npcm7xx_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .name = "npcm7xx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .of_match_table = npcm7xx_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int __init npcm7xx_pinctrl_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return platform_driver_register(&npcm7xx_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) arch_initcall(npcm7xx_pinctrl_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) MODULE_AUTHOR("jordan_hargrave@dell.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) MODULE_AUTHOR("tomer.maimon@nuvoton.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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