^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic GPIO driver for logic cells found in the Nomadik SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008,2009 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Since we request GPIOs from ourself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pinctrl-nomadik.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The GPIO module in the Nomadik family of Systems-on-Chip is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * AMBA device, managing 32 pins and alternate functions. The logic block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * is currently used in the Nomadik and ux500.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * pin configurations are represented by 32-bit integers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * bit 0.. 8 - Pin Number (512 Pins Maximum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * bit 9..10 - Alternate Function Selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * bit 11..12 - Pull up/down state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * bit 13 - Sleep mode behaviour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * bit 14 - Direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * bit 15 - Value (if output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * bit 16..18 - SLPM pull up/down state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * bit 19..20 - SLPM direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * bit 21..22 - SLPM Value (if output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * bit 23..25 - PDIS value (if input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * bit 26 - Gpio mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * bit 27 - Sleep mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * to facilitate the definition, the following macros are provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * PIN_CFG_DEFAULT - default config (0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * pull up/down = disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * sleep mode = input/wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * direction = input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * value = low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * SLPM direction = same as normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * SLPM pull = same as normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * SLPM value = same as normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * PIN_CFG - default config with alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) typedef unsigned long pin_cfg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PIN_NUM_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PIN_ALT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PIN_PULL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PIN_SLPM_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* These two replace the above in DB8500v2+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PIN_DIR_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PIN_VAL_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PIN_SLPM_PULL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PIN_SLPM_PULL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PIN_SLPM_PULL_NONE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PIN_SLPM_PULL_UP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PIN_SLPM_PULL_DOWN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PIN_SLPM_DIR_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PIN_SLPM_DIR(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PIN_SLPM_VAL_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PIN_SLPM_VAL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PIN_SLPM_PDIS_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PIN_SLPM_PDIS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PIN_LOWEMI_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PIN_GPIOMODE_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PIN_SLEEPMODE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PIN_CFG_DEFAULT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PIN_CFG(num, alt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (PIN_CFG_DEFAULT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (PIN_NUM(num) | PIN_##alt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PIN_CFG_INPUT(num, alt, pull) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (PIN_CFG_DEFAULT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PIN_CFG_OUTPUT(num, alt, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (PIN_CFG_DEFAULT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * the "gpio" namespace for generic and cross-machine functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GPIO_BLOCK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Register in the logic block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define NMK_GPIO_DAT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define NMK_GPIO_DATS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define NMK_GPIO_DATC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define NMK_GPIO_PDIS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define NMK_GPIO_DIR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define NMK_GPIO_DIRS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define NMK_GPIO_DIRC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define NMK_GPIO_SLPC 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define NMK_GPIO_AFSLA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define NMK_GPIO_AFSLB 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define NMK_GPIO_LOWEMI 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define NMK_GPIO_RIMSC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define NMK_GPIO_FIMSC 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NMK_GPIO_IS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NMK_GPIO_IC 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define NMK_GPIO_RWIMSC 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define NMK_GPIO_FWIMSC 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NMK_GPIO_WKS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* These appear in DB8540 and later ASICs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define NMK_GPIO_EDGELEVEL 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define NMK_GPIO_LEVEL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Pull up/down values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum nmk_gpio_pull {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) NMK_GPIO_PULL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) NMK_GPIO_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) NMK_GPIO_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum nmk_gpio_slpm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) NMK_GPIO_SLPM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) NMK_GPIO_SLPM_NOCHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct nmk_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void (*set_ioforce)(bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bool sleepmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Keep track of configured edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 edge_rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 edge_falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 real_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 rwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 fwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 rimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 fimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 pull_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 lowemi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * struct nmk_pinctrl - state container for the Nomadik pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @dev: containing device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @pctl: corresponding pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @soc: SoC data for this specific chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @prcm_base: PRCM register range virtual base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct nmk_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct nmk_pinctrl_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void __iomem *prcm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned offset, int gpio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 afunc, bfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (gpio_mode & NMK_GPIO_ALT_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) afunc |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (gpio_mode & NMK_GPIO_ALT_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bfunc |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned offset, enum nmk_gpio_slpm mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 slpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (mode == NMK_GPIO_SLPM_NOCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) slpm |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) slpm &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned offset, enum nmk_gpio_pull pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 pdis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (pull == NMK_GPIO_PULL_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pdis |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) nmk_chip->pull_up &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pdis &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (pull == NMK_GPIO_PULL_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) nmk_chip->pull_up |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else if (pull == NMK_GPIO_PULL_DOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) nmk_chip->pull_up &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned offset, bool lowemi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool enabled = nmk_chip->lowemi & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (lowemi == enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (lowemi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) nmk_chip->lowemi |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) nmk_chip->lowemi &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) writel_relaxed(nmk_chip->lowemi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) nmk_chip->addr + NMK_GPIO_LOWEMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __nmk_gpio_set_output(nmk_chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned offset, int gpio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bool glitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 rwimsc = nmk_chip->rwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 fwimsc = nmk_chip->fwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (glitch && nmk_chip->set_ioforce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Prevent spurious wakeups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) nmk_chip->set_ioforce(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (glitch && nmk_chip->set_ioforce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) nmk_chip->set_ioforce(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 falling = nmk_chip->fimsc & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 rising = nmk_chip->rimsc & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int gpio = nmk_chip->chip.base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct irq_data *d = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!rising && !falling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!d || !irqd_irq_disabled(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (rising) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) nmk_chip->rimsc &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel_relaxed(nmk_chip->rimsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) nmk_chip->addr + NMK_GPIO_RIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (falling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) nmk_chip->fimsc &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writel_relaxed(nmk_chip->fimsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) nmk_chip->addr + NMK_GPIO_FIMSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = ((val & ~mask) | (value & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned offset, unsigned alt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 alt_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const u16 *gpiocr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!npct->prcm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) alt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (npct->soc->altcx_pins[i].pin == offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (i == npct->soc->npins_altcx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pin_desc = npct->soc->altcx_pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) gpiocr_regs = npct->soc->prcm_gpiocr_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * If alt_num is NULL, just clear current ALTCx selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * to make sure we come back to a pure ALTC selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!alt_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (pin_desc->altcx[i].used == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bit = pin_desc->altcx[i].control_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (readl(npct->prcm_base + reg) & BIT(bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(npct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) offset, i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) alt_index = alt_num - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (pin_desc->altcx[alt_index].used == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_warn(npct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) offset, alt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Check if any other ALTCx functions are activated on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * and disable it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (i == alt_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (pin_desc->altcx[i].used == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bit = pin_desc->altcx[i].control_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (readl(npct->prcm_base + reg) & BIT(bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(npct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) offset, i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bit = pin_desc->altcx[alt_index].control_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) offset, alt_index+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * - Save SLPM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * - Set SLPM=0 for the IOs you want to switch and others to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * - Configure the GPIO registers for the IOs that are being switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * - Set IOFORCE=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * - Modify the AFLSA/B registers for the IOs that are being switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * - Set IOFORCE=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * - Restore SLPM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * - Any spurious wake up event during switch sequence to be ignored and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < NUM_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int temp = slpm[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clk_enable(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(temp, chip->addr + NMK_GPIO_SLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < NUM_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) clk_disable(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const u16 *gpiocr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!npct->prcm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return NMK_GPIO_ALT_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) for (i = 0; i < npct->soc->npins_altcx; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (npct->soc->altcx_pins[i].pin == gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (i == npct->soc->npins_altcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return NMK_GPIO_ALT_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pin_desc = npct->soc->altcx_pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gpiocr_regs = npct->soc->prcm_gpiocr_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (pin_desc->altcx[i].used == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bit = pin_desc->altcx[i].control_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (readl(npct->prcm_base + reg) & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return NMK_GPIO_ALT_C+i+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return NMK_GPIO_ALT_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* IRQ functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void nmk_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) enum nmk_gpio_irq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int offset, enum nmk_gpio_irq_type which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 *rimscval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 *fimscval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 rimscreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 fimscreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (which == NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) rimscreg = NMK_GPIO_RIMSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fimscreg = NMK_GPIO_FIMSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rimscval = &nmk_chip->rimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fimscval = &nmk_chip->fimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rimscreg = NMK_GPIO_RWIMSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) fimscreg = NMK_GPIO_FWIMSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rimscval = &nmk_chip->rwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) fimscval = &nmk_chip->fwimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* we must individually set/clear the two edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (nmk_chip->edge_rising & BIT(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *rimscval |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *rimscval &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) writel(*rimscval, nmk_chip->addr + rimscreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (nmk_chip->edge_falling & BIT(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *fimscval |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) *fimscval &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writel(*fimscval, nmk_chip->addr + fimscreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int offset, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * disabled, since setting SLPM to 1 increases power consumption, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (nmk_chip->sleepmode && on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __nmk_gpio_set_slpm(nmk_chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) NMK_GPIO_SLPM_WAKEUP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) nmk_chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!nmk_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_lock(&nmk_chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!(nmk_chip->real_wake & BIT(d->hwirq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spin_unlock(&nmk_chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void nmk_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) nmk_gpio_irq_maskunmask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void nmk_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) nmk_gpio_irq_maskunmask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) nmk_chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!nmk_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock(&nmk_chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (irqd_irq_disabled(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) nmk_chip->real_wake |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) nmk_chip->real_wake &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) spin_unlock(&nmk_chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bool enabled = !irqd_irq_disabled(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bool wake = irqd_is_wakeup_set(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) nmk_chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!nmk_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (type & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (type & IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_lock_irqsave(&nmk_chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (enabled || wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) nmk_chip->edge_rising &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) nmk_chip->edge_rising |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) nmk_chip->edge_falling &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) nmk_chip->edge_falling |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (enabled || wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) spin_unlock_irqrestore(&nmk_chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) nmk_gpio_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void nmk_gpio_irq_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) nmk_gpio_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void nmk_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct irq_chip *host_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) chained_irq_enter(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) status = readl(nmk_chip->addr + NMK_GPIO_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int bit = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) status &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) chained_irq_exit(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* I/O Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __nmk_gpio_set_output(nmk_chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __nmk_gpio_make_output(nmk_chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 afunc, bfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static void nmk_gpio_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct pinctrl_dev *pctldev, struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned offset, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const char *label = gpiochip_is_requested(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) bool is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) bool data_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bool pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) const char *modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [NMK_GPIO_ALT_GPIO] = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [NMK_GPIO_ALT_A] = "altA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [NMK_GPIO_ALT_B] = "altB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [NMK_GPIO_ALT_C] = "altC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [NMK_GPIO_ALT_C+1] = "altC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [NMK_GPIO_ALT_C+2] = "altC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [NMK_GPIO_ALT_C+3] = "altC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [NMK_GPIO_ALT_C+4] = "altC4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mode = nmk_gpio_get_mode(nmk_chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if ((mode == NMK_GPIO_ALT_C) && pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (is_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) label ?: "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) data_out ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) (mode < 0) ? "unknown" : modes[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int irq = chip->to_irq(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct irq_desc *desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) const int pullidx = pull ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const char * const pulls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) "none ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "pull enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) label ?: "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) pulls[pullidx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) (mode < 0) ? "unknown" : modes[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) val = nmk_gpio_get_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) seq_printf(s, " VAL %d", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * This races with request_irq(), set_irq_type(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * and set_irq_wake() ... but those are "rare".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (irq > 0 && desc && desc->action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) char *trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (nmk_chip->edge_rising & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) trigger = "edge-rising";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) else if (nmk_chip->edge_falling & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) trigger = "edge-falling";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) trigger = "edge-undefined";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) seq_printf(s, " irq-%d %s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) irq, trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) irqd_is_wakeup_set(&desc->irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ? " wakeup" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned gpio = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) for (i = 0; i < chip->ngpio; i++, gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) seq_printf(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned offset, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define nmk_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * We will allocate memory for the state container using devm* allocators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * binding to the first device reaching this point, it doesn't matter if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * it is the pin controller or GPIO driver. However we need to use the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * platform device when looking up resources so pay attention to pdev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct platform_device *gpio_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) gpio_pdev = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!gpio_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) pr_err("populate \"%pOFn\": device not found\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (of_property_read_u32(np, "gpio-bank", &id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) platform_device_put(gpio_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Already populated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) nmk_chip = nmk_gpio_chips[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (nmk_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) platform_device_put(gpio_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (!nmk_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) platform_device_put(gpio_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) nmk_chip->bank = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) chip = &nmk_chip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) chip->base = id * NMK_GPIO_PER_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) chip->ngpio = NMK_GPIO_PER_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) chip->label = dev_name(&gpio_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) chip->parent = &gpio_pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) platform_device_put(gpio_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ERR_CAST(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) nmk_chip->addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) clk = clk_get(&gpio_pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) platform_device_put(gpio_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return (void *) clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) clk_prepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) nmk_chip->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) nmk_gpio_chips[id] = nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int nmk_gpio_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct device_node *np = dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct irq_chip *irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) bool supports_sleepmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) nmk_chip = nmk_gpio_populate_chip(np, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (IS_ERR(nmk_chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev_err(&dev->dev, "could not populate nmk chip struct\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return PTR_ERR(nmk_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) supports_sleepmode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) of_property_read_bool(np, "st,supports-sleepmode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Correct platform device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev->id = nmk_chip->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * The virt address in nmk_chip->addr is in the nomadik register space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * so we can simply convert the resource address, without remapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) nmk_chip->sleepmode = supports_sleepmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_lock_init(&nmk_chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) chip = &nmk_chip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) chip->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) chip->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) chip->get_direction = nmk_gpio_get_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) chip->direction_input = nmk_gpio_make_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) chip->get = nmk_gpio_get_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) chip->direction_output = nmk_gpio_make_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) chip->set = nmk_gpio_set_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) chip->dbg_show = nmk_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) chip->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) irqchip = &nmk_chip->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) irqchip->irq_ack = nmk_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) irqchip->irq_mask = nmk_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) irqchip->irq_unmask = nmk_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) irqchip->irq_set_type = nmk_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) irqchip->irq_startup = nmk_gpio_irq_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) chip->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) chip->base + chip->ngpio - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) girq->chip = irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) girq->parent_handler = nmk_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) girq->parents = devm_kcalloc(&dev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = gpiochip_add_data(chip, nmk_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) platform_set_drvdata(dev, nmk_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dev_info(&dev->dev, "chip registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return npct->soc->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return npct->soc->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) *pins = npct->soc->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) *num_pins = npct->soc->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct nmk_gpio_chip *nmk_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) for(i = 0; i < NMK_MAX_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) nmk_gpio = nmk_gpio_chips[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!nmk_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (pin >= nmk_gpio->chip.base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return nmk_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static struct gpio_chip *find_gc_from_pin(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (nmk_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return &nmk_gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct gpio_chip *chip = find_gc_from_pin(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) seq_printf(s, "invalid pin offset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned *num_maps, const char *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) const char *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) (*map)[*num_maps].data.mux.group = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) (*map)[*num_maps].data.mux.function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int nmk_dt_add_map_configs(struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) unsigned *num_maps, const char *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) unsigned long *dup_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (!dup_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) (*map)[*num_maps].data.configs.group_or_pin = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) (*map)[*num_maps].data.configs.configs = dup_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) (*map)[*num_maps].data.configs.num_configs = num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .size = ARRAY_SIZE(y), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const unsigned long nmk_pin_input_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PIN_INPUT_NOPULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PIN_INPUT_PULLUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PIN_INPUT_PULLDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const unsigned long nmk_pin_output_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PIN_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PIN_OUTPUT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PIN_DIR_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const unsigned long nmk_pin_sleep_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PIN_SLEEPMODE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PIN_SLEEPMODE_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static const unsigned long nmk_pin_sleep_input_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PIN_SLPM_INPUT_NOPULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PIN_SLPM_INPUT_PULLUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PIN_SLPM_INPUT_PULLDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PIN_SLPM_DIR_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static const unsigned long nmk_pin_sleep_output_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PIN_SLPM_OUTPUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PIN_SLPM_OUTPUT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PIN_SLPM_DIR_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PIN_SLPM_WAKEUP_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PIN_SLPM_WAKEUP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const unsigned long nmk_pin_gpio_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PIN_GPIOMODE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PIN_GPIOMODE_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const unsigned long nmk_pin_sleep_pdis_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PIN_SLPM_PDIS_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PIN_SLPM_PDIS_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct nmk_cfg_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) const char *property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) const unsigned long *choice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static const struct nmk_cfg_param nmk_cfg_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int nmk_dt_pin_config(int index, int val, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (nmk_cfg_params[index].choice == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) *config = nmk_cfg_params[index].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* test if out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (val < nmk_cfg_params[index].size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) *config = nmk_cfg_params[index].config |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) nmk_cfg_params[index].choice[val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int i, pin_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) for (i = 0; i < npct->soc->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (npct->soc->pins[i].number == pin_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return npct->soc->pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static bool nmk_pinctrl_dt_get_config(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) unsigned long *configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) bool has_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) unsigned long cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int i, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ret = of_property_read_u32(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) nmk_cfg_params[i].property, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (nmk_dt_pin_config(i, val, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) *configs |= cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) has_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return has_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) const char *function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) unsigned long configs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) bool has_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct device_node *np_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = of_property_read_string(np, "function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) const char *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret = of_property_count_strings(np, "groups");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ret = pinctrl_utils_reserve_map(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) num_maps, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) of_property_for_each_string(np, "groups", prop, group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) group, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) has_config = nmk_pinctrl_dt_get_config(np, &configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) np_config = of_parse_phandle(np, "ste,config", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (np_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (has_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) const char *gpio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) const char *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = of_property_count_strings(np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) ret = pinctrl_utils_reserve_map(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) num_maps, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) of_property_for_each_string(np, "pins", prop, pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gpio_name = nmk_find_pin_name(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ret = nmk_dt_add_map_configs(map, reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) gpio_name, &configs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const struct pinctrl_ops nmk_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .get_groups_count = nmk_get_groups_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .get_group_name = nmk_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .get_group_pins = nmk_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .pin_dbg_show = nmk_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return npct->soc->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return npct->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) *groups = npct->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) *num_groups = npct->soc->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) const struct nmk_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static unsigned int slpm[NUM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) bool glitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) g = &npct->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (g->altsetting < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * we may pass through an undesired state. In this case we take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * some extra care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * - Save SLPM registers (since we have a shadow register in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * nmk_chip we're using that as backup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * - Set SLPM=0 for the IOs you want to switch and others to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * - Configure the GPIO registers for the IOs that are being switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * - Set IOFORCE=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * - Modify the AFLSA/B registers for the IOs that are being switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * - Set IOFORCE=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * - Restore SLPM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * - Any spurious wake up event during switch sequence to be ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * and cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * We REALLY need to save ALL slpm registers, because the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * IOFORCE will switch *all* ports to their sleepmode setting to as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * to avoid glitches. (Not just one port!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (glitch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /* Initially don't put any pins to sleep when switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) memset(slpm, 0xff, sizeof(slpm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * Then mask the pins that need to be sleeping now when we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * switching to the ALT C function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) for (i = 0; i < g->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) nmk_gpio_glitch_slpm_init(slpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) for (i = 0; i < g->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (!nmk_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_err(npct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) "invalid pin offset %d in group %s at index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) g->pins[i], g->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) goto out_glitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) bit = g->pins[i] % NMK_GPIO_PER_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * If the pin is switching to altfunc, and there was an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * interrupt installed on it which has been lazy disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * actually mask the interrupt to prevent spurious interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * that would occur while the pin is under control of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * peripheral. Only SKE does this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) nmk_gpio_disable_lazy_irq(nmk_chip, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) __nmk_gpio_set_mode_safe(nmk_chip, bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) (g->altsetting & NMK_GPIO_ALT_C), glitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * Call PRCM GPIOCR config function in case ALTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * has been selected:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * - If selection is pure ALTC and previous selection was ALTCx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * then some bits in PRCM GPIOCR registers must be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) nmk_prcm_altcx_set_mode(npct, g->pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* When all pins are successfully reconfigured we get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) out_glitch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (glitch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) nmk_gpio_glitch_slpm_restore(slpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dev_err(npct->dev, "invalid range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (!range->gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) dev_err(npct->dev, "missing GPIO chip in range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) chip = range->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) nmk_chip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) bit = offset % NMK_GPIO_PER_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* There is no glitch when converting any pin to GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* Set the pin to some default state, GPIO is usually default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static const struct pinmux_ops nmk_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .get_functions_count = nmk_pmx_get_funcs_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .get_function_name = nmk_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .get_function_groups = nmk_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .set_mux = nmk_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .gpio_request_enable = nmk_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .gpio_disable_free = nmk_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const char *pullnames[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) [NMK_GPIO_PULL_NONE] = "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) [NMK_GPIO_PULL_UP] = "up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) [NMK_GPIO_PULL_DOWN] = "down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) [3] /* illegal */ = "??"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static const char *slpmnames[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) pin_cfg_t cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) int pull, slpm, output, val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) bool lowemi, gpiomode, sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) nmk_chip = find_nmk_gpio_from_pin(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (!nmk_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev_err(npct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) "invalid pin offset %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * The pin config contains pin number and altfunction fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * here we just ignore that part. It's being handled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * framework and pinmux callback respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) cfg = (pin_cfg_t) configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) pull = PIN_PULL(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) slpm = PIN_SLPM(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) output = PIN_DIR(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) val = PIN_VAL(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) lowemi = PIN_LOWEMI(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) gpiomode = PIN_GPIOMODE(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) sleep = PIN_SLEEPMODE(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (sleep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) int slpm_pull = PIN_SLPM_PULL(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) int slpm_output = PIN_SLPM_DIR(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) int slpm_val = PIN_SLPM_VAL(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* All pins go into GPIO mode at sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) gpiomode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * The SLPM_* values are normal values + 1 to allow zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * to mean "same as normal".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (slpm_pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) pull = slpm_pull - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (slpm_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) output = slpm_output - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (slpm_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) val = slpm_val - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_dbg(nmk_chip->chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) "pin %d: sleep pull %s, dir %s, val %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) slpm_pull ? pullnames[pull] : "same",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) slpm_output ? (output ? "output" : "input")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) : "same",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) slpm_val ? (val ? "high" : "low") : "same");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) dev_dbg(nmk_chip->chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) pin, cfg, pullnames[pull], slpmnames[slpm],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) output ? "output " : "input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) output ? (val ? "high" : "low") : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) lowemi ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) clk_enable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) bit = pin % NMK_GPIO_PER_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (gpiomode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* No glitch when going to GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) __nmk_gpio_make_output(nmk_chip, bit, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) __nmk_gpio_make_input(nmk_chip, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) __nmk_gpio_set_pull(nmk_chip, bit, pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* TODO: isn't this only applicable on output pins? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) clk_disable(nmk_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static const struct pinconf_ops nmk_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .pin_config_get = nmk_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .pin_config_set = nmk_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static struct pinctrl_desc nmk_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .name = "pinctrl-nomadik",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .pctlops = &nmk_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .pmxops = &nmk_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .confops = &nmk_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static const struct of_device_id nmk_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .compatible = "stericsson,stn8815-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .data = (void *)PINCTRL_NMK_STN8815,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .compatible = "stericsson,db8500-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .data = (void *)PINCTRL_NMK_DB8500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .compatible = "stericsson,db8540-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .data = (void *)PINCTRL_NMK_DB8540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static int nmk_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct nmk_pinctrl *npct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) npct = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (!npct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return pinctrl_force_sleep(npct->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static int nmk_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct nmk_pinctrl *npct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) npct = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (!npct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) return pinctrl_force_default(npct->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static int nmk_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct device_node *prcm_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct nmk_pinctrl *npct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) unsigned int version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (!npct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) match = of_match_device(nmk_pinctrl_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) version = (unsigned int) match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* Poke in other ASIC variants here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (version == PINCTRL_NMK_STN8815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) nmk_pinctrl_stn8815_init(&npct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (version == PINCTRL_NMK_DB8500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) nmk_pinctrl_db8500_init(&npct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (version == PINCTRL_NMK_DB8540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) nmk_pinctrl_db8540_init(&npct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * Since we depend on the GPIO chips to provide clock and register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * for the pin control operations, make sure that we have these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * populated before we continue. Follow the phandles to instantiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * them. The GPIO portion of the actual hardware may be probed before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * or after this point: it shouldn't matter as the APIs are orthogonal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) for (i = 0; i < NMK_MAX_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) struct device_node *gpio_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct nmk_gpio_chip *nmk_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (gpio_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) "populate NMK GPIO %d \"%pOFn\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) i, gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (IS_ERR(nmk_chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) "could not populate nmk chip struct "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) "- continue anyway\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) of_node_put(gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) prcm_np = of_parse_phandle(np, "prcm", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (prcm_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) npct->prcm_base = of_iomap(prcm_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) of_node_put(prcm_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (!npct->prcm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (version == PINCTRL_NMK_STN8815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) "No PRCM base, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) "assuming no ALT-Cx control is available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dev_err(&pdev->dev, "missing PRCM base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) nmk_pinctrl_desc.pins = npct->soc->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) nmk_pinctrl_desc.npins = npct->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) npct->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (IS_ERR(npct->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return PTR_ERR(npct->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) platform_set_drvdata(pdev, npct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const struct of_device_id nmk_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) { .compatible = "st,nomadik-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static struct platform_driver nmk_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .of_match_table = nmk_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .probe = nmk_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) nmk_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) nmk_pinctrl_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct platform_driver nmk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .name = "pinctrl-nomadik",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .of_match_table = nmk_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .pm = &nmk_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .probe = nmk_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static int __init nmk_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return platform_driver_register(&nmk_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) subsys_initcall(nmk_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static int __init nmk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return platform_driver_register(&nmk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) core_initcall(nmk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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