^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include "pinctrl-nomadik.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* All the pins that can be used for GPIO and some other functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DB8500_PIN_AJ5 _GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DB8500_PIN_AJ3 _GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DB8500_PIN_AH4 _GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DB8500_PIN_AH3 _GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DB8500_PIN_AH6 _GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DB8500_PIN_AG6 _GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DB8500_PIN_AF6 _GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DB8500_PIN_AG5 _GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DB8500_PIN_AD5 _GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DB8500_PIN_AE4 _GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DB8500_PIN_AF5 _GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DB8500_PIN_AG4 _GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DB8500_PIN_AC4 _GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DB8500_PIN_AF3 _GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DB8500_PIN_AE3 _GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DB8500_PIN_AC3 _GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DB8500_PIN_AD3 _GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DB8500_PIN_AD4 _GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DB8500_PIN_AC2 _GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DB8500_PIN_AC1 _GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DB8500_PIN_AB4 _GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DB8500_PIN_AB3 _GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DB8500_PIN_AA3 _GPIO(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DB8500_PIN_AA4 _GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DB8500_PIN_AB2 _GPIO(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DB8500_PIN_Y4 _GPIO(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DB8500_PIN_Y2 _GPIO(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DB8500_PIN_AA2 _GPIO(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DB8500_PIN_AA1 _GPIO(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DB8500_PIN_W2 _GPIO(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DB8500_PIN_W3 _GPIO(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DB8500_PIN_V3 _GPIO(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DB8500_PIN_V2 _GPIO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DB8500_PIN_AF2 _GPIO(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DB8500_PIN_AE1 _GPIO(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DB8500_PIN_AE2 _GPIO(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DB8500_PIN_AG2 _GPIO(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DB8500_PIN_F3 _GPIO(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DB8500_PIN_F1 _GPIO(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DB8500_PIN_G3 _GPIO(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DB8500_PIN_G2 _GPIO(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DB8500_PIN_E1 _GPIO(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DB8500_PIN_E2 _GPIO(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DB8500_PIN_G5 _GPIO(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DB8500_PIN_G4 _GPIO(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DB8500_PIN_H4 _GPIO(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DB8500_PIN_H3 _GPIO(73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DB8500_PIN_J3 _GPIO(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DB8500_PIN_H2 _GPIO(75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DB8500_PIN_J2 _GPIO(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DB8500_PIN_H1 _GPIO(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DB8500_PIN_F4 _GPIO(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DB8500_PIN_E3 _GPIO(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DB8500_PIN_E4 _GPIO(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DB8500_PIN_D2 _GPIO(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DB8500_PIN_C1 _GPIO(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DB8500_PIN_D3 _GPIO(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DB8500_PIN_C2 _GPIO(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DB8500_PIN_D5 _GPIO(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DB8500_PIN_C6 _GPIO(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DB8500_PIN_B3 _GPIO(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DB8500_PIN_C4 _GPIO(88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DB8500_PIN_E6 _GPIO(89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DB8500_PIN_A3 _GPIO(90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DB8500_PIN_B6 _GPIO(91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DB8500_PIN_D6 _GPIO(92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DB8500_PIN_B7 _GPIO(93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DB8500_PIN_D7 _GPIO(94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DB8500_PIN_E8 _GPIO(95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DB8500_PIN_D8 _GPIO(96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DB8500_PIN_D9 _GPIO(97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DB8500_PIN_A5 _GPIO(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DB8500_PIN_B4 _GPIO(129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DB8500_PIN_C8 _GPIO(130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DB8500_PIN_A12 _GPIO(131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DB8500_PIN_C10 _GPIO(132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DB8500_PIN_B10 _GPIO(133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DB8500_PIN_B9 _GPIO(134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DB8500_PIN_A9 _GPIO(135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DB8500_PIN_C7 _GPIO(136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DB8500_PIN_A7 _GPIO(137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DB8500_PIN_C5 _GPIO(138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DB8500_PIN_C9 _GPIO(139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DB8500_PIN_B11 _GPIO(140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DB8500_PIN_C12 _GPIO(141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DB8500_PIN_C11 _GPIO(142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DB8500_PIN_D12 _GPIO(143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DB8500_PIN_B13 _GPIO(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DB8500_PIN_C13 _GPIO(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DB8500_PIN_D13 _GPIO(146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DB8500_PIN_C15 _GPIO(147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DB8500_PIN_B16 _GPIO(148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DB8500_PIN_B14 _GPIO(149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DB8500_PIN_C14 _GPIO(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DB8500_PIN_D17 _GPIO(151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DB8500_PIN_D16 _GPIO(152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DB8500_PIN_B17 _GPIO(153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DB8500_PIN_C16 _GPIO(154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DB8500_PIN_C19 _GPIO(155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DB8500_PIN_C17 _GPIO(156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DB8500_PIN_A18 _GPIO(157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DB8500_PIN_C18 _GPIO(158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DB8500_PIN_B19 _GPIO(159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DB8500_PIN_B20 _GPIO(160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DB8500_PIN_D21 _GPIO(161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DB8500_PIN_D20 _GPIO(162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DB8500_PIN_C20 _GPIO(163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DB8500_PIN_B21 _GPIO(164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DB8500_PIN_C21 _GPIO(165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DB8500_PIN_A22 _GPIO(166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DB8500_PIN_B24 _GPIO(167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DB8500_PIN_C22 _GPIO(168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DB8500_PIN_D22 _GPIO(169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DB8500_PIN_C23 _GPIO(170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DB8500_PIN_D23 _GPIO(171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DB8500_PIN_AJ27 _GPIO(192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DB8500_PIN_AH27 _GPIO(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DB8500_PIN_AF27 _GPIO(194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DB8500_PIN_AG28 _GPIO(195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DB8500_PIN_AG26 _GPIO(196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DB8500_PIN_AH24 _GPIO(197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DB8500_PIN_AG25 _GPIO(198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DB8500_PIN_AH23 _GPIO(199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DB8500_PIN_AH26 _GPIO(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DB8500_PIN_AF24 _GPIO(201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DB8500_PIN_AF25 _GPIO(202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DB8500_PIN_AE23 _GPIO(203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DB8500_PIN_AF23 _GPIO(204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DB8500_PIN_AG23 _GPIO(205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DB8500_PIN_AG24 _GPIO(206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DB8500_PIN_AJ23 _GPIO(207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DB8500_PIN_AH16 _GPIO(208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DB8500_PIN_AG15 _GPIO(209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DB8500_PIN_AJ15 _GPIO(210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DB8500_PIN_AG14 _GPIO(211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DB8500_PIN_AF13 _GPIO(212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DB8500_PIN_AG13 _GPIO(213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DB8500_PIN_AH15 _GPIO(214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DB8500_PIN_AH13 _GPIO(215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DB8500_PIN_AG12 _GPIO(216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DB8500_PIN_AH12 _GPIO(217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DB8500_PIN_AH11 _GPIO(218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DB8500_PIN_AG10 _GPIO(219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DB8500_PIN_AH10 _GPIO(220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DB8500_PIN_AJ11 _GPIO(221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DB8500_PIN_AJ9 _GPIO(222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DB8500_PIN_AH9 _GPIO(223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DB8500_PIN_AG9 _GPIO(224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DB8500_PIN_AG8 _GPIO(225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DB8500_PIN_AF8 _GPIO(226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DB8500_PIN_AH7 _GPIO(227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DB8500_PIN_AJ6 _GPIO(228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DB8500_PIN_AG7 _GPIO(229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DB8500_PIN_AF7 _GPIO(230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DB8500_PIN_AF28 _GPIO(256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DB8500_PIN_AE29 _GPIO(257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DB8500_PIN_AD29 _GPIO(258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DB8500_PIN_AC29 _GPIO(259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DB8500_PIN_AD28 _GPIO(260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DB8500_PIN_AD26 _GPIO(261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DB8500_PIN_AE26 _GPIO(262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DB8500_PIN_AG29 _GPIO(263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DB8500_PIN_AE27 _GPIO(264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DB8500_PIN_AD27 _GPIO(265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DB8500_PIN_AC28 _GPIO(266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DB8500_PIN_AC27 _GPIO(267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * The names of the pins are denoted by GPIO number and ball name, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * though they can be used for other things than GPIO, this is the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * column in the table of the data sheet and often used on schematics and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * such.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Read the pin group names like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * u0_a_1 = first groups of pins for uart0 on alt function a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * i2c2_b_2 = second group of pins for i2c2 on alt function b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * The groups are arranged as sets per altfunction column, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * mux in one group at a time by selecting the same altfunction for them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * all. When functions require pins on different altfunctions, you need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * to combine several groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Altfunction A column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DB8500_PIN_AH4, DB8500_PIN_AH3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Image processor I2C line, this is driven by image processor firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* MSP0 can only be on these pins, but TXD and RXD can be flipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Basic pins of the MMC/SD card 0 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, /* MC0_CMDDIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DB8500_PIN_AC1, /* MC0_DAT0DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DB8500_PIN_AB4, /* MC0_DAT2DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DB8500_PIN_AA3, /* MC0_FBCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DB8500_PIN_AA4, /* MC0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DB8500_PIN_AB2, /* MC0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DB8500_PIN_Y4, /* MC0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DB8500_PIN_Y2, /* MC0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DB8500_PIN_AA2, /* MC0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DB8500_PIN_AA1 /* MC0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* MMC/SD card 0 interface without CMD/DAT0/DAT2 direction control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const unsigned mc0_a_2_pins[] = { DB8500_PIN_AA3, /* MC0_FBCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DB8500_PIN_AA4, /* MC0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DB8500_PIN_AB2, /* MC0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DB8500_PIN_Y4, /* MC0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DB8500_PIN_Y2, /* MC0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DB8500_PIN_AA2, /* MC0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DB8500_PIN_AA1 /* MC0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Often only 4 bits are used, then these are not needed (only used for MMC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, /* MC0_DAT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DB8500_PIN_W3, /* MC0_DAT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DB8500_PIN_V3, /* MC0_DAT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DB8500_PIN_V2 /* MC0_DAT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; /* MC0_DAT31DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* MSP1 can only be on these pins, but TXD and RXD can be flipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* LCD interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DB8500_PIN_G3, DB8500_PIN_G2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const unsigned lcd_d0_d7_a_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* D8 thru D11 often used as TVOUT lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const unsigned lcd_d12_d23_a_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DB8500_PIN_D8, DB8500_PIN_D9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const unsigned kp_a_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* MC2 has 8 data lines and no direction control, so only for (e)MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DB8500_PIN_C5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DB8500_PIN_C12, DB8500_PIN_C11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DB8500_PIN_C13, DB8500_PIN_D13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Image processor GPIO pins are named "ipgpio" and have their own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * numberspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DB8500_PIN_D23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * This MSP cannot switch RX and TX, SCK in a separate group since this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * seems to be optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DB8500_PIN_AG28, DB8500_PIN_AG26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DB8500_PIN_AJ23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DB8500_PIN_AH15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, DB8500_PIN_AH15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DB8500_PIN_AH12, DB8500_PIN_AH11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DB8500_PIN_AJ11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const unsigned hsit_a_2_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DB8500_PIN_AG9, DB8500_PIN_AG8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const unsigned clkout1_a_1_pins[] = { DB8500_PIN_AH7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const unsigned clkout1_a_2_pins[] = { DB8500_PIN_AG7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const unsigned clkout2_a_1_pins[] = { DB8500_PIN_AJ6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const unsigned clkout2_a_2_pins[] = { DB8500_PIN_AF7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DB8500_PIN_AC28, DB8500_PIN_AC27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Altfunction B column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Just RX and TX for UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DB8500_PIN_V3, DB8500_PIN_V2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DB8500_PIN_C9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* This chip select pin can be "ps0" in alt C so have it separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* This chip select pin can be "ps1" in alt C so have it separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const unsigned smcs1_b_1_pins[] = { DB8500_PIN_B14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) DB8500_PIN_C23, DB8500_PIN_D23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DB8500_PIN_AG13, DB8500_PIN_AH15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) DB8500_PIN_AG8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Altfunction C column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Optional 4-bit Memory Stick interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) DB8500_PIN_AE2, DB8500_PIN_AG2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DB8500_PIN_D9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DB8500_PIN_C23, DB8500_PIN_D23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const unsigned smps0_c_1_pins[] = { DB8500_PIN_E8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const unsigned clkout1_c_1_pins[] = { DB8500_PIN_AH13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const unsigned clkout2_c_1_pins[] = { DB8500_PIN_AH12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DB8500_PIN_AG9, DB8500_PIN_AG8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Other C1 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const unsigned u2rx_oc1_1_pins[] = { DB8500_PIN_AB2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const unsigned stmape_oc1_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const unsigned remap0_oc1_1_pins[] = { DB8500_PIN_E1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const unsigned remap1_oc1_1_pins[] = { DB8500_PIN_E2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const unsigned ptma9_oc1_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DB8500_PIN_J2, DB8500_PIN_H1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) DB8500_PIN_D6, DB8500_PIN_B7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const unsigned rf_oc1_1_pins[] = { DB8500_PIN_D8, DB8500_PIN_D9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const unsigned hxclk_oc1_1_pins[] = { DB8500_PIN_D16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const unsigned uartmodrx_oc1_1_pins[] = { DB8500_PIN_B17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const unsigned uartmodtx_oc1_1_pins[] = { DB8500_PIN_C16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const unsigned stmmod_oc1_1_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const unsigned hxgpio_oc1_1_pins[] = { DB8500_PIN_D21, DB8500_PIN_D20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) DB8500_PIN_C20, DB8500_PIN_B21, DB8500_PIN_C21, DB8500_PIN_A22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const unsigned rf_oc1_2_pins[] = { DB8500_PIN_C23, DB8500_PIN_D23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DB8500_PIN_AH12, DB8500_PIN_AH11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const unsigned spi2_oc1_2_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DB8500_PIN_AH11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Other C2 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const unsigned sbag_oc2_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_AB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const unsigned etmr4_oc2_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DB8500_PIN_J2, DB8500_PIN_H1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const unsigned ptma9_oc2_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Other C3 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const unsigned stmmod_oc3_1_pins[] = { DB8500_PIN_AB2, DB8500_PIN_W2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) DB8500_PIN_W3, DB8500_PIN_V3, DB8500_PIN_V2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const unsigned stmmod_oc3_2_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const unsigned uartmodrx_oc3_1_pins[] = { DB8500_PIN_H2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const unsigned uartmodtx_oc3_1_pins[] = { DB8500_PIN_J2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const unsigned etmr4_oc3_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Other C4 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const unsigned sbag_oc4_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const unsigned hwobs_oc4_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const struct nmk_pingroup nmk_db8500_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Altfunction A column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) DB8500_PIN_GROUP(mc0_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) DB8500_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DB8500_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) DB8500_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DB8500_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) DB8500_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) DB8500_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Altfunction B column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Altfunction C column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DB8500_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DB8500_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DB8500_PIN_GROUP(clkout1_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DB8500_PIN_GROUP(clkout2_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Other alt C1 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DB8500_PIN_GROUP(u2rx_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DB8500_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DB8500_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DB8500_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DB8500_PIN_GROUP(ptma9_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DB8500_PIN_GROUP(rf_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DB8500_PIN_GROUP(hxclk_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DB8500_PIN_GROUP(uartmodrx_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DB8500_PIN_GROUP(uartmodtx_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DB8500_PIN_GROUP(stmmod_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) DB8500_PIN_GROUP(hxgpio_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DB8500_PIN_GROUP(rf_oc1_2, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Other alt C2 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) DB8500_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) DB8500_PIN_GROUP(etmr4_oc2_1, NMK_GPIO_ALT_C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) DB8500_PIN_GROUP(ptma9_oc2_1, NMK_GPIO_ALT_C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Other alt C3 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DB8500_PIN_GROUP(stmmod_oc3_1, NMK_GPIO_ALT_C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DB8500_PIN_GROUP(stmmod_oc3_2, NMK_GPIO_ALT_C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DB8500_PIN_GROUP(uartmodrx_oc3_1, NMK_GPIO_ALT_C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DB8500_PIN_GROUP(uartmodtx_oc3_1, NMK_GPIO_ALT_C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) DB8500_PIN_GROUP(etmr4_oc3_1, NMK_GPIO_ALT_C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Other alt C4 column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DB8500_PIN_GROUP(sbag_oc4_1, NMK_GPIO_ALT_C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) DB8500_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* We use this macro to define the groups applicable to a function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define DB8500_FUNC_GROUPS(a, b...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const char * const a##_groups[] = { b };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * only available on two pins in alternative function C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "u2rxtx_c_2", "u2rxtx_c_3", "u2rx_oc1_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * switched around by selecting the altfunction A or B. The SCK pin is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * only available on the altfunction B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "msp0txrx_b_1", "msp0sck_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_a_2", "mc0_dat47_a_1", "mc0dat31dir_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* The image processor has 8 GPIO pins that can be muxed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DB8500_FUNC_GROUPS(clkout, "clkout1_a_1", "clkout1_a_2", "clkout1_c_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "clkout2_a_1", "clkout2_a_2", "clkout2_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DB8500_FUNC_GROUPS(usb, "usb_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DB8500_FUNC_GROUPS(trig, "trig_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * The modem UART can output its RX and TX pins in some different places,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * so select one of each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "uartmodrx_c_1", "uartmod_tx_c_1", "uartmodrx_oc1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "uartmodtx_oc1_1", "uartmodrx_oc3_1", "uartmodtx_oc3_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1", "stmmod_oc1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "stmmod_oc3_1", "stmmod_oc3_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Select between CS0 on alt B or PS1 on alt C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcs1_b_1", "smcleale_c_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "smps0_c_1", "smps1_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) DB8500_FUNC_GROUPS(ms, "ms_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2", "stmape_oc1_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1", "spi2_oc1_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DB8500_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DB8500_FUNC_GROUPS(ptm, "ptma9_oc1_1", "ptma9_oc2_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DB8500_FUNC_GROUPS(rf, "rf_oc1_1", "rf_oc1_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DB8500_FUNC_GROUPS(hx, "hxclk_oc1_1", "hxgpio_oc1_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DB8500_FUNC_GROUPS(etm, "etmr4_oc2_1", "etmr4_oc3_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DB8500_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct nmk_function nmk_db8500_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) FUNCTION(u0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) FUNCTION(u1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) FUNCTION(u2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) FUNCTION(ipi2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) FUNCTION(msp0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) FUNCTION(mc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) FUNCTION(msp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) FUNCTION(lcdb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) FUNCTION(lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) FUNCTION(kp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) FUNCTION(mc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) FUNCTION(ssp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) FUNCTION(ssp0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) FUNCTION(ipgpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) FUNCTION(msp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) FUNCTION(mc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) FUNCTION(mc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) FUNCTION(hsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) FUNCTION(clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) FUNCTION(usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) FUNCTION(trig),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) FUNCTION(uartmod),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) FUNCTION(stmmod),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) FUNCTION(sm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) FUNCTION(lcda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) FUNCTION(ddrtrig),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) FUNCTION(pwl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) FUNCTION(mc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) FUNCTION(ipjtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) FUNCTION(slim0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) FUNCTION(ms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) FUNCTION(iptrigout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) FUNCTION(stmape),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) FUNCTION(mc5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) FUNCTION(usbsim),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) FUNCTION(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) FUNCTION(remap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) FUNCTION(sbag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) FUNCTION(ptm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) FUNCTION(rf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) FUNCTION(hx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) FUNCTION(etm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) FUNCTION(hwobs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const struct prcm_gpiocr_altcx_pin_desc db8500_altcx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_CLK_a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE or U2_RXD ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_VAL_a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PRCM_GPIOCR_ALTCX(29, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PRCM_GPIOCR_ALTCX(30, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PRCM_GPIOCR_ALTCX(31, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PRCM_GPIOCR_ALTCX(32, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PRCM_GPIOCR_ALTCX(68, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PRCM_GPIOCR_ALTCX(69, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) true, PRCM_IDX_GPIOCR1, 8 /* SBAG_VAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR1, 12, /* KP_O3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR1, 12, /* KP_O2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PRCM_GPIOCR_ALTCX(88, true, PRCM_IDX_GPIOCR1, 12, /* KP_I3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PRCM_GPIOCR_ALTCX(89, true, PRCM_IDX_GPIOCR1, 12, /* KP_I2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PRCM_GPIOCR_ALTCX(90, true, PRCM_IDX_GPIOCR1, 12, /* KP_O1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PRCM_GPIOCR_ALTCX(91, true, PRCM_IDX_GPIOCR1, 12, /* KP_O0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PRCM_GPIOCR_ALTCX(92, true, PRCM_IDX_GPIOCR1, 12, /* KP_I1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PRCM_GPIOCR_ALTCX(93, true, PRCM_IDX_GPIOCR1, 12, /* KP_I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PRCM_GPIOCR_ALTCX(96, true, PRCM_IDX_GPIOCR2, 3, /* RF_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PRCM_GPIOCR_ALTCX(97, true, PRCM_IDX_GPIOCR2, 1, /* RF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PRCM_GPIOCR_ALTCX(151, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 4, /* Hx_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PRCM_GPIOCR_ALTCX(160, false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PRCM_GPIOCR_ALTCX(165, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PRCM_GPIOCR_ALTCX(166, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PRCM_GPIOCR_ALTCX(167, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PRCM_GPIOCR_ALTCX(168, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PRCM_GPIOCR_ALTCX(170, true, PRCM_IDX_GPIOCR2, 2, /* RF_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PRCM_GPIOCR_ALTCX(171, true, PRCM_IDX_GPIOCR2, 0, /* RF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PRCM_GPIOCR_ALTCX(215, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PRCM_GPIOCR_ALTCX(216, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_FRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PRCM_GPIOCR_ALTCX(217, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PRCM_GPIOCR_ALTCX(218, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) false, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) false, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const u16 db8500_prcm_gpiocr_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) [PRCM_IDX_GPIOCR1] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) [PRCM_IDX_GPIOCR2] = 0x574,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .pins = nmk_db8500_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .npins = ARRAY_SIZE(nmk_db8500_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .functions = nmk_db8500_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .groups = nmk_db8500_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .ngroups = ARRAY_SIZE(nmk_db8500_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .altcx_pins = db8500_altcx_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .npins_altcx = ARRAY_SIZE(db8500_altcx_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .prcm_gpiocr_registers = db8500_prcm_gpiocr_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *soc = &nmk_db8500_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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