^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef PINCTRL_PINCTRL_ABx500_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define PINCTRL_PINCTRL_ABx500_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* Package definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define PINCTRL_AB8500 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PINCTRL_AB8505 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* pins alternate function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) enum abx500_pin_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ABX500_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ABX500_ALT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ABX500_ALT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ABX500_ALT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum abx500_gpio_pull_updown {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ABX500_GPIO_PULL_DOWN = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ABX500_GPIO_PULL_NONE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ABX500_GPIO_PULL_UP = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum abx500_gpio_vinsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ABX500_GPIO_VINSEL_VBAT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * struct abx500_function - ABx500 pinctrl mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @name: The name of the function, exported to pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @groups: An array of pin groups that may select this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @ngroups: The number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct abx500_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct abx500_pingroup - describes a ABx500 pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @pins: an array of discrete physical pins used in this group, taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * from the driver-local pin enumeration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @num_pins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @altsetting: the altsetting to apply to all pins in this group to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * configure them to be used by a function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct abx500_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int altsetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pin_number = pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .gpiosel_bit = sel_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .alt_bit1 = alt1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .alt_bit2 = alt2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .alta_val = alta, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .altb_val = altb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .altc_val = altc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UNUSED -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * struct alternate_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @pin_number: The pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @gpiosel_bit: Control bit in GPIOSEL register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @alt_bit1: First AlternateFunction bit used to select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @alt_bit2: Second AlternateFunction bit used to select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * these 3 following fields are necessary due to none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * coherency on how to select the altA, altB and altC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * function between the ABx500 SOC family when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * alternatfunc register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @alta_val: value to write in alternatfunc to select altA function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @altb_val: value to write in alternatfunc to select altB function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @altc_val: value to write in alternatfunc to select altC function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct alternate_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned pin_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) s8 gpiosel_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) s8 alt_bit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) s8 alt_bit2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 alta_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 altb_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 altc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPIO_IRQ_CLUSTER(a, b, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .start = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .end = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .to_irq = c, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @start: The pin number of the first pin interrupt capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @end: The pin number of the last pin interrupt capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @to_irq: The ABx500 GPIO's associated IRQs are clustered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * together throughout the interrupt numbers at irregular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * intervals. To solve this quandary, we will place the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * read-in values into the cluster information table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct abx500_gpio_irq_cluster {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * struct abx500_pinrange - map pin numbers to GPIO offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @offset: offset into the GPIO local numberspace, incidentally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * identical to the offset into the local pin numberspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @npins: number of pins to map from both offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @altfunc: altfunc setting to be used to enable GPIO on a pin in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * this range (may vary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct abx500_pinrange {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int altfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @gpio_ranges: An array of GPIO ranges for this SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @gpio_num_ranges: The number of GPIO ranges for this SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @pins: An array describing all pins the pin controller affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * All pins which are also GPIOs must be listed first within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * array, and be numbered identically to the GPIO controller's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @npins: The number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @functions: The functions supported on this SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @nfunction: The number of entries in @functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @groups: An array describing all pin groups the pin SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @ngroups: The number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @alternate_functions: array describing pins which supports alternate and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * how to set it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * setting strategy of the rising interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * setting strategy of the falling interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @irq_gpio_factor: Factor used to compute specific setting strategy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct abx500_pinctrl_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const struct abx500_pinrange *gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned gpio_num_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const struct abx500_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct abx500_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct alternate_functions *alternate_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct abx500_gpio_irq_cluster *gpio_irq_cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned ngpio_irq_cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int irq_gpio_rising_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int irq_gpio_falling_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int irq_gpio_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_PINCTRL_AB8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_PINCTRL_AB8505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif /* PINCTRL_PINCTRL_ABx500_H */
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