^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Patrice Chotard <patrice.chotard@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Driver allows to use AxB5xx unused pins to be used as GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/abx500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/abx500/ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pinctrl-abx500.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * GPIO registers offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Bank: 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AB8500_GPIO_SEL1_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AB8500_GPIO_SEL2_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AB8500_GPIO_SEL3_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AB8500_GPIO_SEL4_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AB8500_GPIO_SEL5_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AB8500_GPIO_SEL6_REG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AB8500_GPIO_DIR1_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AB8500_GPIO_DIR2_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AB8500_GPIO_DIR3_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AB8500_GPIO_DIR4_REG 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AB8500_GPIO_DIR5_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AB8500_GPIO_DIR6_REG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AB8500_GPIO_OUT1_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AB8500_GPIO_OUT2_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AB8500_GPIO_OUT3_REG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AB8500_GPIO_OUT4_REG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AB8500_GPIO_OUT5_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AB8500_GPIO_OUT6_REG 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AB8500_GPIO_PUD1_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AB8500_GPIO_PUD2_REG 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AB8500_GPIO_PUD3_REG 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AB8500_GPIO_PUD4_REG 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AB8500_GPIO_PUD5_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AB8500_GPIO_PUD6_REG 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AB8500_GPIO_IN1_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AB8500_GPIO_IN2_REG 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AB8500_GPIO_IN3_REG 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AB8500_GPIO_IN4_REG 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AB8500_GPIO_IN5_REG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AB8500_GPIO_IN6_REG 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AB8500_GPIO_ALTFUN_REG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ABX500_GPIO_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ABX500_GPIO_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct abx500_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct abx500_pinctrl_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ab8500 *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct abx500_gpio_irq_cluster *irq_cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq_cluster_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned offset, bool *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg += offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = abx500_get_register_interruptible(pct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) AB8500_MISC, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(pct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "%s read reg =%x, offset=%x failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __func__, reg, offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *bit = !!(val & BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) reg += offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = abx500_mask_and_set_register_interruptible(pct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AB8500_MISC, reg, BIT(pos), val << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __func__, reg, offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * abx500_gpio_get() - Get the particular GPIO value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @chip: Gpio device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @offset: GPIO number to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 gpio_offset = offset - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) gpio_offset, &is_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (is_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) gpio_offset, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gpio_offset, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int abx500_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* set direction as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AB8500_GPIO_DIR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ABX500_GPIO_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* disable pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AB8500_GPIO_PUD1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ABX500_GPIO_PULL_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* set the output as 1 or 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* set the register as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AB8500_GPIO_DIR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ABX500_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* The AB8500 GPIO numbers are off by one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int gpio = offset + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < pct->irq_cluster_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct abx500_gpio_irq_cluster *cluster =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) &pct->irq_cluster[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (gpio >= cluster->start && gpio <= cluster->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * The ABx500 GPIO's associated IRQs are clustered together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * throughout the interrupt numbers at irregular intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * To solve this quandry, we have placed the read-in values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * into the cluster information table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) hwirq = gpio - cluster->start + cluster->to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return irq_create_mapping(pct->parent->domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned gpio, int alt_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct alternate_functions af = pct->soc->alternate_functions[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const char *modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [ABX500_DEFAULT] = "default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [ABX500_ALT_A] = "altA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [ABX500_ALT_B] = "altB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [ABX500_ALT_C] = "altC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) modes[alt_setting]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* on ABx5xx, there is no GPIO0, so adjust the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) offset = gpio - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) switch (alt_setting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case ABX500_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * for ABx5xx family, default mode is always selected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * writing 0 to GPIOSELx register, except for pins which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * support at least ALT_B mode, default mode is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * by writing 1 to GPIOSELx register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (af.alt_bit1 != UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case ABX500_ALT_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * for ABx5xx family, alt_a mode is always selected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * writing 1 to GPIOSELx register, except for pins which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * support at least ALT_B mode, alt_a mode is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * by writing 0 to GPIOSELx register and 0 in ALTFUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (af.alt_bit1 != UNUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) af.alt_bit1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) !!(af.alta_val & BIT(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (af.alt_bit2 != UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) af.alt_bit2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) !!(af.alta_val & BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case ABX500_ALT_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) af.alt_bit1, !!(af.altb_val & BIT(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (af.alt_bit2 != UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) af.alt_bit2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) !!(af.altb_val & BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case ABX500_ALT_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) af.alt_bit2, !!(af.altc_val & BIT(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) af.alt_bit2, !!(af.altc_val & BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bool bit_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bool alt_bit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bool alt_bit2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct alternate_functions af = pct->soc->alternate_functions[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* on ABx5xx, there is no GPIO0, so adjust the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned offset = gpio - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * if gpiosel_bit is set to unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * it means no GPIO or special case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (af.gpiosel_bit == UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ABX500_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* read GpioSelx register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) af.gpiosel_bit, &bit_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mode = bit_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(pct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "alt_bitX value not in correct range (-1 to 7)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* if alt_bit2 is used, alt_bit1 must be used too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(pct->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "if alt_bit2 is used, alt_bit1 can't be unused\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* check if pin use AlternateFunction register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * if pin GPIOSEL bit is set and pin supports alternate function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * it means DEFAULT mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ABX500_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * pin use the AlternatFunction register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * read alt_bit1 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) af.alt_bit1, &alt_bit1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (af.alt_bit2 != UNUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* read alt_bit2 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) af.alt_bit2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &alt_bit2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) alt_bit2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mode = (alt_bit2 << 1) + alt_bit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (mode == af.alta_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ABX500_ALT_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else if (mode == af.altb_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ABX500_ALT_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ABX500_ALT_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void abx500_gpio_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned offset, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const char *label = gpiochip_is_requested(chip, offset - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 gpio_offset = offset - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int mode = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) bool is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bool pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) const char *modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [ABX500_DEFAULT] = "default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [ABX500_ALT_A] = "altA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [ABX500_ALT_B] = "altB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [ABX500_ALT_C] = "altC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const char *pull_up_down[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [ABX500_GPIO_PULL_DOWN] = "pull down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [ABX500_GPIO_PULL_NONE] = "pull none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [ABX500_GPIO_PULL_NONE + 1] = "pull none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [ABX500_GPIO_PULL_UP] = "pull up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) gpio_offset, &is_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gpio, label ?: "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) is_out ? "out" : "in ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!is_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) gpio_offset, &pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) seq_printf(s, " %-9s", pull_up_down[pd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mode = abx500_get_mode(pctldev, chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned gpio = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct abx500_pinctrl *pct = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct pinctrl_dev *pctldev = pct->pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) for (i = 0; i < chip->ngpio; i++, gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) seq_putc(s, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned offset, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define abx500_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct gpio_chip abx500gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .label = "abx500-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .direction_input = abx500_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .get = abx500_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .direction_output = abx500_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .set = abx500_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .to_irq = abx500_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .dbg_show = abx500_gpio_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return pct->soc->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return pct->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *groups = pct->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *num_groups = pct->soc->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct gpio_chip *chip = &pct->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct abx500_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) g = &pct->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (g->altsetting < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < g->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) g->pins[i], g->altsetting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) const struct abx500_pinrange *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Different ranges have different ways to enable GPIO function on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * pin, so refer back to our local range type, where we handily define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * what altfunc enables GPIO for a certain pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) p = &pct->soc->gpio_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if ((offset >= p->offset) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (offset < (p->offset + p->npins)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (i == pct->soc->gpio_num_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(pct->dev, "%s failed to locate range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) p->altfunc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = abx500_set_mode(pct->pctldev, &pct->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) offset, p->altfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const struct pinmux_ops abx500_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .get_functions_count = abx500_pmx_get_funcs_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .get_function_name = abx500_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .get_function_groups = abx500_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .set_mux = abx500_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .gpio_request_enable = abx500_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .gpio_disable_free = abx500_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return pct->soc->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return pct->soc->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *pins = pct->soc->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *num_pins = pct->soc->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct seq_file *s, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct gpio_chip *chip = &pct->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) chip->base + offset - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int abx500_dt_add_map_mux(struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned *num_maps, const char *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const char *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (*map)[*num_maps].data.mux.group = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) (*map)[*num_maps].data.mux.function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int abx500_dt_add_map_configs(struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned *num_maps, const char *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned long *dup_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!dup_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) (*map)[*num_maps].data.configs.group_or_pin = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) (*map)[*num_maps].data.configs.configs = dup_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (*map)[*num_maps].data.configs.num_configs = num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) const char *pin_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int i, pin_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) for (i = 0; i < npct->soc->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (npct->soc->pins[i].number == pin_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return npct->soc->pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const char *function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int nconfigs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = of_property_read_string(np, "function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) const char *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = of_property_count_strings(np, "groups");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) num_maps, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) of_property_for_each_string(np, "groups", prop, group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = abx500_dt_add_map_mux(map, reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) num_maps, group, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (nconfigs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) const char *gpio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) const char *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = of_property_count_strings(np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = pinctrl_utils_reserve_map(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) num_maps, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) of_property_for_each_string(np, "pins", prop, pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gpio_name = abx500_find_pin_name(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = abx500_dt_add_map_configs(map, reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) num_maps, gpio_name, configs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = abx500_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const struct pinctrl_ops abx500_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .get_groups_count = abx500_get_groups_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .get_group_name = abx500_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .get_group_pins = abx500_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .pin_dbg_show = abx500_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .dt_node_to_map = abx500_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct gpio_chip *chip = &pct->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) enum pin_config_param argument;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) argument = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pin, configs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) (param == PIN_CONFIG_OUTPUT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (argument ? "high" : "low") :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (argument ? "pull up" : "pull down"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* on ABx500, there is no GPIO0, so adjust the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) offset = pin - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = abx500_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Chip only supports pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) AB8500_GPIO_PUD1_REG, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ABX500_GPIO_PULL_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = abx500_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * if argument = 1 set the pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * else clear the pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Chip only supports pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = abx500_gpio_set_bits(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) AB8500_GPIO_PUD1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) argument ? ABX500_GPIO_PULL_DOWN :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ABX500_GPIO_PULL_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = abx500_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * if argument = 1 set the pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * else clear the pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ret = abx500_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = abx500_gpio_direction_output(chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) argument);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(chip->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "illegal configuration requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct pinconf_ops abx500_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .pin_config_get = abx500_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .pin_config_set = abx500_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static struct pinctrl_desc abx500_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "pinctrl-abx500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .pctlops = &abx500_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .pmxops = &abx500_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .confops = &abx500_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int lowest = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) unsigned int highest = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) unsigned int npins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * Compute number of GPIOs from the last SoC gpio range descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * These ranges may include "holes" but the GPIO number space shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * still be homogeneous, so we need to detect and account for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * such holes so that these are included in the number of GPIO pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) for (i = 0; i < soc->gpio_num_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned gstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned gend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) const struct abx500_pinrange *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) p = &soc->gpio_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) gstart = p->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) gend = p->offset + p->npins - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* First iteration, set start values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) lowest = gstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) highest = gend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (gstart < lowest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) lowest = gstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (gend > highest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) highest = gend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* this gives the absolute number of pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) npins = highest - lowest + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct of_device_id abx500_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int abx500_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct abx500_pinctrl *pct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned int id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_err(&pdev->dev, "gpio dt node missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!pct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pct->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pct->parent = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pct->chip = abx500gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) pct->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pct->chip.base = -1; /* Dynamic allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) match = of_match_device(abx500_gpio_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_err(&pdev->dev, "gpio dt not matching\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) id = (unsigned long)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Poke in other ASIC variants here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case PINCTRL_AB8500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) abx500_pinctrl_ab8500_init(&pct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case PINCTRL_AB8505:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) abx500_pinctrl_ab8505_init(&pct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!pct->soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(&pdev->dev, "Invalid SOC data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pct->irq_cluster = pct->soc->gpio_irq_cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = gpiochip_add_data(&pct->chip, pct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_info(&pdev->dev, "added gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) abx500_pinctrl_desc.pins = pct->soc->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) abx500_pinctrl_desc.npins = pct->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pct->pctldev = devm_pinctrl_register(&pdev->dev, &abx500_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (IS_ERR(pct->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "could not register abx500 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = PTR_ERR(pct->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto out_rem_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev_info(&pdev->dev, "registered pin controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* We will handle a range of GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = gpiochip_add_pin_range(&pct->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) p->offset - 1, p->offset, p->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) goto out_rem_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) platform_set_drvdata(pdev, pct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) out_rem_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) gpiochip_remove(&pct->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * abx500_gpio_remove() - remove Ab8500-gpio driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * @pdev: Platform device registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int abx500_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) gpiochip_remove(&pct->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static struct platform_driver abx500_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "abx500-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .of_match_table = abx500_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .probe = abx500_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .remove = abx500_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static int __init abx500_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return platform_driver_register(&abx500_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) core_initcall(abx500_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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