^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/abx500/ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pinctrl-abx500.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* All the pins that can be used for GPIO and some other functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ABX500_GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AB8500_PIN_T10 ABX500_GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AB8500_PIN_T9 ABX500_GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AB8500_PIN_U9 ABX500_GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AB8500_PIN_W2 ABX500_GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AB8500_PIN_Y18 ABX500_GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AB8500_PIN_AA20 ABX500_GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AB8500_PIN_W18 ABX500_GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AB8500_PIN_AA19 ABX500_GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AB8500_PIN_U17 ABX500_GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AB8500_PIN_AA18 ABX500_GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AB8500_PIN_U16 ABX500_GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AB8500_PIN_W17 ABX500_GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AB8500_PIN_F14 ABX500_GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AB8500_PIN_B17 ABX500_GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AB8500_PIN_F15 ABX500_GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AB8500_PIN_P5 ABX500_GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AB8500_PIN_R5 ABX500_GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AB8500_PIN_U5 ABX500_GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AB8500_PIN_T5 ABX500_GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AB8500_PIN_H19 ABX500_GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AB8500_PIN_G20 ABX500_GPIO(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AB8500_PIN_G19 ABX500_GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AB8500_PIN_T14 ABX500_GPIO(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AB8500_PIN_R16 ABX500_GPIO(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AB8500_PIN_M16 ABX500_GPIO(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AB8500_PIN_J6 ABX500_GPIO(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AB8500_PIN_K6 ABX500_GPIO(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AB8500_PIN_G6 ABX500_GPIO(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AB8500_PIN_H6 ABX500_GPIO(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AB8500_PIN_F5 ABX500_GPIO(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AB8500_PIN_G5 ABX500_GPIO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AB8500_PIN_R17 ABX500_GPIO(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AB8500_PIN_W15 ABX500_GPIO(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AB8500_PIN_A17 ABX500_GPIO(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AB8500_PIN_E15 ABX500_GPIO(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AB8500_PIN_C17 ABX500_GPIO(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AB8500_PIN_E16 ABX500_GPIO(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AB8500_PIN_T19 ABX500_GPIO(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AB8500_PIN_U19 ABX500_GPIO(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AB8500_PIN_U2 ABX500_GPIO(42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* indicates the highest GPIO number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AB8500_GPIO_MAX_NUMBER 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The names of the pins are denoted by GPIO number and ball name, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * though they can be used for other things than GPIO, this is the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * column in the table of the data sheet and often used on schematics and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * such.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct pinctrl_pin_desc ab8500_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(AB8500_PIN_T10, "GPIO1_T10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(AB8500_PIN_T9, "GPIO2_T9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(AB8500_PIN_U9, "GPIO3_U9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(AB8500_PIN_W2, "GPIO4_W2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(AB8500_PIN_Y18, "GPIO6_Y18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(AB8500_PIN_AA20, "GPIO7_AA20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(AB8500_PIN_W18, "GPIO8_W18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(AB8500_PIN_AA19, "GPIO9_AA19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(AB8500_PIN_U17, "GPIO10_U17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(AB8500_PIN_AA18, "GPIO11_AA18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(AB8500_PIN_U16, "GPIO12_U16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(AB8500_PIN_W17, "GPIO13_W17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(AB8500_PIN_F14, "GPIO14_F14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(AB8500_PIN_B17, "GPIO15_B17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(AB8500_PIN_F15, "GPIO16_F15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(AB8500_PIN_P5, "GPIO17_P5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(AB8500_PIN_R5, "GPIO18_R5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(AB8500_PIN_U5, "GPIO19_U5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(AB8500_PIN_T5, "GPIO20_T5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(AB8500_PIN_H19, "GPIO21_H19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(AB8500_PIN_G20, "GPIO22_G20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(AB8500_PIN_G19, "GPIO23_G19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(AB8500_PIN_T14, "GPIO24_T14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(AB8500_PIN_R16, "GPIO25_R16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(AB8500_PIN_M16, "GPIO26_M16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(AB8500_PIN_J6, "GPIO27_J6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(AB8500_PIN_K6, "GPIO28_K6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(AB8500_PIN_G6, "GPIO29_G6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(AB8500_PIN_H6, "GPIO30_H6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(AB8500_PIN_F5, "GPIO31_F5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(AB8500_PIN_G5, "GPIO32_G5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(AB8500_PIN_R17, "GPIO34_R17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(AB8500_PIN_W15, "GPIO35_W15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(AB8500_PIN_A17, "GPIO36_A17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(AB8500_PIN_E15, "GPIO37_E15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(AB8500_PIN_C17, "GPIO38_C17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(AB8500_PIN_E16, "GPIO39_E16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(AB8500_PIN_T19, "GPIO40_T19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(AB8500_PIN_U19, "GPIO41_U19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(AB8500_PIN_U2, "GPIO42_U2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Maps local GPIO offsets to local pin numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct abx500_pinrange ab8500_pinranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ABX500_PINRANGE(1, 4, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ABX500_PINRANGE(6, 4, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ABX500_PINRANGE(10, 4, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ABX500_PINRANGE(14, 12, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ABX500_PINRANGE(26, 1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ABX500_PINRANGE(27, 6, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ABX500_PINRANGE(34, 1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ABX500_PINRANGE(35, 1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ABX500_PINRANGE(36, 7, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Read the pin group names like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * The groups are arranged as sets per altfunction column, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * mux in one group at a time by selecting the same altfunction for them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * all. When functions require pins on different altfunctions, you need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * to combine several groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* default column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const unsigned sysclkreq2_d_1_pins[] = { AB8500_PIN_T10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const unsigned sysclkreq3_d_1_pins[] = { AB8500_PIN_T9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const unsigned sysclkreq4_d_1_pins[] = { AB8500_PIN_U9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const unsigned sysclkreq6_d_1_pins[] = { AB8500_PIN_W2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const unsigned ycbcr0123_d_1_pins[] = { AB8500_PIN_Y18, AB8500_PIN_AA20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) AB8500_PIN_W18, AB8500_PIN_AA19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const unsigned gpio10_d_1_pins[] = { AB8500_PIN_U17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const unsigned gpio11_d_1_pins[] = { AB8500_PIN_AA18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const unsigned gpio12_d_1_pins[] = { AB8500_PIN_U16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const unsigned gpio13_d_1_pins[] = { AB8500_PIN_W17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const unsigned pwmout1_d_1_pins[] = { AB8500_PIN_F14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const unsigned pwmout2_d_1_pins[] = { AB8500_PIN_B17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const unsigned pwmout3_d_1_pins[] = { AB8500_PIN_F15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* audio data interface 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const unsigned adi1_d_1_pins[] = { AB8500_PIN_P5, AB8500_PIN_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) AB8500_PIN_U5, AB8500_PIN_T5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* USBUICC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const unsigned usbuicc_d_1_pins[] = { AB8500_PIN_H19, AB8500_PIN_G20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) AB8500_PIN_G19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned sysclkreq7_d_1_pins[] = { AB8500_PIN_T14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const unsigned sysclkreq8_d_1_pins[] = { AB8500_PIN_R16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned gpio26_d_1_pins[] = { AB8500_PIN_M16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Digital microphone 1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const unsigned dmic12_d_1_pins[] = { AB8500_PIN_J6, AB8500_PIN_K6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Digital microphone 3 and 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const unsigned dmic34_d_1_pins[] = { AB8500_PIN_G6, AB8500_PIN_H6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Digital microphone 5 and 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const unsigned dmic56_d_1_pins[] = { AB8500_PIN_F5, AB8500_PIN_G5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned extcpena_d_1_pins[] = { AB8500_PIN_R17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const unsigned gpio35_d_1_pins[] = { AB8500_PIN_W15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* APE SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const unsigned apespi_d_1_pins[] = { AB8500_PIN_A17, AB8500_PIN_E15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) AB8500_PIN_C17, AB8500_PIN_E16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* modem SDA/SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned modsclsda_d_1_pins[] = { AB8500_PIN_T19, AB8500_PIN_U19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned sysclkreq5_d_1_pins[] = { AB8500_PIN_U2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Altfunction A column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned gpio1_a_1_pins[] = { AB8500_PIN_T10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned gpio2_a_1_pins[] = { AB8500_PIN_T9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const unsigned gpio3_a_1_pins[] = { AB8500_PIN_U9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned gpio4_a_1_pins[] = { AB8500_PIN_W2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned gpio6_a_1_pins[] = { AB8500_PIN_Y18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned gpio7_a_1_pins[] = { AB8500_PIN_AA20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned gpio8_a_1_pins[] = { AB8500_PIN_W18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned gpio9_a_1_pins[] = { AB8500_PIN_AA19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* YCbCr4 YCbCr5 YCbCr6 YCbCr7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned ycbcr4567_a_1_pins[] = { AB8500_PIN_U17, AB8500_PIN_AA18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AB8500_PIN_U16, AB8500_PIN_W17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned gpio14_a_1_pins[] = { AB8500_PIN_F14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned gpio15_a_1_pins[] = { AB8500_PIN_B17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned gpio16_a_1_pins[] = { AB8500_PIN_F15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const unsigned gpio17_a_1_pins[] = { AB8500_PIN_P5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const unsigned gpio18_a_1_pins[] = { AB8500_PIN_R5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned gpio19_a_1_pins[] = { AB8500_PIN_U5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const unsigned gpio20_a_1_pins[] = { AB8500_PIN_T5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned gpio21_a_1_pins[] = { AB8500_PIN_H19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const unsigned gpio22_a_1_pins[] = { AB8500_PIN_G20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned gpio23_a_1_pins[] = { AB8500_PIN_G19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const unsigned gpio24_a_1_pins[] = { AB8500_PIN_T14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned gpio25_a_1_pins[] = { AB8500_PIN_R16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const unsigned gpio27_a_1_pins[] = { AB8500_PIN_J6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const unsigned gpio28_a_1_pins[] = { AB8500_PIN_K6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned gpio29_a_1_pins[] = { AB8500_PIN_G6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const unsigned gpio30_a_1_pins[] = { AB8500_PIN_H6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned gpio31_a_1_pins[] = { AB8500_PIN_F5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned gpio32_a_1_pins[] = { AB8500_PIN_G5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned gpio34_a_1_pins[] = { AB8500_PIN_R17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned gpio36_a_1_pins[] = { AB8500_PIN_A17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned gpio37_a_1_pins[] = { AB8500_PIN_E15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned gpio38_a_1_pins[] = { AB8500_PIN_C17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned gpio39_a_1_pins[] = { AB8500_PIN_E16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const unsigned gpio40_a_1_pins[] = { AB8500_PIN_T19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned gpio41_a_1_pins[] = { AB8500_PIN_U19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned gpio42_a_1_pins[] = { AB8500_PIN_U2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Altfunction B colum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned hiqclkena_b_1_pins[] = { AB8500_PIN_U17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const unsigned usbuiccpd_b_1_pins[] = { AB8500_PIN_AA18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned i2ctrig1_b_1_pins[] = { AB8500_PIN_U16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned i2ctrig2_b_1_pins[] = { AB8500_PIN_W17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Altfunction C column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned usbvdat_c_1_pins[] = { AB8500_PIN_W17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct abx500_pingroup ab8500_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* default column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) AB8500_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) AB8500_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AB8500_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) AB8500_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) AB8500_PIN_GROUP(ycbcr0123_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) AB8500_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AB8500_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) AB8500_PIN_GROUP(gpio12_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) AB8500_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) AB8500_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) AB8500_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) AB8500_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) AB8500_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AB8500_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) AB8500_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AB8500_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AB8500_PIN_GROUP(gpio26_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AB8500_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) AB8500_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AB8500_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) AB8500_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) AB8500_PIN_GROUP(gpio35_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) AB8500_PIN_GROUP(apespi_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AB8500_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AB8500_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Altfunction A column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) AB8500_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AB8500_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AB8500_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) AB8500_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) AB8500_PIN_GROUP(gpio6_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AB8500_PIN_GROUP(gpio7_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) AB8500_PIN_GROUP(gpio8_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AB8500_PIN_GROUP(gpio9_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) AB8500_PIN_GROUP(ycbcr4567_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AB8500_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) AB8500_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AB8500_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) AB8500_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AB8500_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) AB8500_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AB8500_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) AB8500_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) AB8500_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) AB8500_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) AB8500_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) AB8500_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) AB8500_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) AB8500_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) AB8500_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) AB8500_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) AB8500_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) AB8500_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) AB8500_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AB8500_PIN_GROUP(gpio36_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) AB8500_PIN_GROUP(gpio37_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) AB8500_PIN_GROUP(gpio38_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) AB8500_PIN_GROUP(gpio39_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) AB8500_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) AB8500_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) AB8500_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Altfunction B column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) AB8500_PIN_GROUP(hiqclkena_b_1, ABX500_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) AB8500_PIN_GROUP(usbuiccpd_b_1, ABX500_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) AB8500_PIN_GROUP(i2ctrig1_b_1, ABX500_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) AB8500_PIN_GROUP(i2ctrig2_b_1, ABX500_ALT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Altfunction C column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) AB8500_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* We use this macro to define the groups applicable to a function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AB8500_FUNC_GROUPS(a, b...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char * const a##_groups[] = { b };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) AB8500_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "sysclkreq7_d_1", "sysclkreq8_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) AB8500_FUNC_GROUPS(ycbcr, "ycbcr0123_d_1", "ycbcr4567_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) AB8500_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "gpio6_a_1", "gpio7_a_1", "gpio8_a_1", "gpio9_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "gpio10_d_1", "gpio11_d_1", "gpio12_d_1", "gpio13_d_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio21_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "gpio22_a_1", "gpio23_a_1", "gpio24_a_1", "gpio25_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "gpio26_d_1", "gpio27_a_1", "gpio28_a_1", "gpio29_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "gpio30_a_1", "gpio31_a_1", "gpio32_a_1", "gpio34_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "gpio35_d_1", "gpio36_a_1", "gpio37_a_1", "gpio38_a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "gpio39_a_1", "gpio40_a_1", "gpio41_a_1", "gpio42_a_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AB8500_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AB8500_FUNC_GROUPS(adi1, "adi1_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) AB8500_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) AB8500_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) AB8500_FUNC_GROUPS(extcpena, "extcpena_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AB8500_FUNC_GROUPS(apespi, "apespi_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) AB8500_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AB8500_FUNC_GROUPS(hiqclkena, "hiqclkena_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) AB8500_FUNC_GROUPS(i2ctrig, "i2ctrig1_b_1", "i2ctrig2_b_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AB8500_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct abx500_function ab8500_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) FUNCTION(sysclkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) FUNCTION(ycbcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FUNCTION(pwmout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FUNCTION(adi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FUNCTION(usbuicc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FUNCTION(dmic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FUNCTION(extcpena),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FUNCTION(apespi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FUNCTION(modsclsda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FUNCTION(hiqclkena),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FUNCTION(i2ctrig),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FUNCTION(usbvdat),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * this table translates what's is in the AB8500 specification regarding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1 ,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * select the mux. ALTA, ALTB and ALTC val indicates values to write in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * ALTERNATFUNC register. We need to specifies these values as SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * designers didn't apply the same logic on how to select mux in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * ABx500 family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * As this pins supports at least ALT_B mux, default mux is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * selected by writing 1 in GPIOSEL bit :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * default | 1 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * alt_A | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * alt_B | 0 | 0 | 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * alt_C | 0 | 1 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * register is used to select the mux. As this pins doesn't support at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * | GPIOSEL bit=7 | alternatfunc bit2= | alternatfunc bit1=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * default | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * alt_A | 1 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* bit 4 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ALTERNATE_FUNCTIONS(6, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ALTERNATE_FUNCTIONS(7, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ALTERNATE_FUNCTIONS(9, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ALTERNATE_FUNCTIONS(12, 3, 2, UNUSED, 0, 1, 0), /* GPIO12, altA and altB controlled by bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * pins 17 to 20 are special case, only bit 0 is used to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * alternate function for these 4 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * bits 1 to 3 are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* pin 26 special case, no alternate function, bit 1 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* pin 35 special case, no alternate function, bit 2 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ALTERNATE_FUNCTIONS(36, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO36, altA controlled by bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ALTERNATE_FUNCTIONS(37, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO37, altA controlled by bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ALTERNATE_FUNCTIONS(38, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO38, altA controlled by bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ALTERNATE_FUNCTIONS(39, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO39, altA controlled by bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Only some GPIOs are interrupt capable, and they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * organized in discontiguous clusters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * GPIO6 to GPIO13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * GPIO24 and GPIO25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * GPIO36 to GPIO41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GPIO_IRQ_CLUSTER(6, 13, AB8500_INT_GPIO6R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct abx500_pinctrl_soc_data ab8500_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .gpio_ranges = ab8500_pinranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .gpio_num_ranges = ARRAY_SIZE(ab8500_pinranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .pins = ab8500_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .npins = ARRAY_SIZE(ab8500_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .functions = ab8500_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .nfunctions = ARRAY_SIZE(ab8500_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .groups = ab8500_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .ngroups = ARRAY_SIZE(ab8500_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .alternate_functions = ab8500_alternate_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .gpio_irq_cluster = ab8500_gpio_irq_cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ngpio_irq_cluster = ARRAY_SIZE(ab8500_gpio_irq_cluster),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .irq_gpio_factor = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *soc = &ab8500_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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