^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Orion pinctrl driver based on mvebu pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The first 16 MPP pins on Orion are easy to handle: they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * configured through 2 consecutive registers, located at the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * address of the MPP device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * However the last 4 MPP pins are handled by a register at offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 0x50 from the base address, so it is not consecutive with the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pinctrl-mvebu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __iomem *mpp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *high_mpp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned pid, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (pid < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned pid, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (pid < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) writel(reg | (config << shift), mpp_base + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(reg | (config << shift), high_mpp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define V(f5181, f5182, f5281) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum orion_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) V_5181 = V(1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) V_5182 = V(0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) V_5281 = V(0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) V_ALL = V(1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct mvebu_mpp_mode orion_mpp_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MPP_MODE(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MPP_MODE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MPP_MODE(2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MPP_MODE(3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MPP_MODE(4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MPP_MODE(5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MPP_MODE(6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MPP_MODE(7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MPP_MODE(8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MPP_MODE(9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MPP_MODE(10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MPP_MODE(11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MPP_MODE(12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MPP_MODE(13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MPP_MODE(14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MPP_MODE(15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MPP_MODE(16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MPP_MODE(17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MPP_MODE(18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MPP_MODE(19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MPP_GPIO_RANGE(0, 0, 0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MPP_GPIO_RANGE(0, 0, 0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MPP_GPIO_RANGE(0, 0, 0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct mvebu_pinctrl_soc_info mv88f5181_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .variant = V_5181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .controls = orion_mpp_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ncontrols = ARRAY_SIZE(orion_mpp_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .modes = orion_mpp_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .nmodes = ARRAY_SIZE(orion_mpp_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .gpioranges = mv88f5181_gpio_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct mvebu_pinctrl_soc_info mv88f5182_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .variant = V_5182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .controls = orion_mpp_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .ncontrols = ARRAY_SIZE(orion_mpp_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .modes = orion_mpp_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nmodes = ARRAY_SIZE(orion_mpp_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .gpioranges = mv88f5182_gpio_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct mvebu_pinctrl_soc_info mv88f5281_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .variant = V_5281,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .controls = orion_mpp_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ncontrols = ARRAY_SIZE(orion_mpp_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .modes = orion_mpp_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .nmodes = ARRAY_SIZE(orion_mpp_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .gpioranges = mv88f5281_gpio_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * There are multiple variants of the Orion SoCs, but in terms of pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * muxing, they are identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct of_device_id orion_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int orion_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) of_match_device(orion_pinctrl_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pdev->dev.platform_data = (void*)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mpp_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (IS_ERR(mpp_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(mpp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) high_mpp_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR(high_mpp_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(high_mpp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return mvebu_pinctrl_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct platform_driver orion_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "orion-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .of_match_table = of_match_ptr(orion_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .probe = orion_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) builtin_platform_driver(orion_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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