Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell MVEBU pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *          Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __PINCTRL_MVEBU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __PINCTRL_MVEBU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * @base: base address of pinctrl hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * @regmap.map: regmap structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * @regmap.offset: regmap offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct mvebu_mpp_ctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 			struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		} regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * struct mvebu_mpp_ctrl - describe a mpp control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @name: name of the control group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @pid: first pin id handled by this control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @npins: number of pins controlled by this control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @mpp_get: (optional) special function to get mpp setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @mpp_set: (optional) special function to set mpp setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @mpp_gpio_req: (optional) special function to request gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @mpp_gpio_dir: (optional) special function to set gpio direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * internal function, inside the SoC. Each muxable unit can be switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * between two or more different settings, e.g. assign mpp pin 13 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * uart1 or sata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * The mpp_get/_set functions are mandatory and are used to get/set a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * specific mode. The optional mpp_gpio_req/_dir functions can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * to allow pin settings with varying gpio pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct mvebu_mpp_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int (*mpp_get)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		       unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int (*mpp_set)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		       unsigned long config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int (*mpp_gpio_req)(struct mvebu_mpp_ctrl_data *data, unsigned pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			    bool input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * @val: ctrl setting value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @subname: (optional) additional ctrl setting name, e.g. rts, cts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @variant: (optional) variant identifier mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * @flags: (private) flags to store gpi/gpo/gpio capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * A ctrl_setting describes a specific internal mux function that a mpp pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * can be switched to. The value (val) will be written in the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * register for common mpp pin configuration registers on MVEBU. SoC specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * mpp_get/_set function may use val to distinguish between different settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * The name will be used to switch to this setting in DT description, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * marvell,function = "uart2". subname is only for debugging purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * parsed during initialization and stored in flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * The variant can be used to combine different revisions of one SoC to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * common pinctrl driver. It is matched (AND) with variant of soc_info to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * determine if a setting is available on the current SoC revision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct mvebu_mpp_ctrl_setting {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	const char *subname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  MVEBU_SETTING_GPO	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  MVEBU_SETTING_GPI	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * struct mvebu_mpp_mode - link ctrl and settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * @pid: first pin id handled by this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * @settings: list of settings available for this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * A mode connects all available settings with the corresponding mpp_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * given by pid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mvebu_mpp_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct mvebu_mpp_ctrl_setting *settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * @variant: variant mask of soc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * @controls: list of available mvebu_mpp_ctrls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * @control_data: optional array, one entry for each control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * @ncontrols: number of available mvebu_mpp_ctrls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * @modes: list of available mvebu_mpp_modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * @nmodes: number of available mvebu_mpp_modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * @gpioranges: list of pinctrl_gpio_ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * @ngpioranges: number of available pinctrl_gpio_ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * This struct describes all pinctrl related information for a specific SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * If variant is unequal 0 it will be matched (AND) with variant of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * setting and allows to distinguish between different revisions of one SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mvebu_pinctrl_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	const struct mvebu_mpp_ctrl *controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct mvebu_mpp_ctrl_data *control_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ncontrols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct mvebu_mpp_mode *modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int nmodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct pinctrl_gpio_range *gpioranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int ngpioranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MPP_FUNC_CTRL(_idl, _idh, _name, _func)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.pid = _idl,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.npins = _idh - _idl + 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.pins = (unsigned[_idh - _idl + 1]) { },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.mpp_get = _func ## _get,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.mpp_set = _func ## _set,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.mpp_gpio_req = NULL,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.mpp_gpio_dir = NULL,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.pid = _idl,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.npins = _idh - _idl + 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.pins = (unsigned[_idh - _idl + 1]) { },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.mpp_get = _func ## _get,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.mpp_set = _func ## _set,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.mpp_gpio_req = _func ## _gpio_req,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.mpp_gpio_dir = _func ## _gpio_dir,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.val = _val,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.subname = _subname,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.variant = _mask,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.flags = 0,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MPP_FUNCTION(_val, _name, _subname)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MPP_MODE(_id, ...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.pid = _id,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.settings = (struct mvebu_mpp_ctrl_setting[]){	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			__VA_ARGS__, { } },			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.name = "mvebu-gpio",				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.id = _id,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.pin_base = _pinbase,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.base = _gpiobase,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.npins = _npins,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MVEBU_MPPS_PER_REG	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MVEBU_MPP_BITS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MVEBU_MPP_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int mvebu_mmio_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			       unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int mvebu_mmio_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			       unsigned long config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int mvebu_regmap_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			      unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			      unsigned long config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int mvebu_pinctrl_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				      struct device *syscon_dev, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif