^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Dove pinctrl driver based on mvebu pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinctrl-mvebu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Internal registers can be configured at any 1 MiB aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INT_REGS_MASK ~(SZ_1M - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPP4_REGS_OFFS 0xd0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMU_REGS_OFFS 0xd802c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GC_REGS_OFFS 0xe802c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* MPP Base registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMU_MPP_GENERAL_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AU0_AC97_SEL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* MPP Control 4 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_GPIO_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UART1_GPIO_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AU1_GPIO_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAM_GPIO_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SD1_GPIO_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SD0_GPIO_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* PMU Signal Select registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PMU_SIGNAL_SELECT_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PMU_SIGNAL_SELECT_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Global Config regmap registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GLOBAL_CONFIG_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TWSI_ENABLE_OPTION1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GLOBAL_CONFIG_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TWSI_ENABLE_OPTION2 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TWSI_ENABLE_OPTION3 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TWSI_OPTION3_GPIO BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSP_CTRL_STATUS_1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSP_ON_AU1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPP_GENERAL_CONFIG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AU1_SPDIFO_GPIO_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NAND_GPIO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CONFIG_PMU BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void __iomem *mpp4_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __iomem *pmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct regmap *gconfmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned pid, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if ((pmu & BIT(pid)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return mvebu_mmio_mpp_ctrl_get(data, pid, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *config = (func >> shift) & MVEBU_MPP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *config |= CONFIG_PMU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned pid, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if ((config & CONFIG_PMU) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return mvebu_mmio_mpp_ctrl_set(data, pid, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) func &= ~(MVEBU_MPP_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) func |= (config & MVEBU_MPP_MASK) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long mpp4 = readl(mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) switch (pid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case 24: /* mpp_camera */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mask = CAM_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case 40: /* mpp_sdio0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mask = SD0_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case 46: /* mpp_sdio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mask = SD1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case 58: /* mpp_spi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mask = SPI_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 62: /* mpp_uart1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mask = UART1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *config = ((mpp4 & mask) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long mpp4 = readl(mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (pid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 24: /* mpp_camera */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mask = CAM_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case 40: /* mpp_sdio0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mask = SD0_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 46: /* mpp_sdio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mask = SD1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case 58: /* mpp_spi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mask = SPI_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case 62: /* mpp_uart1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mask = UART1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mpp4 &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mpp4 |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(mpp4, mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int gmpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *config = ((gmpp & NAND_GPIO_EN) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NAND_GPIO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (config) ? NAND_GPIO_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *config = ((pmu & AU0_AC97_SEL) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pmu &= ~AU0_AC97_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pmu |= AU0_AC97_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int mpp4 = readl(mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int sspc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int gmpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int gcfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mpp4 & AU1_GPIO_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *config |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (sspc1 & SSP_ON_AU1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *config |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (gmpp & AU1_SPDIFO_GPIO_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *config |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (gcfg2 & TWSI_OPTION3_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *config |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* SSP/TWSI only if I2S1 not set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if ((*config & BIT(3)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *config &= ~(BIT(2) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* TWSI only if SPDIFO not set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if ((*config & BIT(1)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *config &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int mpp4 = readl(mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mpp4 &= ~AU1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (config & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mpp4 |= AU1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(mpp4, mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SSP_ON_AU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (config & BIT(2)) ? SSP_ON_AU1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) AU1_SPDIFO_GPIO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TWSI_OPTION3_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* mpp[52:57] gpio pins depend heavily on current config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * gpio_req does not try to mux in gpio capabilities to not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * break other functions. If you require all mpps as gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * enforce gpio setting by pinctrl mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dove_audio1_ctrl_get(data, pid, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case 0x02: /* i2s1 : gpio[56:57] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 0x0e: /* ssp : gpio[56:57] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (pid >= 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 0x08: /* spdifo : gpio[52:55] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 0x0b: /* twsi : gpio[52:55] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (pid <= 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 0x0a: /* all gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* 0x00 : i2s1/spdifo : no gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* 0x0c : ssp/spdifo : no gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* 0x0f : ssp/twsi : no gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* mpp[52:57] has gpio pins capable of in and out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned pid, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (pid < 52 || pid > 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int gcfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int gcfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (gcfg1 & TWSI_ENABLE_OPTION1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else if (gcfg2 & TWSI_ENABLE_OPTION2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *config = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else if (gcfg2 & TWSI_ENABLE_OPTION3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *config = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int gcfg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int gcfg2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch (config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gcfg1 = TWSI_ENABLE_OPTION1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) gcfg2 = TWSI_ENABLE_OPTION2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) gcfg2 = TWSI_ENABLE_OPTION3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) TWSI_ENABLE_OPTION1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) gcfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) gcfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct mvebu_mpp_ctrl dove_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct mvebu_mpp_mode dove_mpp_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MPP_MODE(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MPP_FUNCTION(0x02, "uart2", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MPP_FUNCTION(0x03, "sdio0", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MPP_FUNCTION(0x0f, "lcd0", "pwm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MPP_MODE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MPP_FUNCTION(0x02, "uart2", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MPP_FUNCTION(0x03, "sdio0", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MPP_FUNCTION(0x0f, "lcd1", "pwm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MPP_MODE(2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MPP_FUNCTION(0x01, "sata", "prsnt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MPP_FUNCTION(0x02, "uart2", "txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MPP_FUNCTION(0x03, "sdio0", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MPP_FUNCTION(0x04, "uart1", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MPP_MODE(3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MPP_FUNCTION(0x01, "sata", "act"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MPP_FUNCTION(0x02, "uart2", "rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MPP_FUNCTION(0x04, "uart1", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MPP_MODE(4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MPP_FUNCTION(0x02, "uart3", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MPP_FUNCTION(0x03, "sdio1", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MPP_FUNCTION(0x04, "spi1", "miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MPP_MODE(5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MPP_FUNCTION(0x02, "uart3", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MPP_FUNCTION(0x03, "sdio1", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MPP_FUNCTION(0x04, "spi1", "cs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MPP_MODE(6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MPP_FUNCTION(0x02, "uart3", "txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MPP_FUNCTION(0x03, "sdio1", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MPP_FUNCTION(0x04, "spi1", "mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MPP_MODE(7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MPP_FUNCTION(0x02, "uart3", "rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MPP_FUNCTION(0x04, "spi1", "sck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MPP_MODE(8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MPP_FUNCTION(0x01, "watchdog", "rstout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MPP_MODE(9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MPP_FUNCTION(0x05, "pex1", "clkreq"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MPP_MODE(10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MPP_FUNCTION(0x05, "ssp", "sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MPP_MODE(11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MPP_FUNCTION(0x01, "sata", "prsnt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MPP_FUNCTION(0x02, "sata-1", "act"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MPP_FUNCTION(0x05, "pex0", "clkreq"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MPP_MODE(12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MPP_FUNCTION(0x01, "sata", "act"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MPP_FUNCTION(0x02, "uart2", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MPP_FUNCTION(0x03, "audio0", "extclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MPP_FUNCTION(0x04, "sdio1", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MPP_MODE(13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MPP_FUNCTION(0x02, "uart2", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MPP_FUNCTION(0x03, "audio1", "extclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MPP_FUNCTION(0x04, "sdio1", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MPP_FUNCTION(0x05, "ssp", "extclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MPP_MODE(14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MPP_FUNCTION(0x02, "uart2", "txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MPP_FUNCTION(0x04, "sdio1", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MPP_FUNCTION(0x05, "ssp", "rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MPP_MODE(15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MPP_FUNCTION(0x02, "uart2", "rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MPP_FUNCTION(0x05, "ssp", "sfrm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MPP_MODE(16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MPP_FUNCTION(0x02, "uart3", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MPP_FUNCTION(0x03, "sdio0", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MPP_FUNCTION(0x05, "ac97", "sdi1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MPP_MODE(17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MPP_FUNCTION(0x02, "uart3", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MPP_FUNCTION(0x03, "sdio0", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MPP_FUNCTION(0x04, "twsi", "sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MPP_FUNCTION(0x05, "ac97", "sdi2")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MPP_MODE(18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MPP_FUNCTION(0x02, "uart3", "txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MPP_FUNCTION(0x03, "sdio0", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MPP_FUNCTION(0x04, "lcd0", "pwm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MPP_FUNCTION(0x05, "ac97", "sdi3")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MPP_MODE(19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) MPP_FUNCTION(0x02, "uart3", "rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MPP_FUNCTION(0x04, "twsi", "sck")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MPP_MODE(20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MPP_FUNCTION(0x01, "ac97", "sysclko"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MPP_FUNCTION(0x02, "lcd-spi", "miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MPP_FUNCTION(0x03, "sdio1", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MPP_FUNCTION(0x05, "sdio0", "cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MPP_FUNCTION(0x06, "spi1", "miso")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MPP_MODE(21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MPP_FUNCTION(0x01, "uart1", "rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MPP_FUNCTION(0x03, "sdio1", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MPP_FUNCTION(0x04, "ssp", "sfrm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MPP_FUNCTION(0x05, "sdio0", "wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MPP_FUNCTION(0x06, "spi1", "cs")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MPP_MODE(22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MPP_FUNCTION(0x01, "uart1", "cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MPP_FUNCTION(0x03, "sdio1", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MPP_FUNCTION(0x04, "ssp", "txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MPP_FUNCTION(0x05, "sdio0", "buspwr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MPP_FUNCTION(0x06, "spi1", "mosi")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MPP_MODE(23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MPP_FUNCTION(0x00, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MPP_FUNCTION(0x02, "lcd-spi", "sck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MPP_FUNCTION(0x04, "ssp", "sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MPP_FUNCTION(0x06, "spi1", "sck")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MPP_MODE(24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MPP_FUNCTION(0x00, "camera", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MPP_FUNCTION(0x01, "gpio", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MPP_MODE(40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) MPP_FUNCTION(0x00, "sdio0", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MPP_FUNCTION(0x01, "gpio", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MPP_MODE(46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MPP_FUNCTION(0x00, "sdio1", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MPP_FUNCTION(0x01, "gpio", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MPP_MODE(52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MPP_FUNCTION(0x02, "i2s1", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MPP_FUNCTION(0x08, "spdifo", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MPP_FUNCTION(0x0a, "gpio", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MPP_FUNCTION(0x0b, "twsi", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MPP_FUNCTION(0x0e, "ssp", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MPP_MODE(58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MPP_FUNCTION(0x00, "spi0", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MPP_FUNCTION(0x01, "gpio", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MPP_MODE(62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MPP_FUNCTION(0x00, "uart1", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MPP_FUNCTION(0x01, "gpio", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MPP_MODE(64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MPP_FUNCTION(0x00, "nand", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MPP_FUNCTION(0x01, "gpo", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MPP_MODE(72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MPP_FUNCTION(0x00, "i2s", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MPP_FUNCTION(0x01, "ac97", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MPP_MODE(73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MPP_FUNCTION(0x00, "twsi-none", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MPP_FUNCTION(0x01, "twsi-opt1", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MPP_FUNCTION(0x02, "twsi-opt2", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MPP_GPIO_RANGE(0, 0, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) MPP_GPIO_RANGE(1, 32, 32, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MPP_GPIO_RANGE(2, 64, 64, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .controls = dove_mpp_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .ncontrols = ARRAY_SIZE(dove_mpp_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .modes = dove_mpp_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .nmodes = ARRAY_SIZE(dove_mpp_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .gpioranges = dove_mpp_gpio_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .variant = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const struct of_device_id dove_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct regmap_config gc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .max_register = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int dove_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct resource *res, *mpp_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct resource fb_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) of_match_device(dove_pinctrl_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct mvebu_mpp_ctrl_data *mpp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pdev->dev.platform_data = (void *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * General MPP Configuration Register is part of pdma registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * grab clk to make sure it is ticking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_err(&pdev->dev, "Unable to get pdma clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) base = devm_ioremap_resource(&pdev->dev, mpp_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) sizeof(*mpp_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!mpp_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dove_pinctrl_info.control_data = mpp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mpp_data[i].base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* prepare fallback resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) memcpy(&fb_res, mpp_res, sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fb_res.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) adjust_resource(&fb_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) res = &fb_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mpp4_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (IS_ERR(mpp4_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return PTR_ERR(mpp4_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) adjust_resource(&fb_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) res = &fb_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pmu_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (IS_ERR(pmu_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return PTR_ERR(pmu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (IS_ERR(gconfmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) void __iomem *gc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) adjust_resource(&fb_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (IS_ERR(gc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return PTR_ERR(gc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) gconfmap = devm_regmap_init_mmio(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) gc_base, &gc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (IS_ERR(gconfmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return PTR_ERR(gconfmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Warn on any missing DT resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (fb_res.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return mvebu_pinctrl_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static struct platform_driver dove_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .name = "dove-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .of_match_table = dove_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .probe = dove_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) builtin_platform_driver(dove_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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