^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file supports the three variants of Armada XP SoCs that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * available: mv78230, mv78260 and mv78460. From a pin muxing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * both have 67 MPP pins (more GPIOs and address lines for the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * bus mainly).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinctrl-mvebu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u32 *mpp_saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum armada_xp_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) V_MV78230 = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) V_MV78260 = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) V_MV78460 = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) V_MV78260_PLUS = (V_MV78260 | V_MV78460),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) V_98DX3236 = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) V_98DX3336 = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) V_98DX4251 = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MPP_MODE(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MPP_MODE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MPP_MODE(2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MPP_MODE(3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MPP_MODE(4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MPP_MODE(5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MPP_MODE(6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MPP_MODE(7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MPP_MODE(8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MPP_MODE(9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MPP_MODE(10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MPP_MODE(11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MPP_MODE(12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MPP_MODE(13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MPP_MODE(14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MPP_MODE(15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MPP_MODE(16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MPP_MODE(17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MPP_MODE(18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MPP_MODE(19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MPP_MODE(20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MPP_MODE(21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MPP_MODE(22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MPP_MODE(23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MPP_MODE(24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MPP_MODE(25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MPP_MODE(26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MPP_MODE(27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MPP_MODE(28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MPP_MODE(29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MPP_MODE(30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MPP_MODE(31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MPP_MODE(32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MPP_MODE(33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MPP_MODE(34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MPP_MODE(35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MPP_MODE(36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MPP_MODE(37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MPP_MODE(38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MPP_MODE(39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MPP_MODE(40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MPP_MODE(41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MPP_MODE(42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MPP_MODE(43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MPP_MODE(44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MPP_MODE(45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MPP_MODE(46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MPP_MODE(47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MPP_MODE(48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MPP_MODE(49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MPP_MODE(50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MPP_MODE(51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MPP_MODE(52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MPP_MODE(53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MPP_MODE(54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MPP_MODE(55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MPP_MODE(56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MPP_MODE(57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MPP_MODE(58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MPP_MODE(59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MPP_MODE(60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MPP_MODE(61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MPP_MODE(62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MPP_MODE(63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MPP_MODE(64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MPP_MODE(65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MPP_MODE(66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MPP_MODE(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MPP_MODE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MPP_MODE(2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MPP_MODE(3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MPP_MODE(4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MPP_MODE(5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MPP_MODE(6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MPP_MODE(7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MPP_MODE(8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MPP_MODE(9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MPP_MODE(10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MPP_MODE(11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MPP_MODE(12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MPP_MODE(13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MPP_MODE(14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MPP_MODE(15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MPP_VAR_FUNCTION(0x1, "i2c0", "sda", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MPP_MODE(16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MPP_MODE(17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MPP_MODE(18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MPP_MODE(19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MPP_VAR_FUNCTION(0x4, "nand", "rb", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MPP_MODE(20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MPP_MODE(21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MPP_VAR_FUNCTION(0x4, "dev", "ad0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MPP_MODE(22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MPP_VAR_FUNCTION(0x4, "dev", "ad1", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MPP_MODE(23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MPP_VAR_FUNCTION(0x4, "dev", "ad2", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MPP_MODE(24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MPP_VAR_FUNCTION(0x4, "dev", "ad3", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MPP_MODE(25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MPP_VAR_FUNCTION(0x4, "dev", "ad4", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MPP_MODE(26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MPP_VAR_FUNCTION(0x4, "dev", "ad5", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MPP_MODE(27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MPP_VAR_FUNCTION(0x4, "dev", "ad6", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MPP_MODE(28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MPP_VAR_FUNCTION(0x4, "dev", "ad7", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MPP_MODE(29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MPP_VAR_FUNCTION(0x4, "dev", "a0", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MPP_MODE(30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MPP_VAR_FUNCTION(0x4, "dev", "a1", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MPP_MODE(31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MPP_MODE(32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct of_device_id armada_xp_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .compatible = "marvell,mv78230-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .data = (void *) V_MV78230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .compatible = "marvell,mv78260-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .data = (void *) V_MV78260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .compatible = "marvell,mv78460-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .data = (void *) V_MV78460,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .compatible = "marvell,98dx3236-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .data = (void *) V_98DX3236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .compatible = "marvell,98dx4251-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .data = (void *) V_98DX4251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MPP_FUNC_CTRL(0, 48, NULL, mvebu_mmio_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MPP_GPIO_RANGE(0, 0, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MPP_GPIO_RANGE(1, 32, 32, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MPP_GPIO_RANGE(0, 0, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MPP_GPIO_RANGE(1, 32, 32, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MPP_GPIO_RANGE(2, 64, 64, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MPP_GPIO_RANGE(0, 0, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MPP_GPIO_RANGE(1, 32, 32, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MPP_GPIO_RANGE(2, 64, 64, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MPP_GPIO_RANGE(0, 0, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mvebu_pinctrl_soc_info *soc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i, nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) for (i = 0; i < nregs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mpp_saved_regs[i] = readl(soc->control_data[0].base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int armada_xp_pinctrl_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct mvebu_pinctrl_soc_info *soc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int i, nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (i = 0; i < nregs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int armada_xp_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) soc->variant = (unsigned) match->data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) switch (soc->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case V_MV78230:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) soc->controls = mv78230_mpp_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) soc->modes = armada_xp_mpp_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* We don't necessarily want the full list of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * armada_xp_mpp_modes, but only the first 'n' ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * that are available on this SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) soc->nmodes = mv78230_mpp_controls[0].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) soc->gpioranges = mv78230_mpp_gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case V_MV78260:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) soc->controls = mv78260_mpp_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) soc->modes = armada_xp_mpp_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* We don't necessarily want the full list of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * armada_xp_mpp_modes, but only the first 'n' ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * that are available on this SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) soc->nmodes = mv78260_mpp_controls[0].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) soc->gpioranges = mv78260_mpp_gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case V_MV78460:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) soc->controls = mv78460_mpp_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) soc->modes = armada_xp_mpp_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* We don't necessarily want the full list of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * armada_xp_mpp_modes, but only the first 'n' ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * that are available on this SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) soc->nmodes = mv78460_mpp_controls[0].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) soc->gpioranges = mv78460_mpp_gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case V_98DX3236:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case V_98DX3336:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case V_98DX4251:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* fall-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) soc->controls = mv98dx3236_mpp_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) soc->modes = mv98dx3236_mpp_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) soc->nmodes = mv98dx3236_mpp_controls[0].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) soc->gpioranges = mv98dx3236_mpp_gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mpp_saved_regs = devm_kmalloc_array(&pdev->dev, nregs, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!mpp_saved_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pdev->dev.platform_data = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return mvebu_pinctrl_simple_mmio_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct platform_driver armada_xp_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .name = "armada-xp-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .of_match_table = armada_xp_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .probe = armada_xp_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .suspend = armada_xp_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .resume = armada_xp_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) builtin_platform_driver(armada_xp_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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