^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Marvell 37xx SoC pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2 or later. This program is licensed "as is"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * without any warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OUTPUT_EN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INPUT_VAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OUTPUT_VAL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OUTPUT_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SELECTION 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IRQ_EN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_POL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_WKUP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NB_FUNCS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The pins of a pinmux groups are composed of one or two groups of contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @name: Name of the pin group, used to lookup the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @start_pin: Index of the first pin of the main range of pins belonging to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @npins: Number of pins included in the first range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @reg_mask: Bit mask matching the group in the selection register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @val: Value to write to the registers for a given function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @extra_pin: Index of the first pin of the optional second range of pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * belonging to the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @extra_npins:Number of pins included in the second optional range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @funcs: A list of pinmux functions that can be selected for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @pins: List of the pins included in the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct armada_37xx_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int start_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 val[NB_FUNCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int extra_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int extra_npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const char *funcs[NB_FUNCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct armada_37xx_pin_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct armada_37xx_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct armada_37xx_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct armada_37xx_pm_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 out_en_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 out_en_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 out_val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 out_val_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 irq_en_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 irq_en_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 irq_pol_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 irq_pol_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 selection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct armada_37xx_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct armada_37xx_pin_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pinctrl_desc pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct armada_37xx_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct armada_37xx_pmx_func *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct armada_37xx_pm_state pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .start_pin = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .npins = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .val = {0, _mask}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .funcs = {_func1, _func2} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .start_pin = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .npins = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .val = {0, _mask}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .funcs = {_func1, "gpio"} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .start_pin = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .npins = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .val = {_val1, _val2}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .funcs = {_func1, "gpio"} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .start_pin = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .npins = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .val = {_v1, _v2, _v3}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .funcs = {_f1, _f2, "gpio"} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) _f1, _f2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .start_pin = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .npins = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .val = {_v1, _v2}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .extra_pin = _start2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .extra_npins = _nr2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .funcs = {_f1, _f2} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "pwm", "led"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "pwm", "led"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "pwm", "led"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "pwm", "led"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 18, 2, "gpio", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "mii", "mii_err"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .nr_pins = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "GPIO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .groups = armada_37xx_nb_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .nr_pins = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "GPIO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .groups = armada_37xx_sb_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static inline void armada_37xx_update_reg(unsigned int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* We never have more than 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (*offset >= GPIO_PER_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *offset -= GPIO_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *reg += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct armada_37xx_pinctrl *info, int pin, int *grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) while (*grp < info->ngroups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct armada_37xx_pin_group *group = &info->groups[*grp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *grp = *grp + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (j = 0; j < (group->npins + group->extra_npins); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (group->pins[j] == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int selector, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int selector, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct pinconf_ops armada_37xx_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .pin_config_group_get = armada_37xx_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .pin_config_group_set = armada_37xx_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return info->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *pins = info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *npins = info->groups[selector].npins +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) info->groups[selector].extra_npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct pinctrl_ops armada_37xx_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .get_groups_count = armada_37xx_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .get_group_name = armada_37xx_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .get_group_pins = armada_37xx_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Pinmux_ops handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return info->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return info->funcs[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *groups = info->funcs[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *num_groups = info->funcs[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct armada_37xx_pin_group *grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int reg = SELECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int mask = grp->reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int func, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_dbg(info->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) func = match_string(grp->funcs, NB_FUNCS, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (func < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) val = grp->val[func];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) regmap_update_bits(info->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct armada_37xx_pin_group *grp = &info->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const char *name = info->funcs[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return armada_37xx_pmx_set_by_name(pctldev, name, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static inline void armada_37xx_irq_update_reg(unsigned int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) armada_37xx_update_reg(reg, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int reg = OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) armada_37xx_update_reg(®, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return regmap_update_bits(info->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int reg = OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) armada_37xx_update_reg(®, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) regmap_read(info->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int reg = OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int mask, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) armada_37xx_update_reg(®, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = regmap_update_bits(info->regmap, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reg = OUTPUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val = value ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) regmap_update_bits(info->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int reg = INPUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) armada_37xx_update_reg(®, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regmap_read(info->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return (val & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int reg = OUTPUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) armada_37xx_update_reg(®, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val = value ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(info->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct gpio_chip *chip = range->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) offset, range->name, offset, input ? "input" : "output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) armada_37xx_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) armada_37xx_gpio_direction_output(chip, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct armada_37xx_pin_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int grp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(info->dev, "requesting gpio %d\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct pinmux_ops armada_37xx_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .get_functions_count = armada_37xx_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .get_function_name = armada_37xx_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .get_function_groups = armada_37xx_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_mux = armada_37xx_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .gpio_request_enable = armada_37xx_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct gpio_chip armada_37xx_gpiolib_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .set = armada_37xx_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .get = armada_37xx_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .get_direction = armada_37xx_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .direction_input = armada_37xx_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .direction_output = armada_37xx_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void armada_37xx_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 reg = IRQ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) armada_37xx_irq_update_reg(®, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(d->mask, info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void armada_37xx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 val, reg = IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) armada_37xx_irq_update_reg(®, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val = readl(info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) writel(val & ~d->mask, info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void armada_37xx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 val, reg = IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) armada_37xx_irq_update_reg(®, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = readl(info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(val | d->mask, info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 val, reg = IRQ_WKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) armada_37xx_irq_update_reg(®, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = readl(info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) val |= (BIT(d->hwirq % GPIO_PER_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val &= ~(BIT(d->hwirq % GPIO_PER_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) writel(val, info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 val, reg = IRQ_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) armada_37xx_irq_update_reg(®, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val = readl(info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val &= ~(BIT(d->hwirq % GPIO_PER_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) val |= (BIT(d->hwirq % GPIO_PER_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case IRQ_TYPE_EDGE_BOTH: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 in_val, in_reg = INPUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) armada_37xx_irq_update_reg(&in_reg, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) regmap_read(info->regmap, in_reg, &in_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Set initial polarity based on current input level. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (in_val & BIT(d->hwirq % GPIO_PER_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writel(val, info->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 pin_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 reg_idx = pin_idx / GPIO_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 bit_num = pin_idx % GPIO_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 p, l, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) p = readl(info->base + IRQ_POL + 4 * reg_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if ((p ^ l) & (1 << bit_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * For the gpios which are used for both-edge irqs, when their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * interrupts happen, their input levels are changed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * yet their interrupt polarities are kept in old values, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * should synchronize their interrupt polarities; for example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * at first a gpio's input level is low and its interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * polarity control is "Detect rising edge", then the gpio has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * a interrupt , its level turns to high, we should change its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * polarity control to "Detect falling edge" correspondingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) p ^= 1 << bit_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel(p, info->base + IRQ_POL + 4 * reg_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Spurious irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void armada_37xx_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct irq_domain *d = gc->irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Manage only the interrupt that was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 hwirq = ffs(status) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 virq = irq_find_mapping(d, hwirq +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) i * GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 t = irq_get_trigger_type(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Swap polarity (race with GPIO line) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (armada_37xx_edge_both_irq_swap_pol(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) hwirq + i * GPIO_PER_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * For spurious irq, which gpio level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * is not as expected after incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * edge, just ack the gpio irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(1 << hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) info->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) IRQ_STATUS + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto update_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) update_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Update status in case a new IRQ appears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spin_lock_irqsave(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) status = readl_relaxed(info->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) IRQ_STATUS + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Manage only the interrupt that was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_unlock_irqrestore(&info->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static unsigned int armada_37xx_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * The mask field is a "precomputed bitmask for accessing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * chip registers" which was introduced for the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * irqchip framework. As we don't use this framework, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * reuse this field for our own usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) d->mask = BIT(d->hwirq % GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) armada_37xx_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int armada_37xx_irqchip_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct armada_37xx_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct device_node *np = info->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct gpio_chip *gc = &info->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct irq_chip *irqchip = &info->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct gpio_irq_chip *girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int ret = -ENODEV, i, nr_irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Check if we have at least one gpio-controller child node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) for_each_child_of_node(info->dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (of_property_read_bool(np, "gpio-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(dev, "no gpio-controller child node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) nr_irq_parent = of_irq_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) spin_lock_init(&info->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!nr_irq_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(dev, "invalid or no IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (of_address_to_resource(info->dev->of_node, 1, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(dev, "cannot find IO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) info->base = devm_ioremap_resource(info->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (IS_ERR(info->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return PTR_ERR(info->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) irqchip->irq_ack = armada_37xx_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) irqchip->irq_mask = armada_37xx_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) irqchip->irq_unmask = armada_37xx_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) irqchip->irq_set_wake = armada_37xx_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) irqchip->irq_set_type = armada_37xx_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) irqchip->irq_startup = armada_37xx_irq_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) irqchip->name = info->data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) girq->chip = irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) girq->parent_handler = armada_37xx_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Many interrupts are connected to the parent interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * controller. But we do not take advantage of this and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * the chained irq with all of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) girq->num_parents = nr_irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) sizeof(*girq->parents), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) for (i = 0; i < nr_irq_parent; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int irq = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) girq->parents[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int armada_37xx_gpiochip_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct armada_37xx_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) for_each_child_of_node(info->dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (of_find_property(np, "gpio-controller", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) info->gpio_chip = armada_37xx_gpiolib_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) gc = &info->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) gc->ngpio = info->data->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) gc->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) gc->label = info->data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = armada_37xx_irqchip_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * armada_37xx_add_function() - Add a new function to the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * @funcs: array of function to add the new one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * @funcsize: size of the remaining space for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * @name: name of the function to add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * If it is a new function then create it by adding its name else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * increment the number of group associated to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int *funcsize, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (*funcsize <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) while (funcs->ngroups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* function already there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (strcmp(funcs->name, name) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) funcs->ngroups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) funcs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* append new unique function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) funcs->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) funcs->ngroups = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) (*funcsize)--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * armada_37xx_fill_group() - complete the group array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * @info: info driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Based on the data available from the armada_37xx_pin_group array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * completes the last member of the struct for each function: the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * of the groups associated to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int n, num = 0, funcsize = info->data->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for (n = 0; n < info->ngroups; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct armada_37xx_pin_group *grp = &info->groups[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int i, j, f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) grp->pins = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) grp->npins + grp->extra_npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) sizeof(*grp->pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!grp->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) for (i = 0; i < grp->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) grp->pins[i] = grp->start_pin + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) for (j = 0; j < grp->extra_npins; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) grp->pins[i+j] = grp->extra_pin + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* check for unique functions and count groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = armada_37xx_add_function(info->funcs, &funcsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) grp->funcs[f]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (ret == -EOVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "More functions than pins(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) info->data->nr_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) info->nfuncs = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * armada_37xx_fill_funcs() - complete the funcs array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * @info: info driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Based on the data available from the armada_37xx_pin_group array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * completes the last two member of the struct for each group:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * - the list of the pins included in the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * - the list of pinmux functions that can be selected for this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct armada_37xx_pmx_func *funcs = info->funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (n = 0; n < info->nfuncs; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) const char *name = funcs[n].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) funcs[n].groups = devm_kcalloc(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) funcs[n].ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) sizeof(*(funcs[n].groups)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!funcs[n].groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) groups = funcs[n].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) for (g = 0; g < info->ngroups; g++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct armada_37xx_pin_group *gp = &info->groups[g];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) f = match_string(gp->funcs, NB_FUNCS, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (f < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *groups = gp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) groups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int armada_37xx_pinctrl_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct armada_37xx_pinctrl *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) const struct armada_37xx_pin_data *pin_data = info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct pinctrl_desc *ctrldesc = &info->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct pinctrl_pin_desc *pindesc, *pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int pin, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) info->groups = pin_data->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) info->ngroups = pin_data->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ctrldesc->name = "armada_37xx-pinctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ctrldesc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ctrldesc->pctlops = &armada_37xx_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ctrldesc->pmxops = &armada_37xx_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ctrldesc->confops = &armada_37xx_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pindesc = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) pin_data->nr_pins, sizeof(*pindesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!pindesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ctrldesc->pins = pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ctrldesc->npins = pin_data->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pdesc = pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) for (pin = 0; pin < pin_data->nr_pins; pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pdesc->number = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pin_data->name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pdesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * we allocate functions for number of pins and hope there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * fewer unique functions than pins available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) info->funcs = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pin_data->nr_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) sizeof(struct armada_37xx_pmx_func),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!info->funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = armada_37xx_fill_group(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = armada_37xx_fill_func(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (IS_ERR(info->pctl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_err(&pdev->dev, "could not register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return PTR_ERR(info->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #if defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int armada_3700_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Save GPIO state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &info->pm.out_val_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) info->pm.irq_en_l = readl(info->base + IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) info->pm.irq_pol_l = readl(info->base + IRQ_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* Save pinctrl state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) regmap_read(info->regmap, SELECTION, &info->pm.selection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int armada_3700_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct irq_domain *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Restore GPIO state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) info->pm.out_en_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) info->pm.out_val_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Input levels may change during suspend, which is not monitored at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * that time. GPIOs used for both-edge IRQs may not be synchronized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * anymore with their polarities (rising/falling edge) and must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * re-configured manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) gc = &info->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) d = gc->irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u32 irq_bit = BIT(i % GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 mask, *irq_pol, input_reg, virq, type, level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (i < GPIO_PER_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mask = info->pm.irq_en_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) irq_pol = &info->pm.irq_pol_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) input_reg = INPUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mask = info->pm.irq_en_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) irq_pol = &info->pm.irq_pol_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) input_reg = INPUT_VAL + sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!(mask & irq_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) virq = irq_find_mapping(d, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) type = irq_get_trigger_type(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Synchronize level and polarity for both-edge irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * - a high input level expects a falling edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * - a low input level exepects a rising edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if ((type & IRQ_TYPE_SENSE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) regmap_read(info->regmap, input_reg, &level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if ((*irq_pol ^ level) & irq_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) *irq_pol ^= irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(info->pm.irq_en_l, info->base + IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) writel(info->pm.irq_pol_l, info->base + IRQ_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Restore pinctrl state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) regmap_write(info->regmap, SELECTION, info->pm.selection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * Since pinctrl is an infrastructure module, its resume should be issued prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * to other IO drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .suspend_noirq = armada_3700_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .resume_noirq = armada_3700_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .compatible = "marvell,armada3710-sb-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .data = &armada_37xx_pin_sb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .compatible = "marvell,armada3710-nb-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .data = &armada_37xx_pin_nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct armada_37xx_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) regmap = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_err(&pdev->dev, "cannot get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) info->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) info->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = armada_37xx_pinctrl_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ret = armada_37xx_gpiochip_register(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static struct platform_driver armada_37xx_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .name = "armada-37xx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .of_match_table = armada_37xx_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) armada_37xx_pinctrl_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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