^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pin controller and GPIO driver for Amlogic Meson8b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Endless Mobile, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/gpio/meson8b-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "pinctrl-meson.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-meson8-pmx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) MESON_PIN(GPIOX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MESON_PIN(GPIOX_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MESON_PIN(GPIOX_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MESON_PIN(GPIOX_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MESON_PIN(GPIOX_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MESON_PIN(GPIOX_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MESON_PIN(GPIOX_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MESON_PIN(GPIOX_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MESON_PIN(GPIOX_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MESON_PIN(GPIOX_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MESON_PIN(GPIOX_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MESON_PIN(GPIOX_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MESON_PIN(GPIOX_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MESON_PIN(GPIOX_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MESON_PIN(GPIOX_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MESON_PIN(GPIOX_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MESON_PIN(GPIOX_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MESON_PIN(GPIOX_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MESON_PIN(GPIOY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MESON_PIN(GPIOY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MESON_PIN(GPIOY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MESON_PIN(GPIOY_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MESON_PIN(GPIOY_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MESON_PIN(GPIOY_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MESON_PIN(GPIOY_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MESON_PIN(GPIOY_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MESON_PIN(GPIOY_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MESON_PIN(GPIOY_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MESON_PIN(GPIOY_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MESON_PIN(GPIOY_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MESON_PIN(GPIODV_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MESON_PIN(GPIODV_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MESON_PIN(GPIODV_25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MESON_PIN(GPIODV_26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MESON_PIN(GPIODV_27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MESON_PIN(GPIODV_28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MESON_PIN(GPIODV_29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MESON_PIN(GPIOH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MESON_PIN(GPIOH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MESON_PIN(GPIOH_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MESON_PIN(GPIOH_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MESON_PIN(GPIOH_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MESON_PIN(GPIOH_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MESON_PIN(GPIOH_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MESON_PIN(GPIOH_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MESON_PIN(GPIOH_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MESON_PIN(GPIOH_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MESON_PIN(CARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MESON_PIN(CARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MESON_PIN(CARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MESON_PIN(CARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MESON_PIN(CARD_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MESON_PIN(CARD_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MESON_PIN(CARD_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MESON_PIN(BOOT_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MESON_PIN(BOOT_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MESON_PIN(BOOT_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MESON_PIN(BOOT_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MESON_PIN(BOOT_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MESON_PIN(BOOT_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MESON_PIN(BOOT_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MESON_PIN(BOOT_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MESON_PIN(BOOT_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MESON_PIN(BOOT_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MESON_PIN(BOOT_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MESON_PIN(BOOT_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MESON_PIN(BOOT_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MESON_PIN(BOOT_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MESON_PIN(BOOT_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MESON_PIN(BOOT_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MESON_PIN(BOOT_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MESON_PIN(BOOT_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MESON_PIN(BOOT_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MESON_PIN(DIF_0_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MESON_PIN(DIF_0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MESON_PIN(DIF_1_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MESON_PIN(DIF_1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MESON_PIN(DIF_2_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MESON_PIN(DIF_2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MESON_PIN(DIF_3_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MESON_PIN(DIF_3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MESON_PIN(DIF_4_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MESON_PIN(DIF_4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MESON_PIN(GPIOAO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MESON_PIN(GPIOAO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MESON_PIN(GPIOAO_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MESON_PIN(GPIOAO_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MESON_PIN(GPIOAO_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MESON_PIN(GPIOAO_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MESON_PIN(GPIOAO_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MESON_PIN(GPIOAO_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MESON_PIN(GPIOAO_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MESON_PIN(GPIOAO_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MESON_PIN(GPIOAO_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MESON_PIN(GPIOAO_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MESON_PIN(GPIOAO_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MESON_PIN(GPIOAO_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The following 2 pins are not mentionned in the public datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * According to this datasheet, they can't be used with the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MESON_PIN(GPIO_BSD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MESON_PIN(GPIO_TEST_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* bank X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GPIOX_6, GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GPIOX_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const unsigned int pwm_e_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned int uart_tx_a_pins[] = { GPIOX_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const unsigned int uart_rx_a_pins[] = { GPIOX_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const unsigned int uart_cts_a_pins[] = { GPIOX_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const unsigned int uart_rts_a_pins[] = { GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned int spi_miso_0_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned int pwm_b_pins[] = { GPIOX_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* bank Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const unsigned int tsin_d17_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned int spdif_out_0_pins[] = { GPIOY_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned int xtal_24m_pins[] = { GPIOY_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* bank DV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int pwm_d_pins[] = { GPIODV_28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned int pwm_c0_pins[] = { GPIODV_29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const unsigned int xtal24_out_pins[] = { GPIODV_29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned int uart_tx_c_pins[] = { GPIODV_24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned int uart_rx_c_pins[] = { GPIODV_25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const unsigned int uart_cts_c_pins[] = { GPIODV_26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned int uart_rts_c_pins[] = { GPIODV_27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int pwm_c1_pins[] = { GPIODV_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* bank H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const unsigned int spi_ss1_pins[] = { GPIOH_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int spi_ss2_pins[] = { GPIOH_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const unsigned int spi_miso_1_pins[] = { GPIOH_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const unsigned int eth_txd3_pins[] = { GPIOH_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned int eth_txd2_pins[] = { GPIOH_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* bank BOOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const unsigned int nand_io_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const unsigned int nand_ale_pins[] = { BOOT_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned int nand_cle_pins[] = { BOOT_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const unsigned int nand_dqs_15_pins[] = { BOOT_15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const unsigned int nand_dqs_18_pins[] = { BOOT_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) BOOT_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) BOOT_6, BOOT_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const unsigned int nor_d_pins[] = { BOOT_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned int nor_q_pins[] = { BOOT_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const unsigned int nor_c_pins[] = { BOOT_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned int nor_cs_pins[] = { BOOT_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const unsigned int sd_cmd_c_pins[] = { BOOT_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const unsigned int sd_clk_c_pins[] = { BOOT_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* bank CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned int sd_d1_b_pins[] = { CARD_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const unsigned int sd_d0_b_pins[] = { CARD_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const unsigned int sd_clk_b_pins[] = { CARD_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned int sd_d3_b_pins[] = { CARD_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const unsigned int sd_d2_b_pins[] = { CARD_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CARD_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* bank AO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const unsigned int remote_input_pins[] = { GPIOAO_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int ir_blaster_pins[] = { GPIOAO_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int pwm_c2_pins[] = { GPIOAO_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* bank DIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int eth_rxd1_pins[] = { DIF_0_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int eth_rxd0_pins[] = { DIF_0_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int eth_rx_dv_pins[] = { DIF_1_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const unsigned int eth_rx_clk_pins[] = { DIF_1_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int eth_txd0_1_pins[] = { DIF_2_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int eth_txd1_1_pins[] = { DIF_2_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int eth_rxd3_pins[] = { DIF_2_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int eth_rxd2_pins[] = { DIF_2_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int eth_tx_en_pins[] = { DIF_3_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int eth_ref_clk_pins[] = { DIF_3_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int eth_mdc_pins[] = { DIF_4_P };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned int eth_mdio_en_pins[] = { DIF_4_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct meson_pmx_group meson8b_cbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) GPIO_GROUP(GPIOX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) GPIO_GROUP(GPIOX_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) GPIO_GROUP(GPIOX_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GPIO_GROUP(GPIOX_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GPIO_GROUP(GPIOX_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GPIO_GROUP(GPIOX_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GPIO_GROUP(GPIOX_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GPIO_GROUP(GPIOX_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GPIO_GROUP(GPIOX_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) GPIO_GROUP(GPIOX_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) GPIO_GROUP(GPIOX_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GPIO_GROUP(GPIOX_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) GPIO_GROUP(GPIOX_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) GPIO_GROUP(GPIOX_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) GPIO_GROUP(GPIOX_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) GPIO_GROUP(GPIOX_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) GPIO_GROUP(GPIOX_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) GPIO_GROUP(GPIOX_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) GPIO_GROUP(GPIOY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) GPIO_GROUP(GPIOY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GPIO_GROUP(GPIOY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) GPIO_GROUP(GPIOY_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GPIO_GROUP(GPIOY_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GPIO_GROUP(GPIOY_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GPIO_GROUP(GPIOY_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GPIO_GROUP(GPIOY_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GPIO_GROUP(GPIOY_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GPIO_GROUP(GPIOY_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GPIO_GROUP(GPIOY_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) GPIO_GROUP(GPIOY_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) GPIO_GROUP(GPIODV_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) GPIO_GROUP(GPIODV_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GPIO_GROUP(GPIODV_25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GPIO_GROUP(GPIODV_26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GPIO_GROUP(GPIODV_27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) GPIO_GROUP(GPIODV_28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) GPIO_GROUP(GPIODV_29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) GPIO_GROUP(GPIOH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) GPIO_GROUP(GPIOH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GPIO_GROUP(GPIOH_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GPIO_GROUP(GPIOH_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GPIO_GROUP(GPIOH_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GPIO_GROUP(GPIOH_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GPIO_GROUP(GPIOH_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) GPIO_GROUP(GPIOH_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) GPIO_GROUP(GPIOH_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GPIO_GROUP(GPIOH_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GPIO_GROUP(CARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) GPIO_GROUP(CARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GPIO_GROUP(CARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GPIO_GROUP(CARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GPIO_GROUP(CARD_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GPIO_GROUP(CARD_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GPIO_GROUP(CARD_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GPIO_GROUP(BOOT_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GPIO_GROUP(BOOT_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GPIO_GROUP(BOOT_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GPIO_GROUP(BOOT_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GPIO_GROUP(BOOT_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GPIO_GROUP(BOOT_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GPIO_GROUP(BOOT_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GPIO_GROUP(BOOT_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPIO_GROUP(BOOT_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GPIO_GROUP(BOOT_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GPIO_GROUP(BOOT_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GPIO_GROUP(BOOT_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GPIO_GROUP(BOOT_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GPIO_GROUP(BOOT_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GPIO_GROUP(BOOT_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GPIO_GROUP(BOOT_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GPIO_GROUP(BOOT_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GPIO_GROUP(BOOT_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GPIO_GROUP(BOOT_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GPIO_GROUP(DIF_0_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GPIO_GROUP(DIF_0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GPIO_GROUP(DIF_1_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GPIO_GROUP(DIF_1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) GPIO_GROUP(DIF_2_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GPIO_GROUP(DIF_2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) GPIO_GROUP(DIF_3_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GPIO_GROUP(DIF_3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GPIO_GROUP(DIF_4_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GPIO_GROUP(DIF_4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* bank X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) GROUP(sd_d0_a, 8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GROUP(sd_d1_a, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GROUP(sd_d2_a, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) GROUP(sd_d3_a, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) GROUP(sdxc_d0_0_a, 5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GROUP(sdxc_d47_a, 5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GROUP(sdxc_d13_0_a, 5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GROUP(sd_clk_a, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GROUP(sd_cmd_a, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GROUP(xtal_32k_out, 3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GROUP(xtal_24m_out, 3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GROUP(uart_tx_b0, 4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GROUP(uart_rx_b0, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GROUP(uart_cts_b0, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GROUP(uart_rts_b0, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GROUP(sdxc_d0_1_a, 5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GROUP(sdxc_d13_1_a, 5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GROUP(pcm_out_a, 3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GROUP(pcm_in_a, 3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GROUP(pcm_fs_a, 3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GROUP(pcm_clk_a, 3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GROUP(sdxc_clk_a, 5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GROUP(sdxc_cmd_a, 5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GROUP(pwm_vs_0, 7, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GROUP(pwm_e, 9, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GROUP(pwm_vs_1, 7, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GROUP(uart_tx_a, 4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GROUP(uart_rx_a, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GROUP(uart_cts_a, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GROUP(uart_rts_a, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GROUP(uart_tx_b1, 6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GROUP(uart_rx_b1, 6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GROUP(uart_cts_b1, 6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GROUP(uart_rts_b1, 6, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GROUP(iso7816_0_clk, 5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GROUP(iso7816_0_data, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GROUP(spi_sclk_0, 4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GROUP(spi_miso_0, 4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GROUP(spi_mosi_0, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GROUP(iso7816_det, 4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GROUP(iso7816_reset, 4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GROUP(iso7816_1_clk, 4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GROUP(iso7816_1_data, 4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GROUP(spi_ss0_0, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GROUP(tsin_clk_b, 3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GROUP(tsin_sop_b, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GROUP(tsin_d0_b, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GROUP(pwm_b, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GROUP(i2c_sda_d0, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GROUP(i2c_sck_d0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GROUP(tsin_d_valid_b, 3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* bank Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GROUP(tsin_d_valid_a, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GROUP(tsin_sop_a, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GROUP(tsin_d17_a, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GROUP(tsin_clk_a, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GROUP(tsin_d0_a, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GROUP(spdif_out_0, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GROUP(xtal_24m, 3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GROUP(iso7816_2_clk, 5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GROUP(iso7816_2_data, 5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* bank DV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GROUP(pwm_d, 3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GROUP(pwm_c0, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GROUP(pwm_vs_2, 7, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GROUP(pwm_vs_3, 7, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GROUP(pwm_vs_4, 7, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GROUP(xtal24_out, 7, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GROUP(uart_tx_c, 6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GROUP(uart_rx_c, 6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GROUP(uart_cts_c, 6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GROUP(uart_rts_c, 6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GROUP(pwm_c1, 3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GROUP(i2c_sda_a, 9, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GROUP(i2c_sck_a, 9, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GROUP(i2c_sda_b0, 9, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GROUP(i2c_sck_b0, 9, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GROUP(i2c_sda_c0, 9, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GROUP(i2c_sck_c0, 9, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* bank H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GROUP(hdmi_hpd, 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GROUP(hdmi_sda, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GROUP(hdmi_scl, 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GROUP(hdmi_cec_0, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GROUP(eth_txd1_0, 7, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GROUP(eth_txd0_0, 7, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GROUP(clk_24m_out, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GROUP(spi_ss1, 8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GROUP(spi_ss2, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GROUP(spi_ss0_1, 9, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GROUP(spi_miso_1, 9, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GROUP(spi_mosi_1, 9, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GROUP(spi_sclk_1, 9, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GROUP(eth_rxd3_h, 6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GROUP(eth_rxd2_h, 6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GROUP(eth_txd3, 6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GROUP(eth_txd2, 6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GROUP(eth_tx_clk, 6, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GROUP(i2c_sda_b1, 5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GROUP(i2c_sck_b1, 5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GROUP(i2c_sda_c1, 5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GROUP(i2c_sck_c1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GROUP(i2c_sda_d1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GROUP(i2c_sck_d1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* bank BOOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GROUP(nand_io, 2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GROUP(nand_io_ce0, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GROUP(nand_io_ce1, 2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GROUP(nand_io_rb0, 2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GROUP(nand_ale, 2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GROUP(nand_cle, 2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GROUP(nand_wen_clk, 2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GROUP(nand_ren_clk, 2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GROUP(nand_dqs_15, 2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GROUP(nand_dqs_18, 2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GROUP(sdxc_d0_c, 4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GROUP(sdxc_d13_c, 4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GROUP(sdxc_d47_c, 4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GROUP(sdxc_clk_c, 7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GROUP(sdxc_cmd_c, 7, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GROUP(nor_d, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GROUP(nor_q, 5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GROUP(nor_c, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GROUP(nor_cs, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GROUP(sd_d0_c, 6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GROUP(sd_d1_c, 6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GROUP(sd_d2_c, 6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GROUP(sd_d3_c, 6, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GROUP(sd_cmd_c, 6, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GROUP(sd_clk_c, 6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* bank CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GROUP(sd_d1_b, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GROUP(sd_d0_b, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GROUP(sd_clk_b, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GROUP(sd_cmd_b, 2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GROUP(sd_d3_b, 2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GROUP(sd_d2_b, 2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GROUP(sdxc_d13_b, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GROUP(sdxc_d0_b, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GROUP(sdxc_clk_b, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GROUP(sdxc_cmd_b, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* bank DIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GROUP(eth_rxd1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GROUP(eth_rxd0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GROUP(eth_rx_dv, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GROUP(eth_rx_clk, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GROUP(eth_txd0_1, 6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GROUP(eth_txd1_1, 6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GROUP(eth_tx_en, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GROUP(eth_ref_clk, 6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GROUP(eth_mdc, 6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GROUP(eth_mdio_en, 6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GROUP(eth_rxd3, 7, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GROUP(eth_rxd2, 7, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct meson_pmx_group meson8b_aobus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GPIO_GROUP(GPIOAO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GPIO_GROUP(GPIOAO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GPIO_GROUP(GPIOAO_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GPIO_GROUP(GPIOAO_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GPIO_GROUP(GPIOAO_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GPIO_GROUP(GPIOAO_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GPIO_GROUP(GPIOAO_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GPIO_GROUP(GPIOAO_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GPIO_GROUP(GPIOAO_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GPIO_GROUP(GPIOAO_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GPIO_GROUP(GPIOAO_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GPIO_GROUP(GPIOAO_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GPIO_GROUP(GPIOAO_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GPIO_GROUP(GPIOAO_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GPIO_GROUP(GPIO_BSD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GPIO_GROUP(GPIO_TEST_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* bank AO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GROUP(uart_tx_ao_a, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GROUP(uart_rx_ao_a, 0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GROUP(uart_cts_ao_a, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GROUP(uart_rts_ao_a, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GROUP(i2c_mst_sck_ao, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GROUP(i2c_mst_sda_ao, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GROUP(clk_32k_in_out, 0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GROUP(remote_input, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GROUP(hdmi_cec_1, 0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GROUP(ir_blaster, 0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GROUP(pwm_c2, 0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GROUP(i2c_sck_ao, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GROUP(i2c_sda_ao, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GROUP(ir_remote_out, 0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GROUP(i2s_am_clk_out, 0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GROUP(i2s_ao_clk_out, 0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GROUP(i2s_lr_clk_out, 0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GROUP(i2s_out_01, 0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GROUP(uart_tx_ao_b0, 0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GROUP(uart_rx_ao_b0, 0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GROUP(uart_cts_ao_b, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GROUP(uart_rts_ao_b, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GROUP(uart_tx_ao_b1, 0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GROUP(uart_rx_ao_b1, 0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GROUP(spdif_out_1, 0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GROUP(i2s_in_ch01, 0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GROUP(i2s_ao_clk_in, 0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GROUP(i2s_lr_clk_in, 0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const char * const gpio_periphs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "GPIOX_19", "GPIOX_20", "GPIOX_21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "GPIOY_13", "GPIOY_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "GPIODV_27", "GPIODV_28", "GPIODV_29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "CARD_5", "CARD_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "DIF_4_P", "DIF_4_N"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char * const gpio_aobus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const char * const sd_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "sd_cmd_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const char * const sdxc_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d13_1_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const char * const pcm_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const char * const uart_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char * const uart_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const char * const iso7816_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const char * const i2c_d_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const char * const xtal_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const char * const uart_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const char * const i2c_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const hdmi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char * const hdmi_cec_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "hdmi_cec_1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const char * const spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "spi_miso_1", "spi_ss2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const char * const ethernet_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "eth_rxd3_h", "eth_rxd2_h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const char * const i2c_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "i2c_sda_a", "i2c_sck_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const char * const i2c_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const sd_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "sd_cmd_c", "sd_clk_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const char * const sdxc_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "sdxc_clk_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char * const nand_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "nand_io", "nand_io_ce0", "nand_io_ce1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "nand_io_rb0", "nand_ale", "nand_cle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "nand_wen_clk", "nand_ren_clk", "nand_dqs_15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "nand_dqs_18"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const char * const nor_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "nor_d", "nor_q", "nor_c", "nor_cs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const sd_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "sd_d3_b", "sd_d2_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const char * const sdxc_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const char * const uart_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const char * const remote_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "remote_input", "ir_blaster", "ir_remote_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const char * const i2c_slave_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "i2c_sck_ao", "i2c_sda_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const char * const uart_ao_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "uart_cts_ao_b", "uart_rts_ao_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const char * const i2c_mst_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "i2c_mst_sck_ao", "i2c_mst_sda_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const char * const clk_24m_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "clk_24m_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const char * const clk_32k_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "clk_32k_in_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const char * const spdif_0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "spdif_out_0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const char * const spdif_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "spdif_out_1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const char * const i2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "i2s_lr_clk_in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const char * const pwm_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "pwm_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const char * const pwm_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "pwm_c0", "pwm_c1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const char * const pwm_c_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "pwm_c2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const char * const pwm_d_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "pwm_d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const char * const pwm_e_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "pwm_e"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const char * const pwm_vs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "pwm_vs_0", "pwm_vs_1", "pwm_vs_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "pwm_vs_3", "pwm_vs_4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const char * const tsin_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "tsin_d_valid_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const char * const tsin_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static struct meson_pmx_func meson8b_cbus_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) FUNCTION(gpio_periphs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) FUNCTION(sd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) FUNCTION(sdxc_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) FUNCTION(pcm_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) FUNCTION(uart_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) FUNCTION(uart_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FUNCTION(iso7816),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) FUNCTION(i2c_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) FUNCTION(xtal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) FUNCTION(uart_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) FUNCTION(i2c_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) FUNCTION(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) FUNCTION(spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) FUNCTION(ethernet),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) FUNCTION(i2c_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FUNCTION(i2c_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) FUNCTION(sd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) FUNCTION(sdxc_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) FUNCTION(nor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) FUNCTION(sd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) FUNCTION(sdxc_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) FUNCTION(spdif_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) FUNCTION(pwm_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) FUNCTION(pwm_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) FUNCTION(pwm_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) FUNCTION(pwm_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) FUNCTION(pwm_vs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) FUNCTION(tsin_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) FUNCTION(tsin_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) FUNCTION(clk_24m),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct meson_pmx_func meson8b_aobus_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) FUNCTION(gpio_aobus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) FUNCTION(uart_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) FUNCTION(uart_ao_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) FUNCTION(i2c_slave_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) FUNCTION(i2c_mst_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) FUNCTION(i2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) FUNCTION(remote),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) FUNCTION(clk_32k),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) FUNCTION(pwm_c_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) FUNCTION(spdif_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) FUNCTION(hdmi_cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static struct meson_bank meson8b_cbus_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* name first last irq pullen pull dir out in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * The following bank is not mentionned in the public datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * There is no information whether it can be used with the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct meson_bank meson8b_aobus_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* name first lastc irq pullen pull dir out in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .name = "cbus-banks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .pins = meson8b_cbus_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .groups = meson8b_cbus_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .funcs = meson8b_cbus_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .banks = meson8b_cbus_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .num_pins = ARRAY_SIZE(meson8b_cbus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .num_groups = ARRAY_SIZE(meson8b_cbus_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .num_banks = ARRAY_SIZE(meson8b_cbus_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .pmx_ops = &meson8_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .name = "aobus-banks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .pins = meson8b_aobus_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .groups = meson8b_aobus_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .funcs = meson8b_aobus_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .banks = meson8b_aobus_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .num_pins = ARRAY_SIZE(meson8b_aobus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .num_groups = ARRAY_SIZE(meson8b_aobus_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .num_banks = ARRAY_SIZE(meson8b_aobus_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .pmx_ops = &meson8_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .parse_dt = &meson8_aobus_parse_dt_extra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const struct of_device_id meson8b_pinctrl_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .compatible = "amlogic,meson8b-cbus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .data = &meson8b_cbus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .compatible = "amlogic,meson8b-aobus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .data = &meson8b_aobus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct platform_driver meson8b_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .probe = meson_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .name = "meson8b-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .of_match_table = meson8b_pinctrl_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) builtin_platform_driver(meson8b_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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