^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/gpio/meson8-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pinctrl-meson.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "pinctrl-meson8-pmx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) MESON_PIN(GPIOX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) MESON_PIN(GPIOX_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MESON_PIN(GPIOX_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MESON_PIN(GPIOX_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MESON_PIN(GPIOX_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MESON_PIN(GPIOX_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MESON_PIN(GPIOX_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MESON_PIN(GPIOX_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MESON_PIN(GPIOX_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MESON_PIN(GPIOX_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MESON_PIN(GPIOX_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MESON_PIN(GPIOX_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MESON_PIN(GPIOX_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MESON_PIN(GPIOX_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MESON_PIN(GPIOX_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MESON_PIN(GPIOX_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MESON_PIN(GPIOX_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MESON_PIN(GPIOX_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MESON_PIN(GPIOX_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MESON_PIN(GPIOX_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MESON_PIN(GPIOX_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MESON_PIN(GPIOX_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MESON_PIN(GPIOY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MESON_PIN(GPIOY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MESON_PIN(GPIOY_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MESON_PIN(GPIOY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MESON_PIN(GPIOY_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MESON_PIN(GPIOY_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MESON_PIN(GPIOY_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MESON_PIN(GPIOY_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MESON_PIN(GPIOY_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MESON_PIN(GPIOY_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MESON_PIN(GPIOY_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MESON_PIN(GPIOY_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MESON_PIN(GPIOY_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MESON_PIN(GPIOY_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MESON_PIN(GPIOY_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MESON_PIN(GPIOY_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MESON_PIN(GPIOY_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MESON_PIN(GPIODV_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MESON_PIN(GPIODV_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MESON_PIN(GPIODV_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MESON_PIN(GPIODV_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MESON_PIN(GPIODV_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MESON_PIN(GPIODV_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MESON_PIN(GPIODV_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MESON_PIN(GPIODV_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MESON_PIN(GPIODV_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MESON_PIN(GPIODV_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MESON_PIN(GPIODV_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MESON_PIN(GPIODV_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MESON_PIN(GPIODV_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MESON_PIN(GPIODV_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MESON_PIN(GPIODV_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MESON_PIN(GPIODV_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MESON_PIN(GPIODV_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MESON_PIN(GPIODV_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MESON_PIN(GPIODV_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MESON_PIN(GPIODV_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MESON_PIN(GPIODV_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MESON_PIN(GPIODV_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MESON_PIN(GPIODV_22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MESON_PIN(GPIODV_23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MESON_PIN(GPIODV_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MESON_PIN(GPIODV_25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MESON_PIN(GPIODV_26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MESON_PIN(GPIODV_27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MESON_PIN(GPIODV_28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MESON_PIN(GPIODV_29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MESON_PIN(GPIOH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MESON_PIN(GPIOH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MESON_PIN(GPIOH_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MESON_PIN(GPIOH_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MESON_PIN(GPIOH_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MESON_PIN(GPIOH_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MESON_PIN(GPIOH_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MESON_PIN(GPIOH_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MESON_PIN(GPIOH_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MESON_PIN(GPIOH_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MESON_PIN(GPIOZ_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MESON_PIN(GPIOZ_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MESON_PIN(GPIOZ_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MESON_PIN(GPIOZ_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MESON_PIN(GPIOZ_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MESON_PIN(GPIOZ_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MESON_PIN(GPIOZ_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MESON_PIN(GPIOZ_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MESON_PIN(GPIOZ_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MESON_PIN(GPIOZ_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MESON_PIN(GPIOZ_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MESON_PIN(GPIOZ_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MESON_PIN(GPIOZ_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MESON_PIN(GPIOZ_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MESON_PIN(GPIOZ_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MESON_PIN(CARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MESON_PIN(CARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MESON_PIN(CARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MESON_PIN(CARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MESON_PIN(CARD_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MESON_PIN(CARD_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MESON_PIN(CARD_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MESON_PIN(BOOT_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MESON_PIN(BOOT_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MESON_PIN(BOOT_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MESON_PIN(BOOT_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MESON_PIN(BOOT_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MESON_PIN(BOOT_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MESON_PIN(BOOT_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MESON_PIN(BOOT_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MESON_PIN(BOOT_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MESON_PIN(BOOT_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MESON_PIN(BOOT_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MESON_PIN(BOOT_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MESON_PIN(BOOT_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MESON_PIN(BOOT_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MESON_PIN(BOOT_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MESON_PIN(BOOT_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MESON_PIN(BOOT_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MESON_PIN(BOOT_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MESON_PIN(BOOT_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MESON_PIN(GPIOAO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MESON_PIN(GPIOAO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MESON_PIN(GPIOAO_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MESON_PIN(GPIOAO_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MESON_PIN(GPIOAO_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MESON_PIN(GPIOAO_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MESON_PIN(GPIOAO_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MESON_PIN(GPIOAO_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MESON_PIN(GPIOAO_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MESON_PIN(GPIOAO_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MESON_PIN(GPIOAO_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MESON_PIN(GPIOAO_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MESON_PIN(GPIOAO_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MESON_PIN(GPIOAO_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MESON_PIN(GPIO_BSD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MESON_PIN(GPIO_TEST_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* bank X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int iso7816_clk_pins[] = { GPIOX_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned int iso7816_data_pins[] = { GPIOX_19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const unsigned int pwm_e_pins[] = { GPIOX_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned int pwm_b_x_pins[] = { GPIOX_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* bank Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned int uart_tx_c_pins[] = { GPIOY_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const unsigned int uart_rx_c_pins[] = { GPIOY_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int uart_cts_c_pins[] = { GPIOY_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned int uart_rts_c_pins[] = { GPIOY_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned int pcm_out_b_pins[] = { GPIOY_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned int pcm_in_b_pins[] = { GPIOY_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned int spdif_in_pins[] = { GPIOY_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int spdif_out_pins[] = { GPIOY_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* bank DV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const unsigned int dvin_rgb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned int dvin_vs_pins[] = { GPIODV_24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const unsigned int dvin_hs_pins[] = { GPIODV_25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const unsigned int dvin_clk_pins[] = { GPIODV_26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int dvin_de_pins[] = { GPIODV_27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const unsigned int enc_0_pins[] = { GPIODV_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const unsigned int enc_1_pins[] = { GPIODV_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const unsigned int enc_2_pins[] = { GPIODV_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const unsigned int enc_3_pins[] = { GPIODV_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const unsigned int enc_4_pins[] = { GPIODV_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned int enc_5_pins[] = { GPIODV_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const unsigned int enc_6_pins[] = { GPIODV_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const unsigned int enc_7_pins[] = { GPIODV_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const unsigned int enc_8_pins[] = { GPIODV_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned int enc_9_pins[] = { GPIODV_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const unsigned int enc_10_pins[] = { GPIODV_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const unsigned int enc_11_pins[] = { GPIODV_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const unsigned int enc_12_pins[] = { GPIODV_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned int enc_13_pins[] = { GPIODV_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const unsigned int enc_14_pins[] = { GPIODV_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const unsigned int enc_15_pins[] = { GPIODV_15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const unsigned int enc_16_pins[] = { GPIODV_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const unsigned int enc_17_pins[] = { GPIODV_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const unsigned int vga_vs_pins[] = { GPIODV_24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned int vga_hs_pins[] = { GPIODV_25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int pwm_d_pins[] = { GPIODV_28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* bank H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const unsigned int hdmi_cec_pins[] = { GPIOH_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const unsigned int spi_miso_0_pins[] = { GPIOH_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* bank Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned int eth_txd3_pins[] = { GPIOZ_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const unsigned int eth_txd2_pins[] = { GPIOZ_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int eth_txd0_pins[] = { GPIOZ_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const unsigned int eth_mdio_pins[] = { GPIOZ_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const unsigned int eth_mdc_pins[] = { GPIOZ_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* bank BOOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const unsigned int sd_cmd_c_pins[] = { BOOT_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const unsigned int sd_clk_c_pins[] = { BOOT_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) BOOT_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int nand_io_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int nand_ale_pins[] = { BOOT_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int nand_cle_pins[] = { BOOT_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned int nand_dqs_pins[] = { BOOT_15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned int nand_ce2_pins[] = { BOOT_16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned int nand_ce3_pins[] = { BOOT_17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned int nor_d_pins[] = { BOOT_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const unsigned int nor_q_pins[] = { BOOT_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const unsigned int nor_c_pins[] = { BOOT_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const unsigned int nor_cs_pins[] = { BOOT_18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* bank CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const unsigned int sd_d1_b_pins[] = { CARD_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const unsigned int sd_d0_b_pins[] = { CARD_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const unsigned int sd_clk_b_pins[] = { CARD_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const unsigned int sd_d3_b_pins[] = { CARD_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const unsigned int sd_d2_b_pins[] = { CARD_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* bank AO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const unsigned int remote_input_pins[] = { GPIOAO_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct meson_pmx_group meson8_cbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GPIO_GROUP(GPIOX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GPIO_GROUP(GPIOX_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GPIO_GROUP(GPIOX_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GPIO_GROUP(GPIOX_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GPIO_GROUP(GPIOX_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GPIO_GROUP(GPIOX_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GPIO_GROUP(GPIOX_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GPIO_GROUP(GPIOX_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GPIO_GROUP(GPIOX_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GPIO_GROUP(GPIOX_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GPIO_GROUP(GPIOX_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPIO_GROUP(GPIOX_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GPIO_GROUP(GPIOX_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GPIO_GROUP(GPIOX_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GPIO_GROUP(GPIOX_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GPIO_GROUP(GPIOX_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GPIO_GROUP(GPIOX_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GPIO_GROUP(GPIOX_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GPIO_GROUP(GPIOX_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GPIO_GROUP(GPIOX_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GPIO_GROUP(GPIOX_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GPIO_GROUP(GPIOX_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GPIO_GROUP(GPIOY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GPIO_GROUP(GPIOY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GPIO_GROUP(GPIOY_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GPIO_GROUP(GPIOY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GPIO_GROUP(GPIOY_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) GPIO_GROUP(GPIOY_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GPIO_GROUP(GPIOY_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) GPIO_GROUP(GPIOY_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GPIO_GROUP(GPIOY_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GPIO_GROUP(GPIOY_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GPIO_GROUP(GPIOY_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GPIO_GROUP(GPIOY_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GPIO_GROUP(GPIOY_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) GPIO_GROUP(GPIOY_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GPIO_GROUP(GPIOY_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GPIO_GROUP(GPIOY_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) GPIO_GROUP(GPIOY_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) GPIO_GROUP(GPIODV_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GPIO_GROUP(GPIODV_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GPIO_GROUP(GPIODV_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GPIO_GROUP(GPIODV_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GPIO_GROUP(GPIODV_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GPIO_GROUP(GPIODV_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GPIO_GROUP(GPIODV_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GPIO_GROUP(GPIODV_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GPIO_GROUP(GPIODV_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GPIO_GROUP(GPIODV_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GPIO_GROUP(GPIODV_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GPIO_GROUP(GPIODV_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GPIO_GROUP(GPIODV_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GPIO_GROUP(GPIODV_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GPIO_GROUP(GPIODV_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GPIO_GROUP(GPIODV_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GPIO_GROUP(GPIODV_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GPIO_GROUP(GPIODV_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GPIO_GROUP(GPIODV_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GPIO_GROUP(GPIODV_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GPIO_GROUP(GPIODV_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GPIO_GROUP(GPIODV_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GPIO_GROUP(GPIODV_22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GPIO_GROUP(GPIODV_23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GPIO_GROUP(GPIODV_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GPIO_GROUP(GPIODV_25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GPIO_GROUP(GPIODV_26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GPIO_GROUP(GPIODV_27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GPIO_GROUP(GPIODV_28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GPIO_GROUP(GPIODV_29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GPIO_GROUP(GPIOH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GPIO_GROUP(GPIOH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GPIO_GROUP(GPIOH_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GPIO_GROUP(GPIOH_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GPIO_GROUP(GPIOH_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GPIO_GROUP(GPIOH_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GPIO_GROUP(GPIOH_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GPIO_GROUP(GPIOH_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GPIO_GROUP(GPIOH_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GPIO_GROUP(GPIOH_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GPIO_GROUP(GPIOZ_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GPIO_GROUP(GPIOZ_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GPIO_GROUP(GPIOZ_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GPIO_GROUP(GPIOZ_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GPIO_GROUP(GPIOZ_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GPIO_GROUP(GPIOZ_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GPIO_GROUP(GPIOZ_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GPIO_GROUP(GPIOZ_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GPIO_GROUP(GPIOZ_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GPIO_GROUP(GPIOZ_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GPIO_GROUP(GPIOZ_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GPIO_GROUP(GPIOZ_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GPIO_GROUP(GPIOZ_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GPIO_GROUP(GPIOZ_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GPIO_GROUP(GPIOZ_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GPIO_GROUP(CARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GPIO_GROUP(CARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GPIO_GROUP(CARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GPIO_GROUP(CARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GPIO_GROUP(CARD_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GPIO_GROUP(CARD_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GPIO_GROUP(CARD_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GPIO_GROUP(BOOT_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GPIO_GROUP(BOOT_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GPIO_GROUP(BOOT_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GPIO_GROUP(BOOT_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GPIO_GROUP(BOOT_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GPIO_GROUP(BOOT_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GPIO_GROUP(BOOT_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GPIO_GROUP(BOOT_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GPIO_GROUP(BOOT_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GPIO_GROUP(BOOT_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GPIO_GROUP(BOOT_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GPIO_GROUP(BOOT_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GPIO_GROUP(BOOT_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GPIO_GROUP(BOOT_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GPIO_GROUP(BOOT_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GPIO_GROUP(BOOT_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPIO_GROUP(BOOT_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPIO_GROUP(BOOT_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GPIO_GROUP(BOOT_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* bank X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GROUP(sd_d0_a, 8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GROUP(sd_d1_a, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GROUP(sd_d2_a, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GROUP(sd_d3_a, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GROUP(sd_clk_a, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GROUP(sd_cmd_a, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GROUP(sdxc_d0_a, 5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GROUP(sdxc_d13_a, 5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GROUP(sdxc_d47_a, 5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GROUP(sdxc_clk_a, 5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GROUP(sdxc_cmd_a, 5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GROUP(pcm_out_a, 3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GROUP(pcm_in_a, 3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GROUP(pcm_fs_a, 3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GROUP(pcm_clk_a, 3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GROUP(uart_tx_a0, 4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GROUP(uart_rx_a0, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GROUP(uart_cts_a0, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GROUP(uart_rts_a0, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GROUP(uart_tx_a1, 4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GROUP(uart_rx_a1, 4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GROUP(uart_cts_a1, 4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GROUP(uart_rts_a1, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GROUP(uart_tx_b0, 4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GROUP(uart_rx_b0, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GROUP(uart_cts_b0, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GROUP(uart_rts_b0, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GROUP(iso7816_det, 4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GROUP(iso7816_reset, 4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GROUP(iso7816_clk, 4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GROUP(iso7816_data, 4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GROUP(i2c_sda_d0, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GROUP(i2c_sck_d0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GROUP(xtal_32k_out, 3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GROUP(xtal_24m_out, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GROUP(pwm_e, 9, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GROUP(pwm_b_x, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* bank Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GROUP(uart_tx_c, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GROUP(uart_rx_c, 1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GROUP(uart_cts_c, 1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GROUP(uart_rts_c, 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GROUP(pcm_out_b, 4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GROUP(pcm_in_b, 4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GROUP(pcm_fs_b, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GROUP(pcm_clk_b, 4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GROUP(i2c_sda_c0, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GROUP(i2c_sck_c0, 1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GROUP(pwm_a_y, 9, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GROUP(i2s_out_ch45, 1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GROUP(i2s_out_ch23, 1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GROUP(i2s_out_ch01, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GROUP(i2s_in_ch01, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GROUP(i2s_lr_clk_in, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GROUP(i2s_ao_clk_in, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GROUP(i2s_am_clk, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GROUP(i2s_out_ch78, 1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GROUP(spdif_in, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GROUP(spdif_out, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* bank DV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GROUP(dvin_rgb, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GROUP(dvin_vs, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GROUP(dvin_hs, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GROUP(dvin_clk, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GROUP(dvin_de, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GROUP(enc_0, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GROUP(enc_1, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GROUP(enc_2, 7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GROUP(enc_3, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GROUP(enc_4, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GROUP(enc_5, 7, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GROUP(enc_6, 7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GROUP(enc_7, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GROUP(enc_8, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GROUP(enc_9, 7, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GROUP(enc_10, 7, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GROUP(enc_11, 7, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GROUP(enc_12, 7, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GROUP(enc_13, 7, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GROUP(enc_14, 7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GROUP(enc_15, 7, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GROUP(enc_16, 7, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GROUP(enc_17, 7, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GROUP(uart_tx_b1, 6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GROUP(uart_rx_b1, 6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GROUP(uart_cts_b1, 6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GROUP(uart_rts_b1, 6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GROUP(vga_vs, 0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GROUP(vga_hs, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GROUP(pwm_c_dv9, 3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GROUP(pwm_c_dv29, 3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GROUP(pwm_d, 3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* bank H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GROUP(hdmi_hpd, 1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GROUP(hdmi_sda, 1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GROUP(hdmi_scl, 1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GROUP(hdmi_cec, 1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GROUP(spi_ss0_0, 9, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GROUP(spi_miso_0, 9, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GROUP(spi_mosi_0, 9, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GROUP(spi_sclk_0, 9, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GROUP(i2c_sda_d1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GROUP(i2c_sck_d1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* bank Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GROUP(spi_ss0_1, 8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GROUP(spi_ss1_1, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GROUP(spi_sclk_1, 8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GROUP(spi_mosi_1, 8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GROUP(spi_miso_1, 8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GROUP(spi_ss2_1, 8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GROUP(eth_tx_clk_50m, 6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GROUP(eth_tx_en, 6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GROUP(eth_txd1, 6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GROUP(eth_txd0, 6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GROUP(eth_rx_clk_in, 6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GROUP(eth_rx_dv, 6, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GROUP(eth_rxd1, 6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GROUP(eth_rxd0, 6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GROUP(eth_mdio, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GROUP(eth_mdc, 6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* NOTE: the following four groups are only available on Meson8m2: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GROUP(eth_rxd2, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GROUP(eth_rxd3, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) GROUP(eth_txd2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GROUP(eth_txd3, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GROUP(i2c_sda_a0, 5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) GROUP(i2c_sck_a0, 5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) GROUP(i2c_sda_b, 5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GROUP(i2c_sck_b, 5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GROUP(i2c_sda_c1, 5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GROUP(i2c_sck_c1, 5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GROUP(i2c_sda_a1, 5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GROUP(i2c_sck_a1, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GROUP(i2c_sda_a2, 5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GROUP(i2c_sck_a2, 5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GROUP(pwm_a_z0, 9, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GROUP(pwm_a_z7, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GROUP(pwm_b_z, 9, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) GROUP(pwm_c_z, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* bank BOOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) GROUP(sd_d0_c, 6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GROUP(sd_d1_c, 6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) GROUP(sd_d2_c, 6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GROUP(sd_d3_c, 6, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) GROUP(sd_cmd_c, 6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) GROUP(sd_clk_c, 6, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) GROUP(sdxc_d0_c, 4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GROUP(sdxc_d13_c, 4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GROUP(sdxc_d47_c, 4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GROUP(sdxc_cmd_c, 4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GROUP(sdxc_clk_c, 4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) GROUP(nand_io, 2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) GROUP(nand_io_ce0, 2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) GROUP(nand_io_ce1, 2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GROUP(nand_io_rb0, 2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GROUP(nand_ale, 2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) GROUP(nand_cle, 2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GROUP(nand_wen_clk, 2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GROUP(nand_ren_clk, 2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GROUP(nand_dqs, 2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) GROUP(nand_ce2, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GROUP(nand_ce3, 2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GROUP(nor_d, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GROUP(nor_q, 5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GROUP(nor_c, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GROUP(nor_cs, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* bank CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GROUP(sd_d1_b, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GROUP(sd_d0_b, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GROUP(sd_clk_b, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GROUP(sd_cmd_b, 2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GROUP(sd_d3_b, 2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GROUP(sd_d2_b, 2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GROUP(sdxc_d13_b, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GROUP(sdxc_d0_b, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) GROUP(sdxc_clk_b, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GROUP(sdxc_cmd_b, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static struct meson_pmx_group meson8_aobus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GPIO_GROUP(GPIOAO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GPIO_GROUP(GPIOAO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GPIO_GROUP(GPIOAO_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GPIO_GROUP(GPIOAO_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GPIO_GROUP(GPIOAO_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) GPIO_GROUP(GPIOAO_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GPIO_GROUP(GPIOAO_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GPIO_GROUP(GPIOAO_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GPIO_GROUP(GPIOAO_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GPIO_GROUP(GPIOAO_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GPIO_GROUP(GPIOAO_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GPIO_GROUP(GPIOAO_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GPIO_GROUP(GPIOAO_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) GPIO_GROUP(GPIOAO_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GPIO_GROUP(GPIO_BSD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GPIO_GROUP(GPIO_TEST_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* bank AO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GROUP(uart_tx_ao_a, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) GROUP(uart_rx_ao_a, 0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GROUP(uart_cts_ao_a, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) GROUP(uart_rts_ao_a, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) GROUP(remote_input, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GROUP(remote_output_ao, 0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GROUP(i2c_slave_sck_ao, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) GROUP(i2c_slave_sda_ao, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GROUP(uart_tx_ao_b0, 0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GROUP(uart_rx_ao_b0, 0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GROUP(uart_tx_ao_b1, 0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GROUP(uart_rx_ao_b1, 0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GROUP(i2c_mst_sck_ao, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GROUP(i2c_mst_sda_ao, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GROUP(pwm_f_ao, 0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GROUP(i2s_am_clk_out_ao, 0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GROUP(i2s_ao_clk_out_ao, 0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GROUP(i2s_lr_clk_out_ao, 0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GROUP(i2s_out_ch01_ao, 0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GROUP(hdmi_cec_ao, 0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const char * const gpio_periphs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "GPIOX_20", "GPIOX_21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "GPIOY_15", "GPIOY_16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "CARD_5", "CARD_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const char * const gpio_aobus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const char * const sd_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const char * const sdxc_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const char * const pcm_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const char * const uart_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const char * const uart_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const char * const iso7816_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const char * const i2c_d_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const char * const xtal_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "xtal_32k_out", "xtal_24m_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const char * const uart_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static const char * const pcm_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const char * const i2c_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const char * const dvin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const char * const enc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const char * const vga_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "vga_vs", "vga_hs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const char * const hdmi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const char * const spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "spi_miso_1", "spi_ss2_1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const char * const ethernet_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "eth_rxd3", "eth_txd2", "eth_txd3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const char * const i2c_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "i2c_sda_a2", "i2c_sck_a2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const char * const i2c_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "i2c_sda_b", "i2c_sck_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const char * const i2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "i2s_am_clk_pins", "i2s_out_ch78_pins"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const char * const sd_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "sd_cmd_c", "sd_clk_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const char * const sdxc_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "sdxc_clk_c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const char * const nand_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "nand_io", "nand_io_ce0", "nand_io_ce1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "nand_io_rb0", "nand_ale", "nand_cle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "nand_wen_clk", "nand_ren_clk", "nand_dqs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "nand_ce2", "nand_ce3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const char * const nor_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "nor_d", "nor_q", "nor_c", "nor_cs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const char * const pwm_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "pwm_a_y", "pwm_a_z0", "pwm_a_z7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const char * const pwm_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "pwm_b_x", "pwm_b_z"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const char * const pwm_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const char * const pwm_d_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "pwm_d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const char * const pwm_e_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "pwm_e"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const char * const sd_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "sd_d3_b", "sd_d2_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const char * const sdxc_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const char * const spdif_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "spdif_in", "spdif_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const char * const uart_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const char * const remote_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "remote_input", "remote_output_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const char * const i2c_slave_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "i2c_slave_sck_ao", "i2c_slave_sda_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const char * const uart_ao_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const char * const i2c_mst_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "i2c_mst_sck_ao", "i2c_mst_sda_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const char * const pwm_f_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "pwm_f_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const char * const i2s_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "i2s_out_ch01_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const char * const hdmi_cec_ao_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "hdmi_cec_ao"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct meson_pmx_func meson8_cbus_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) FUNCTION(gpio_periphs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) FUNCTION(sd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FUNCTION(sdxc_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) FUNCTION(pcm_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FUNCTION(uart_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) FUNCTION(uart_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) FUNCTION(iso7816),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) FUNCTION(i2c_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FUNCTION(xtal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) FUNCTION(uart_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) FUNCTION(pcm_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) FUNCTION(i2c_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FUNCTION(dvin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) FUNCTION(enc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) FUNCTION(vga),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) FUNCTION(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) FUNCTION(spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) FUNCTION(ethernet),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) FUNCTION(i2c_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) FUNCTION(i2c_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) FUNCTION(sd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) FUNCTION(sdxc_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) FUNCTION(nor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) FUNCTION(sd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) FUNCTION(sdxc_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) FUNCTION(pwm_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) FUNCTION(pwm_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) FUNCTION(pwm_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) FUNCTION(pwm_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) FUNCTION(pwm_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) FUNCTION(i2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static struct meson_pmx_func meson8_aobus_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) FUNCTION(gpio_aobus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) FUNCTION(uart_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) FUNCTION(remote),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) FUNCTION(i2c_slave_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) FUNCTION(uart_ao_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) FUNCTION(i2c_mst_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) FUNCTION(pwm_f_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) FUNCTION(i2s_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) FUNCTION(hdmi_cec_ao),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static struct meson_bank meson8_cbus_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* name first last irq pullen pull dir out in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct meson_bank meson8_aobus_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* name first last irq pullen pull dir out in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .name = "cbus-banks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .pins = meson8_cbus_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .groups = meson8_cbus_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .funcs = meson8_cbus_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .banks = meson8_cbus_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .num_pins = ARRAY_SIZE(meson8_cbus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .num_groups = ARRAY_SIZE(meson8_cbus_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .num_banks = ARRAY_SIZE(meson8_cbus_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .pmx_ops = &meson8_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .name = "ao-bank",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .pins = meson8_aobus_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .groups = meson8_aobus_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .funcs = meson8_aobus_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .banks = meson8_aobus_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .num_pins = ARRAY_SIZE(meson8_aobus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .num_groups = ARRAY_SIZE(meson8_aobus_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .num_banks = ARRAY_SIZE(meson8_aobus_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .pmx_ops = &meson8_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .parse_dt = &meson8_aobus_parse_dt_extra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct of_device_id meson8_pinctrl_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .compatible = "amlogic,meson8-cbus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .data = &meson8_cbus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .compatible = "amlogic,meson8-aobus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .data = &meson8_aobus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .compatible = "amlogic,meson8m2-cbus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .data = &meson8_cbus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .compatible = "amlogic,meson8m2-aobus-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .data = &meson8_aobus_pinctrl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static struct platform_driver meson8_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .probe = meson_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = "meson8-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .of_match_table = meson8_pinctrl_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) builtin_platform_driver(meson8_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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