^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * bindings for MediaTek SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Zhiyong Tao <zhiyong.tao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-paris.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Custom pinconf parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct pinconf_generic_params mtk_custom_bindings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct pin_config_item mtk_conf_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const mtk_gpio_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "func0", "func1", "func2", "func3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "func4", "func5", "func6", "func7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "func8", "func9", "func10", "func11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "func12", "func13", "func14", "func15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) hw->soc->gpio_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int pin, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* hardware would take 0 as input direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int pullup, err, reg, ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (pin >= hw->soc->npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (hw->soc->bias_get_combo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret == MTK_PUPD_SET_R1R0_00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = MTK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (param == PIN_CONFIG_BIAS_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret != MTK_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!pullup || ret == MTK_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (pullup || ret == MTK_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* CONFIG Current direction return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * ------------- ----------------- ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * OUTPUT_ENABLE output 1 (= HW value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * input 0 (= HW value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * INPUT_ENABLE output 0 (= reverse HW value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * input 1 (= reverse HW value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (param == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = !ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* return error when in output mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * because schmitt trigger only work in input mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (hw->soc->drive_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = hw->soc->drive_get(hw, desc, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case MTK_PIN_CONFIG_TDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case MTK_PIN_CONFIG_RDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg = (param == MTK_PIN_CONFIG_TDSEL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) err = mtk_hw_get_value(hw, desc, reg, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case MTK_PIN_CONFIG_PU_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case MTK_PIN_CONFIG_PD_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (hw->soc->adv_pull_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pullup = param == MTK_PIN_CONFIG_PU_ADV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case MTK_PIN_CONFIG_DRV_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (hw->soc->adv_drive_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = hw->soc->adv_drive_get(hw, desc, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *config = pinconf_to_config_packed(param, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum pin_config_param param, u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (pin >= hw->soc->npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) switch ((u32)param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (hw->soc->bias_set_combo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (hw->soc->bias_set_combo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err = hw->soc->bias_set_combo(hw, desc, 1, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (hw->soc->bias_set_combo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err = hw->soc->bias_set_combo(hw, desc, 0, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MTK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Keep set direction to consider the case that a GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * does not have SMT control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (err != -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MTK_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* regard all non-zero value as enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MTK_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* regard all non-zero value as enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MTK_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case PIN_CONFIG_INPUT_SCHMITT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* arg = 1: Input mode & SMT enable ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * arg = 0: Output mode & SMT disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (hw->soc->drive_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err = hw->soc->drive_set(hw, desc, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case MTK_PIN_CONFIG_TDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case MTK_PIN_CONFIG_RDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) reg = (param == MTK_PIN_CONFIG_TDSEL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err = mtk_hw_set_value(hw, desc, reg, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case MTK_PIN_CONFIG_PU_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case MTK_PIN_CONFIG_PD_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (hw->soc->adv_pull_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bool pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pullup = param == MTK_PIN_CONFIG_PU_ADV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err = hw->soc->adv_pull_set(hw, desc, pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case MTK_PIN_CONFIG_DRV_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (hw->soc->adv_drive_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err = hw->soc->adv_drive_set(hw, desc, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct mtk_pinctrl_group *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; i < hw->soc->ngrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mtk_pinctrl_group *grp = hw->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (grp->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct mtk_func_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const struct mtk_func_desc *func = pin->funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (func->muxval == fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (i = 0; i < hw->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct mtk_pin_desc *pin = hw->soc->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (pin->number == pin_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct mtk_func_desc *func = pin->funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (func->muxval == fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 pin, u32 fnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mtk_pinctrl_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (*map)[*num_maps].data.mux.group = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(pctl->dev, "invalid function %d on pin %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fnum, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int num_pins, num_funcs, maps_per_pin, i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mtk_pinctrl_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) bool has_config = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 pinfunc, pin, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct property *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned reserve = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pins = of_find_property(node, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(hw->dev, "missing pins property in node %pOFn .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) has_config = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) num_pins = pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) num_funcs = num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) maps_per_pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (num_funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (has_config && num_pins >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!num_pins || !maps_per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reserve = num_pins * maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pin = MTK_GET_PIN_NO(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) func = MTK_GET_PIN_FUNC(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (pin >= hw->soc->npins ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) func >= ARRAY_SIZE(mtk_gpio_functions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(hw->dev, "invalid pins value.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) grp = mtk_pctrl_find_group_by_pin(hw, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(hw->dev, "unable to match pin %d to group\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (has_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) err = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) grp->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return hw->soc->ngrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return hw->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned group, const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) *pins = (unsigned *)&hw->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) err = mtk_hw_get_value(hw, desc, field, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define mtk_pctrl_get_pinmux(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define mtk_pctrl_get_direction(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define mtk_pctrl_get_out(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define mtk_pctrl_get_in(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define mtk_pctrl_get_smt(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define mtk_pctrl_get_ies(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define mtk_pctrl_get_driving(hw, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int gpio, char *buf, unsigned int bufLen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (mtk_is_virt_gpio(hw, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pinmux = mtk_pctrl_get_pinmux(hw, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (pinmux >= hw->soc->nfuncs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pinmux -= hw->soc->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (pullen == MTK_PUPD_SET_R1R0_00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pullen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) r1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) r0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } else if (pullen == MTK_PUPD_SET_R1R0_01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pullen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) r1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) r0 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else if (pullen == MTK_PUPD_SET_R1R0_10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pullen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) r1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) r0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } else if (pullen == MTK_PUPD_SET_R1R0_11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pullen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) r1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) r0 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pullen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) len += scnprintf(buf + len, bufLen - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pinmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mtk_pctrl_get_direction(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mtk_pctrl_get_out(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mtk_pctrl_get_in(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mtk_pctrl_get_driving(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mtk_pctrl_get_smt(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mtk_pctrl_get_ies(hw, gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pullen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pullup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (r1 != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) len += scnprintf(buf + len, bufLen - len, " (%1d %1d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) r1, r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) len += scnprintf(buf + len, bufLen - len, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PIN_DBG_BUF_SZ 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) char buf[PIN_DBG_BUF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) seq_printf(s, "%s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct pinctrl_ops mtk_pctlops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .dt_node_to_map = mtk_pctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .get_groups_count = mtk_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .get_group_name = mtk_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .get_group_pins = mtk_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .pin_dbg_show = mtk_pctrl_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ARRAY_SIZE(mtk_gpio_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return mtk_gpio_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) *groups = hw->grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *num_groups = hw->soc->ngrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct mtk_pinctrl_group *grp = hw->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) const struct mtk_func_desc *desc_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(hw->dev, "invalid function %d on group %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) function, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!desc_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const struct pinmux_ops mtk_pmxops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .get_functions_count = mtk_pmx_get_funcs_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .get_function_name = mtk_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .get_function_groups = mtk_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .set_mux = mtk_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .gpio_set_direction = mtk_pinmux_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .gpio_request_enable = mtk_pinmux_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct mtk_pinctrl_group *grp = &hw->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* One pin per group only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return mtk_pinconf_get(pctldev, grp->pin, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct mtk_pinctrl_group *grp = &hw->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = mtk_pinconf_set(pctldev, grp->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pinconf_to_config_param(configs[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pinconf_to_config_argument(configs[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct pinconf_ops mtk_confops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .pin_config_get = mtk_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .pin_config_group_get = mtk_pconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .pin_config_group_set = mtk_pconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct pinctrl_desc mtk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .name = PINCTRL_PINCTRL_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .pctlops = &mtk_pctlops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .pmxops = &mtk_pmxops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .confops = &mtk_confops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * "Virtual" GPIOs are always and only used for interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Since they are only used for interrupts, they are always inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (mtk_is_virt_gpio(hw, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return pinctrl_gpio_direction_input(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (gpio >= hw->soc->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mtk_gpio_set(chip, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return pinctrl_gpio_direction_output(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!hw->eint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (desc->eint.eint_n == EINT_NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!hw->eint ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) desc->eint.eint_n == EINT_NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct gpio_chip *chip = &hw->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) chip->label = PINCTRL_PINCTRL_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) chip->parent = hw->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) chip->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) chip->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) chip->get_direction = mtk_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) chip->direction_input = mtk_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) chip->direction_output = mtk_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) chip->get = mtk_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) chip->set = mtk_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) chip->to_irq = mtk_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) chip->set_config = mtk_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) chip->ngpio = hw->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) chip->of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = gpiochip_add_data(chip, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static int mtk_pctrl_build_state(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Allocate groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) sizeof(*hw->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!hw->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* We assume that one pin is one group, use pin name as group name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) sizeof(*hw->grp_names), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!hw->grp_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) for (i = 0; i < hw->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) const struct mtk_pin_desc *pin = hw->soc->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct mtk_pinctrl_group *group = hw->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) group->name = pin->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) group->pin = pin->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) hw->grp_names[i] = pin->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int mtk_paris_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) const struct mtk_pin_soc *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct mtk_pinctrl *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) hw->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) hw->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (!hw->soc->nbase_names) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "SoC should be assigned at least one register base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sizeof(*hw->base), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!hw->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) for (i = 0; i < hw->soc->nbase_names; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) hw->soc->base_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (IS_ERR(hw->base[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return PTR_ERR(hw->base[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) hw->nbase = hw->soc->nbase_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) err = mtk_pctrl_build_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_err(&pdev->dev, "build state failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Copy from internal struct mtk_pin_desc to register to the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) for (i = 0; i < hw->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pins[i].number = hw->soc->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pins[i].name = hw->soc->pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Setup pins descriptions per SoC types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mtk_desc.npins = hw->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) mtk_desc.custom_params = mtk_custom_bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mtk_desc.custom_conf_items = mtk_conf_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) &hw->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) err = pinctrl_enable(hw->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) err = mtk_build_eint(hw, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "Failed to add EINT, but pinctrl still can work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Build gpiochip should be after pinctrl_enable is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) err = mtk_build_gpiochip(hw, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(&pdev->dev, "Failed to add gpio_chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static int mtk_paris_pinctrl_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct mtk_pinctrl *pctl = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return mtk_eint_do_suspend(pctl->eint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int mtk_paris_pinctrl_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct mtk_pinctrl *pctl = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return mtk_eint_do_resume(pctl->eint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .suspend_noirq = mtk_paris_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .resume_noirq = mtk_paris_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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