Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __PINCTRL_MTK_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __PINCTRL_MTK_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "mtk-eint.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define NO_EINT_SUPPORT    255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MT_EDGE_SENSITIVE           0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MT_LEVEL_SENSITIVE          1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define EINT_DBNC_SET_DBNC_BITS     4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define EINT_DBNC_RST_BIT           (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define EINT_DBNC_SET_EN            (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MTK_PINCTRL_NOT_SUPPORT	(0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct mtk_desc_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned char muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct mtk_desc_eint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned char eintmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned char eintnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct mtk_desc_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct pinctrl_pin_desc	pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	const struct mtk_desc_eint eint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	const struct mtk_desc_function	*functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MTK_PIN(_pin, _pad, _chip, _eint, ...)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.pin = _pin,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.eint = _eint,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.functions = (struct mtk_desc_function[]){	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			__VA_ARGS__, { } },			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MTK_EINT_FUNCTION(_eintmux, _eintnum)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.eintmux = _eintmux,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.eintnum = _eintnum,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MTK_FUNCTION(_val, _name)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.muxval = _val,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SET_ADDR(x, y)  (x + (y->devdata->port_align))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLR_ADDR(x, y)  (x + (y->devdata->port_align << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct mtk_pinctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned long	config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned	pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * struct mtk_drv_group_desc - Provide driving group data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * @max_drv: The maximum current of this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * @min_drv: The minimum current of this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * @low_bit: The lowest bit of this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @high_bit: The highest bit of this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @step: The step current of this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct mtk_drv_group_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned char min_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned char max_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned char low_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned char high_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned char step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MTK_DRV_GRP(_min, _max, _low, _high, _step)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.min_drv = _min,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.max_drv = _max,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.low_bit = _low,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.high_bit = _high,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.step = _step,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * struct mtk_pin_drv_grp - Provide each pin driving info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * @pin: The pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * @offset: The offset of driving register for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @bit: The bit of driving register for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @grp: The group for this pin belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mtk_pin_drv_grp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned short pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned char grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.pin = _pin,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.offset = _offset,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.bit = _bit,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.grp = _grp,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * struct mtk_pin_spec_pupd_set_samereg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * - For special pins' pull up/down setting which resides in same register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * @pin: The pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * @offset: The offset of special pull up/down setting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * @pupd_bit: The pull up/down bit in this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @r0_bit: The r0 bit of pull resistor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @r1_bit: The r1 bit of pull resistor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mtk_pin_spec_pupd_set_samereg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned short pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned char pupd_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned char r1_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned char r0_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.pin = _pin,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.offset = _offset,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.pupd_bit = _pupd,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.r1_bit = _r1,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.r0_bit = _r0,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * struct mtk_pin_ies_set - For special pins' ies and smt setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * @start: The start pin number of those special pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @end: The end pin number of those special pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * @offset: The offset of special setting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * @bit: The bit of special setting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mtk_pin_ies_smt_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned short start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned short end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.start = _start,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.end = _end,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.bit = _bit,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.offset = _offset,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mtk_eint_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int  stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int  ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int  mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int  mask_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned int  mask_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned int  sens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned int  sens_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned int  sens_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned int  soft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned int  soft_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned int  soft_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned int  pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned int  pol_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned int  pol_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned int  dom_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned int  dbnc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned int  dbnc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int  dbnc_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u8  port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8  ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * @pins: An array describing all pins the pin controller affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * @npins: The number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * @grp_desc: The driving group info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * @pin_drv_grp: The driving group for all pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *  these pins' pull setting are very different, they have separate pull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *  up/down bit, R0 and R1 resistor bit, so they need special pull setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *  If special setting is success, this should return 0, otherwise it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *  return non-zero value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * @spec_ies_smt_set: Some pins are irregular, their input enable and smt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * control register are discontinuous, but they are mapping together. That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * means when user set smt, input enable is set at the same time. So they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * also need special control. If special control is success, this should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * return 0, otherwise return non-zero value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * @spec_pinmux_set: In some cases, there are two pinmux functions share
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * the same value in the same segment of pinmux control register. If user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * want to use one of the two functions, they need an extra bit setting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * select the right one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * @spec_dir_set: In very few SoCs, direction control registers are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * arranged continuously, they may be cut to parts. So they need special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * dir setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @dir_offset: The direction register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * @pullen_offset: The pull-up/pull-down enable register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * @pinmux_offset: The pinmux register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * @type1_start: Some chips have two base addresses for pull select register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *  that means some pins use the first address and others use the second. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *  member record the start of pin number to use the second address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * @type1_end: The end of pin number to use the second address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * @port_shf: The shift between two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * @port_mask: The mask of register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * @port_align: Provide clear register and set register step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct mtk_pinctrl_devdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	const struct mtk_desc_pin	*pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int				npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	const struct mtk_drv_group_desc	*grp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	unsigned int	n_grp_cls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	const struct mtk_pin_drv_grp	*pin_drv_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned int	n_pin_drv_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			unsigned char align, bool isup, unsigned int arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			unsigned char align, int value, enum pin_config_param arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			unsigned int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned int dir_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned int ies_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned int smt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned int pullen_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned int pullsel_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned int drv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	unsigned int dout_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int din_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int pinmux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned short type1_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned short type1_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned char  port_shf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	unsigned char  port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unsigned char  port_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct mtk_eint_hw eint_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct mtk_eint_regs *eint_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct mtk_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct regmap	*regmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct regmap	*regmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct device           *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct gpio_chip	*chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct mtk_pinctrl_group	*groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	unsigned			ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	const char          **grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct pinctrl_dev      *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	const struct mtk_pinctrl_devdata  *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct mtk_eint *eint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int mtk_pctrl_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		const struct mtk_pinctrl_devdata *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		struct regmap *regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		unsigned int info_num, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		unsigned char align, bool isup, unsigned int r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		unsigned int pin, unsigned char align, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern const struct dev_pm_ops mtk_eint_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif /* __PINCTRL_MTK_COMMON_H */