^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "mtk-eint.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_GPIO_MODE_PER_REG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO_MODE_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPIO_MODE_PREFIX "GPIO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char * const mtk_gpio_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "func0", "func1", "func2", "func3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "func4", "func5", "func6", "func7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "func8", "func9", "func10", "func11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "func12", "func13", "func14", "func15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * There are two base address for pull related configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * in mt8135, and different GPIO pins use different base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * When pin number greater than type1_start and less than type1_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * should use the second base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return pctl->regmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return pctl->regmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Different SoC has different mask and port shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ((pin >> 4) & pctl->devdata->port_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) << pctl->devdata->port_shf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct pinctrl_gpio_range *range, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bit = BIT(offset & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (pctl->devdata->spec_dir_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pctl->devdata->spec_dir_set(®_addr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Different SoC has different alignment offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg_addr = CLR_ADDR(reg_addr, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg_addr = SET_ADDR(reg_addr, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bit = BIT(offset & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg_addr = SET_ADDR(reg_addr, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg_addr = CLR_ADDR(reg_addr, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int value, enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int reg_addr, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Due to some soc are not support ies/smt config, add this special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * control to handle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!pctl->devdata->spec_ies_smt_set &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!pctl->devdata->spec_ies_smt_set &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Due to some pins are irregular, their input enable and smt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * control register are discontinuous, so we need this special handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (pctl->devdata->spec_ies_smt_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pin, pctl->devdata->port_align, value, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bit = BIT(pin & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) offset = pctl->devdata->ies_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) offset = pctl->devdata->smt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int pin, unsigned char align, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int i, reg_addr, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 0; i < info_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (pin >= ies_smt_infos[i].start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pin <= ies_smt_infos[i].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (i == info_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg_addr = ies_smt_infos[i].offset + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg_addr = ies_smt_infos[i].offset + (align << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bit = BIT(ies_smt_infos[i].bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) regmap_write(regmap, reg_addr, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mtk_pinctrl *pctl, unsigned long pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const struct mtk_pin_drv_grp *pin_drv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pctl->devdata->pin_drv_grp + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (pin == pin_drv->pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return pin_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int pin, unsigned char driving)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const struct mtk_pin_drv_grp *pin_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int bits, mask, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const struct mtk_drv_group_desc *drv_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (pin >= pctl->devdata->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) && !(driving % drv_grp->step)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = driving / drv_grp->step - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bits = drv_grp->high_bit - drv_grp->low_bit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mask = BIT(bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) shift = pin_drv->bit + drv_grp->low_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mask <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return regmap_update_bits(mtk_get_regmap(pctl, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pin_drv->offset, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int info_num, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned char align, bool isup, unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int reg_pupd, reg_set, reg_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int bit_pupd, bit_r0, bit_r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bool find = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < info_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (pin == pupd_infos[i].pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) find = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!find)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spec_pupd_pin = pupd_infos + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg_set = spec_pupd_pin->offset + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) reg_rst = spec_pupd_pin->offset + (align << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (isup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg_pupd = reg_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg_pupd = reg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bit_pupd = BIT(spec_pupd_pin->pupd_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_write(regmap, reg_pupd, bit_pupd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bit_r0 = BIT(spec_pupd_pin->r0_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bit_r1 = BIT(spec_pupd_pin->r1_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (r1r0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case MTK_PUPD_SET_R1R0_00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regmap_write(regmap, reg_rst, bit_r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_write(regmap, reg_rst, bit_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case MTK_PUPD_SET_R1R0_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regmap_write(regmap, reg_set, bit_r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) regmap_write(regmap, reg_rst, bit_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case MTK_PUPD_SET_R1R0_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) regmap_write(regmap, reg_rst, bit_r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) regmap_write(regmap, reg_set, bit_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case MTK_PUPD_SET_R1R0_11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) regmap_write(regmap, reg_set, bit_r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_write(regmap, reg_set, bit_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int pin, bool enable, bool isup, unsigned int arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int reg_pullen, reg_pullsel, r1r0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Some pins' pull setting are very different,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * they have separate pull up/down bit, R0 and R1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * resistor bit, so we need this special handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pctl->devdata->spec_pull_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* For special pins, bias-disable is set by R1R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * the parameter should be "MTK_PUPD_SET_R1R0_00".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pin, pctl->devdata->port_align, isup, r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* For generic pull config, default arg value should be 0 or 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (arg != 0 && arg != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) arg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bit = BIT(pin & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pctl->devdata->pullen_offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pctl->devdata->pullen_offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (isup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pctl->devdata->pullsel_offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pctl->devdata->pullsel_offset, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int pin, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mtk_gpio_set(pctl->chip, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = mtk_pconf_set_driving(pctl, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *config = pctl->groups[group].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct mtk_pinctrl_group *g = &pctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = mtk_pconf_parse_conf(pctldev, g->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pinconf_to_config_param(configs[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pinconf_to_config_argument(configs[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) g->config = configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct pinconf_ops mtk_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pin_config_group_get = mtk_pconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .pin_config_group_set = mtk_pconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct mtk_pinctrl_group *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (i = 0; i < pctl->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct mtk_pinctrl_group *grp = pctl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (grp->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const struct mtk_desc_function *func = pin->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (func->muxval == fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 pin_num, u32 fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (i = 0; i < pctl->devdata->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (pin->pin.number == pin_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) const struct mtk_desc_function *func =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pin->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (func->muxval == fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct pinctrl_map **map, unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) (*map)[*num_maps].data.mux.group = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(pctl->dev, "invalid function %d on pin %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fnum, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct property *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 pinfunc, pin, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int num_pins, num_funcs, maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool has_config = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned reserve = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct mtk_pinctrl_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pins = of_find_property(node, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) has_config = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) num_pins = pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) num_funcs = num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) maps_per_pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (num_funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (has_config && num_pins >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!num_pins || !maps_per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reserve = num_pins * maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) err = pinctrl_utils_reserve_map(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) reserved_maps, num_maps, reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) err = of_property_read_u32_index(node, "pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) i, &pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pin = MTK_GET_PIN_NO(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) func = MTK_GET_PIN_FUNC(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (pin >= pctl->devdata->npins ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) func >= ARRAY_SIZE(mtk_gpio_functions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(pctl->dev, "invalid pins value.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) grp = mtk_pctrl_find_group_by_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(pctl->dev, "unable to match pin %d to group\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (has_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) err = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) reserved_maps, num_maps, grp->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) configs, num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return pctl->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *pins = (unsigned *)&pctl->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct pinctrl_ops mtk_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .dt_node_to_map = mtk_pctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .get_groups_count = mtk_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .get_group_name = mtk_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .get_group_pins = mtk_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ARRAY_SIZE(mtk_gpio_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return mtk_gpio_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *groups = pctl->grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *num_groups = pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned long pin, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned int reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (pctl->devdata->spec_pinmux_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pin, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) + pctl->devdata->pinmux_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mode &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) bit = pin % MAX_GPIO_MODE_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mask <<= (GPIO_MODE_BITS * bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = (mode << (GPIO_MODE_BITS * bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return regmap_update_bits(mtk_get_regmap(pctl, pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reg_addr, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct mtk_desc_pin *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = 0; i < pctl->devdata->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pin = pctl->devdata->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (pin->eint.eintnum == eint_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) const struct mtk_desc_function *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mtk_pinctrl_group *g = pctl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(pctl->dev, "invalid function %d on group %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) function, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) const struct mtk_desc_function *func = pin->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!strncmp(func->name, GPIO_MODE_PREFIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) sizeof(GPIO_MODE_PREFIX)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return func->muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) muxval = mtk_pmx_find_gpio_mode(pctl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (muxval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mtk_pmx_set_mode(pctldev, offset, muxval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const struct pinmux_ops mtk_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .get_functions_count = mtk_pmx_get_funcs_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .get_function_name = mtk_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .get_function_groups = mtk_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .set_mux = mtk_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .gpio_set_direction = mtk_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .gpio_request_enable = mtk_pmx_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int mtk_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int mtk_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mtk_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned int reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unsigned int read_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bit = BIT(offset & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (pctl->devdata->spec_dir_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pctl->devdata->spec_dir_set(®_addr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) regmap_read(pctl->regmap1, reg_addr, &read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (read_val & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) unsigned int reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned int read_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) reg_addr = mtk_get_port(pctl, offset) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pctl->devdata->din_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) bit = BIT(offset & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) regmap_read(pctl->regmap1, reg_addr, &read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return !!(read_val & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned long eint_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pin = pctl->devdata->pins + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (pin->eint.eintnum == NO_EINT_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) eint_n = pin->eint.eintnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return mtk_eint_find_irq(pctl->eint, eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned long eint_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pin = pctl->devdata->pins + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (pin->eint.eintnum == NO_EINT_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) eint_n = pin->eint.eintnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct gpio_chip mtk_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .get_direction = mtk_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .direction_input = mtk_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .direction_output = mtk_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .get = mtk_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .set = mtk_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .to_irq = mtk_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .set_config = mtk_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .of_gpio_n_cells = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int mtk_eint_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct mtk_pinctrl *pctl = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return mtk_eint_do_suspend(pctl->eint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int mtk_eint_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct mtk_pinctrl *pctl = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return mtk_eint_do_resume(pctl->eint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) const struct dev_pm_ops mtk_eint_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .suspend_noirq = mtk_eint_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .resume_noirq = mtk_eint_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int mtk_pctrl_build_state(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pctl->ngroups = pctl->devdata->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Allocate groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) sizeof(*pctl->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!pctl->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* We assume that one pin is one group, use pin name as group name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) sizeof(*pctl->grp_names), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!pctl->grp_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) for (i = 0; i < pctl->devdata->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct mtk_pinctrl_group *group = pctl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) group->name = pin->pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) group->pin = pin->pin.number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pctl->grp_names[i] = pin->pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct gpio_chip **gpio_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pin = mtk_find_pin_by_eint_num(pctl, eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) *gpio_chip = pctl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *gpio_n = pin->pin.number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pin = mtk_find_pin_by_eint_num(pctl, eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return mtk_gpio_get(pctl->chip, pin->pin.number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) const struct mtk_desc_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pin = mtk_find_pin_by_eint_num(pctl, eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* set mux to INT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* set gpio direction to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* set input-enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PIN_CONFIG_INPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const struct mtk_eint_xt mtk_eint_xt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .get_gpio_n = mtk_xt_get_gpio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .get_gpio_state = mtk_xt_get_gpio_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!of_property_read_bool(np, "interrupt-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!pctl->eint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (IS_ERR(pctl->eint->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return PTR_ERR(pctl->eint->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pctl->eint->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!pctl->eint->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) pctl->eint->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * If pctl->eint->regs == NULL, it would fall back into using a generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * register map in mtk_eint_do_init calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pctl->eint->regs = pctl->devdata->eint_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pctl->eint->hw = &pctl->devdata->eint_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pctl->eint->pctl = pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pctl->eint->gpio_xlate = &mtk_eint_xt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return mtk_eint_do_init(pctl->eint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int mtk_pctrl_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) const struct mtk_pinctrl_devdata *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct mtk_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct device_node *np = pdev->dev.of_node, *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) platform_set_drvdata(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) prop = of_find_property(np, "pins-are-numbered", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(&pdev->dev, "only support pins-are-numbered format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pctl->regmap1 = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (IS_ERR(pctl->regmap1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return PTR_ERR(pctl->regmap1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) } else if (regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pctl->regmap1 = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Only 8135 has two base addr, other SoCs have only one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) pctl->regmap2 = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (IS_ERR(pctl->regmap2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return PTR_ERR(pctl->regmap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pctl->devdata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = mtk_pctrl_build_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(&pdev->dev, "build state failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < pctl->devdata->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pins[i] = pctl->devdata->pins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pctl->pctl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) pctl->pctl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pctl->pctl_desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pctl->pctl_desc.npins = pctl->devdata->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pctl->pctl_desc.confops = &mtk_pconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pctl->pctl_desc.pmxops = &mtk_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (IS_ERR(pctl->pctl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return PTR_ERR(pctl->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (!pctl->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *pctl->chip = mtk_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pctl->chip->ngpio = pctl->devdata->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pctl->chip->label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pctl->chip->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pctl->chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = gpiochip_add_data(pctl->chip, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Register the GPIO to pin mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) 0, 0, pctl->devdata->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) goto chip_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = mtk_eint_init(pctl, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto chip_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) chip_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) gpiochip_remove(pctl->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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