^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __PINCTRL_MTK_COMMON_V2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __PINCTRL_MTK_COMMON_V2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MTK_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MTK_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MTK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MTK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MTK_PULLDOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MTK_PULLUP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EINT_NA U16_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NO_EINT_SUPPORT EINT_NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) _s_bit, _x_bits, _sz_reg, _fixed) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .s_pin = _s_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .e_pin = _e_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .i_base = _i_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .s_addr = _s_addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .x_addrs = _x_addrs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .s_bit = _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .x_bits = _x_bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .sz_reg = _sz_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fixed = _fixed, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) _x_bits, 32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) _x_bits, 32, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* List these attributes which could be modified for the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN_REG_DI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN_REG_DO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN_REG_SMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN_REG_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN_REG_PU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN_REG_E4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN_REG_E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN_REG_TDSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN_REG_RDSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN_REG_DRV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN_REG_PUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN_REG_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN_REG_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN_REG_IES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN_REG_PULLEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN_REG_PULLSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN_REG_DRV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN_REG_DRV_E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN_REG_DRV_E1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Group the pins by the driving current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DRV_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DRV_GRP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DRV_GRP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DRV_GRP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DRV_GRP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DRV_GRP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DRV_GRP_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const mtk_default_register_base_names[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* struct mtk_pin_field - the structure that holds the information of the field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * used to describe the attribute for the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @base: the index pointing to the entry in base address list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @offset: the register offset relative to the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @mask: the mask used to filter out the field from the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @bitpos: the start bit relative to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @next: the indication that the field would be extended to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) next register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mtk_pin_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 bitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* struct mtk_pin_field_calc - the structure that holds the range providing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * the guide used to look up the relevant field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @s_pin: the start pin within the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @e_pin: the end pin within the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @i_base: the index pointing to the entry in base address list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @s_addr: the start address for the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @x_addrs: the address distance between two consecutive registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * within the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @s_bit: the start bit for the first register within the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @x_bits: the bit distance between two consecutive pins within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @sz_reg: the size of bits in a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @fixed: the consecutive pins share the same bits with the 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mtk_pin_field_calc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 s_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 e_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 i_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 s_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 x_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 s_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 x_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 sz_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* struct mtk_pin_reg_calc - the structure that holds all ranges used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * determine which register the pin would make use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * for certain pin attribute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @range: the start address for the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @nranges: the number of items in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mtk_pin_reg_calc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct mtk_pin_field_calc *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int nranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * struct mtk_func_desc - the structure that providing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * all the funcs for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @name: the name of function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @muxval: the mux to the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mtk_func_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * struct mtk_eint_desc - the structure that providing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * for eint data per pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @eint_m: the eint mux for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @eitn_n: the eint number for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mtk_eint_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 eint_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 eint_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * struct mtk_pin_desc - the structure that providing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * for each pin of chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @number: unique pin number from the global pin number space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @name: name for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @eint: the eint data for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @drv_n: the index with the driving group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @funcs: all available functions for this pins (only used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * those drivers compatible to pinctrl-mtk-common.c-like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * ones)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct mtk_pin_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct mtk_eint_desc eint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 drv_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct mtk_func_desc *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mtk_pinctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mtk_pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* struct mtk_pin_soc - the structure that holds SoC-specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mtk_pin_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct mtk_pin_reg_calc *reg_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const struct mtk_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const struct group_desc *grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int ngrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const struct function_desc *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const struct mtk_eint_regs *eint_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct mtk_eint_hw *eint_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Specific parameters per SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 gpio_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool ies_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char * const *base_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int nbase_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Specific pinconfig operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int (*bias_disable_set)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct mtk_pin_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int (*bias_disable_get)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct mtk_pin_desc *desc, int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int (*bias_set)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const struct mtk_pin_desc *desc, bool pullup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int (*bias_get)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct mtk_pin_desc *desc, bool pullup, int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int (*bias_set_combo)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct mtk_pin_desc *desc, u32 pullup, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int (*bias_get_combo)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const struct mtk_pin_desc *desc, u32 *pullup, u32 *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int (*drive_set)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int (*drive_get)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct mtk_pin_desc *desc, int *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int (*adv_pull_set)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int (*adv_pull_get)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int (*adv_drive_set)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int (*adv_drive_get)(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct mtk_pin_desc *desc, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Specific driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mtk_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct pinctrl_dev *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void __iomem **base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 nbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct mtk_pin_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mtk_eint *eint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct mtk_pinctrl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const char **grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int field, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int field, int *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const struct mtk_pin_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct mtk_pin_desc *desc, int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct mtk_pin_desc *desc, bool pullup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct mtk_pin_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const struct mtk_pin_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct mtk_pin_desc *desc, bool pullup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct mtk_pin_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 pullup, u32 enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const struct mtk_pin_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 *pullup, u32 *enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const struct mtk_pin_desc *desc, int *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) const struct mtk_pin_desc *desc, int *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const struct mtk_pin_desc *desc, int *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const struct mtk_pin_desc *desc, bool pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct mtk_pin_desc *desc, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct mtk_pin_desc *desc, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif /* __PINCTRL_MTK_COMMON_V2_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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