^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pinctrl-mtk-mt8173.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_BASE 0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned char align, bool isup, unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char align, int value, enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ARRAY_SIZE(mt8173_ies_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ARRAY_SIZE(mt8173_smt_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* 0E4E8SR 4/8/12/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MTK_DRV_GRP(4, 16, 1, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* 0E2E4SR 2/4/6/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MTK_DRV_GRP(2, 8, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* E8E4E2 2/4/6/8/10/12/14/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MTK_DRV_GRP(2, 16, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .pins = mtk_pins_mt8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .npins = ARRAY_SIZE(mtk_pins_mt8173),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .grp_desc = mt8173_drv_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .pin_drv_grp = mt8173_pin_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .spec_pull_set = mt8173_spec_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .spec_ies_smt_set = mt8173_ies_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .dir_offset = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .pullen_offset = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .pullsel_offset = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .dout_offset = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .din_offset = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .pinmux_offset = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .type1_start = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .type1_end = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .port_shf = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .port_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .port_align = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .port_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .ports = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .ap_num = 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .db_cnt = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mt8173_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct of_device_id mt8173_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .compatible = "mediatek,mt8173-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .probe = mt8173_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "mediatek-mt8173-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .of_match_table = mt8173_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .pm = &mtk_eint_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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